diff options
117 files changed, 12155 insertions, 1968 deletions
diff --git a/os/common/ports/MSP430X/chcore.c b/os/common/ports/MSP430X/chcore.c index 7a8d7f2..b9001b0 100644 --- a/os/common/ports/MSP430X/chcore.c +++ b/os/common/ports/MSP430X/chcore.c @@ -32,6 +32,8 @@ /* Module exported variables. */
/*===========================================================================*/
+bool __msp430x_in_isr;
+
/*===========================================================================*/
/* Module local types. */
/*===========================================================================*/
@@ -98,6 +100,11 @@ void _port_thread_start(void) { asm volatile ("mov R5, R12");
asm volatile ("call R4");
#endif
+#if defined(_CHIBIOS_RT_CONF_)
+ chThdExit(MSG_OK);
+#endif
+#if defined(_CHIBIOS_NIL_CONF_)
chSysHalt(0);
+#endif
}
/** @} */
diff --git a/os/common/ports/MSP430X/chcore.h b/os/common/ports/MSP430X/chcore.h index 09f87c4..9e1efa8 100644 --- a/os/common/ports/MSP430X/chcore.h +++ b/os/common/ports/MSP430X/chcore.h @@ -28,6 +28,8 @@ #include <msp430.h>
#include <in430.h>
+extern bool __msp430x_in_isr;
+
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
@@ -225,21 +227,27 @@ struct port_context { * @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
*/
-#define PORT_IRQ_PROLOGUE()
+#define PORT_IRQ_PROLOGUE() __msp430x_in_isr = true;
/**
* @brief IRQ epilogue code.
* @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
-#define PORT_IRQ_EPILOGUE() chSchRescheduleS()
+#define PORT_IRQ_EPILOGUE() { \
+ __msp430x_in_isr = false; \
+ _dbg_check_lock(); \
+ if (chSchIsPreemptionRequired()) \
+ chSchDoReschedule(); \
+ _dbg_check_unlock(); \
+}
/**
* @brief IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
-#define PORT_IRQ_HANDLER(id) __attribute__ ((interrupt(id))) \
+#define PORT_IRQ_HANDLER(id) __attribute__ ((interrupt(id))) \
void ISR_ ## id (void)
/**
@@ -293,7 +301,7 @@ extern "C" { * @brief Port-related initialization code.
*/
static inline void port_init(void) {
-
+ __msp430x_in_isr = false;
}
/**
@@ -328,9 +336,7 @@ static inline bool port_irq_enabled(syssts_t sts) { * @retval true running in ISR mode.
*/
static inline bool port_is_isr_context(void) {
- /* Efficiency would be enhanced by not doing this,
- * because of implementation details */
- return __get_SR_register() & GIE;
+ return __msp430x_in_isr;
}
/**
diff --git a/os/hal/boards/EXP430FR5969/board.c b/os/hal/boards/EXP430FR5969/board.c index ac48ba0..0643cce 100644 --- a/os/hal/boards/EXP430FR5969/board.c +++ b/os/hal/boards/EXP430FR5969/board.c @@ -25,11 +25,11 @@ const PALConfig pal_default_config =
{
{VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0,
- VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE},
+ VAL_IOPORT1_SEL1},
{VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0,
- VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE},
+ VAL_IOPORT2_SEL1},
{VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0,
- VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE}
+ VAL_IOPORT0_SEL1}
}; /* Set UART TX pin correctly */
#endif /* HAL_USE_PAL */
diff --git a/os/hal/boards/EXP430FR5969/board.h b/os/hal/boards/EXP430FR5969/board.h index 97103d3..3abe1cc 100644 --- a/os/hal/boards/EXP430FR5969/board.h +++ b/os/hal/boards/EXP430FR5969/board.h @@ -65,8 +65,6 @@ #define VAL_IOPORT1_REN 0xFCFE
#define VAL_IOPORT1_SEL0 0x0000
#define VAL_IOPORT1_SEL1 0x0300
-#define VAL_IOPORT1_IES 0x0000
-#define VAL_IOPORT1_IE 0x0000
/*
* Port B setup:
@@ -93,8 +91,6 @@ #define VAL_IOPORT2_REN 0xBDFF
#define VAL_IOPORT2_SEL0 0x0000
#define VAL_IOPORT2_SEL1 0x0000
-#define VAL_IOPORT2_IES 0x0000
-#define VAL_IOPORT2_IE 0x0000
/*
* Port J setup:
@@ -113,8 +109,6 @@ #define VAL_IOPORT0_REN 0x00CF
#define VAL_IOPORT0_SEL0 0x0030
#define VAL_IOPORT0_SEL1 0x0000
-#define VAL_IOPORT0_IES 0x0000
-#define VAL_IOPORT0_IE 0x0000
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
diff --git a/os/hal/boards/EXP430FR6989/board.c b/os/hal/boards/EXP430FR6989/board.c index a6836cf..475a2ea 100644 --- a/os/hal/boards/EXP430FR6989/board.c +++ b/os/hal/boards/EXP430FR6989/board.c @@ -25,17 +25,17 @@ const PALConfig pal_default_config =
{
{VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0,
- VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE},
+ VAL_IOPORT1_SEL1},
{VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0,
- VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE},
+ VAL_IOPORT2_SEL1},
{VAL_IOPORT3_OUT, VAL_IOPORT3_DIR, VAL_IOPORT3_REN, VAL_IOPORT3_SEL0,
- VAL_IOPORT3_SEL1, VAL_IOPORT3_IES, VAL_IOPORT3_IE},
+ VAL_IOPORT3_SEL1},
{VAL_IOPORT4_OUT, VAL_IOPORT4_DIR, VAL_IOPORT4_REN, VAL_IOPORT4_SEL0,
- VAL_IOPORT4_SEL1, VAL_IOPORT4_IES, VAL_IOPORT4_IE},
+ VAL_IOPORT4_SEL1},
{VAL_IOPORT5_OUT, VAL_IOPORT5_DIR, VAL_IOPORT5_REN, VAL_IOPORT5_SEL0,
- VAL_IOPORT5_SEL1, VAL_IOPORT5_IES, VAL_IOPORT5_IE},
+ VAL_IOPORT5_SEL1},
{VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0,
- VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE}
+ VAL_IOPORT0_SEL1}
}; /* Set UART TX pin correctly */
#endif /* HAL_USE_PAL */
diff --git a/os/hal/boards/EXP430FR6989/board.h b/os/hal/boards/EXP430FR6989/board.h index 83b8fbb..d5afe29 100644 --- a/os/hal/boards/EXP430FR6989/board.h +++ b/os/hal/boards/EXP430FR6989/board.h @@ -69,8 +69,6 @@ #define VAL_IOPORT1_REN 0xFFFE
#define VAL_IOPORT1_SEL0 0x0000
#define VAL_IOPORT1_SEL1 0x0000
-#define VAL_IOPORT1_IES 0x0006
-#define VAL_IOPORT1_IE 0x0006
/*
* Port B setup:
@@ -97,8 +95,6 @@ #define VAL_IOPORT2_REN 0xFFCF
#define VAL_IOPORT2_SEL0 0x0030
#define VAL_IOPORT2_SEL1 0x0000
-#define VAL_IOPORT2_IES 0x0000
-#define VAL_IOPORT2_IE 0x0000
/*
* Port C setup:
@@ -125,8 +121,6 @@ #define VAL_IOPORT3_REN 0xFFFF
#define VAL_IOPORT3_SEL0 0x0000
#define VAL_IOPORT3_SEL1 0x0000
-#define VAL_IOPORT3_IES 0x0000
-#define VAL_IOPORT3_IE 0x0000
/*
* Port D setup:
@@ -153,11 +147,9 @@ #define VAL_IOPORT4_REN 0xFFFF
#define VAL_IOPORT4_SEL0 0x0000
#define VAL_IOPORT4_SEL1 0x0000
-#define VAL_IOPORT4_IES 0x0000
-#define VAL_IOPORT4_IE 0x0000
/*
- * Port D setup:
+ * Port E setup:
*
* P9.0 - BoosterPack BP27 (input pullup)
* P9.1 - BoosterPack BP28 (input pullup)
@@ -181,8 +173,6 @@ #define VAL_IOPORT5_REN 0xFF7F
#define VAL_IOPORT5_SEL0 0x0000
#define VAL_IOPORT5_SEL1 0x0000
-#define VAL_IOPORT5_IES 0x0000
-#define VAL_IOPORT5_IE 0x0000
/*
* Port J setup:
@@ -201,8 +191,6 @@ #define VAL_IOPORT0_REN 0x00CF
#define VAL_IOPORT0_SEL0 0x0030
#define VAL_IOPORT0_SEL1 0x0000
-#define VAL_IOPORT0_IES 0x0000
-#define VAL_IOPORT0_IE 0x0000
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h index 05aeceb..0788eb7 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h @@ -587,19 +587,14 @@ PIN_OSPEED_100M(GPIOD_MEM_D0) | \ PIN_OSPEED_100M(GPIOD_MEM_D1)) -#if STM32_NAND_USE_EXT_INT -#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) -#else -#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) -#endif #define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_MEM_D2) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D3) | \ PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_OE) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_WE) | \ - NAND_RB_NWAIT_PUPDR(GPIOD_NAND_RB_NWAIT) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \ + PIN_PUPDR_FLOATING(GPIOD_NAND_RB_NWAIT) |\ + PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D13) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D14) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D15) | \ @@ -893,21 +888,16 @@ PIN_OSPEED_100M(GPIOG_PIN14) | \ PIN_OSPEED_100M(GPIOG_PIN15)) -#if STM32_NAND_USE_EXT_INT -#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) -#else -#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) -#endif #define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_MEM_A10) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A11) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A12) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A13) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A14) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A15) | \ - NAND_RB1_PUPDR(GPIOG_NAND_RB1) | \ + PIN_PUPDR_PULLUP(GPIOG_NAND_RB1) | \ PIN_PUPDR_FLOATING(GPIOG_NAND_RB2) | \ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \ + PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ PIN_PUPDR_FLOATING(GPIOG_SRAM_CS1) | \ diff --git a/os/hal/hal.mk b/os/hal/hal.mk index ce74620..f05ddbc 100644 --- a/os/hal/hal.mk +++ b/os/hal/hal.mk @@ -18,6 +18,7 @@ HALSRC += ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_msd.c
HALINC += ${CHIBIOS_CONTRIB}/os/hal/include
diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index 1518c7e..430df7c 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -67,6 +67,10 @@ #define HAL_USE_USB_HID FALSE
#endif
+#if !defined(HAL_USE_USB_MSD)
+#define HAL_USE_USB_MSD FALSE
+#endif
+
/* Abstract interfaces.*/
/* Shared headers.*/
@@ -84,6 +88,7 @@ #include "hal_crc.h"
#include "hal_eeprom.h"
#include "hal_usb_hid.h"
+#include "hal_usb_msd.h"
/*===========================================================================*/
/* Driver constants. */
diff --git a/os/hal/include/hal_crc.h b/os/hal/include/hal_crc.h index 8c4c895..d7ef10f 100644 --- a/os/hal/include/hal_crc.h +++ b/os/hal/include/hal_crc.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef _CRC_H_ -#define _CRC_H_ +#ifndef HAL_CRC_H_ +#define HAL_CRC_H_ #if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) @@ -153,6 +153,6 @@ extern "C" { #endif /* HAL_USE_CRC */ -#endif /* _CRC_H_ */ +#endif /* HAL_CRC_H_ */ /** @} */ diff --git a/os/hal/include/hal_ee24xx.h b/os/hal/include/hal_ee24xx.h index ab12fd1..00cdc95 100644 --- a/os/hal/include/hal_ee24xx.h +++ b/os/hal/include/hal_ee24xx.h @@ -4,8 +4,8 @@ The work is provided "as is" without warranty of any kind, neither express nor implied. */ -#ifndef EE24XX_H -#define EE24XX_H +#ifndef HAL_EE24XX_H +#define HAL_EE24XX_H #include "hal.h" @@ -61,4 +61,4 @@ typedef struct { #endif /* #if defined(EEPROM_USE_EE24XX) && EEPROM_USE_EE24XX */ -#endif // EE24XX_H +#endif // HAL_EE24XX_H diff --git a/os/hal/include/hal_ee25xx.h b/os/hal/include/hal_ee25xx.h index fc2ad6f..e520bd6 100644 --- a/os/hal/include/hal_ee25xx.h +++ b/os/hal/include/hal_ee25xx.h @@ -4,8 +4,8 @@ The work is provided "as is" without warranty of any kind, neither express nor implied. */ -#ifndef EE25XX_H -#define EE25XX_H +#ifndef HAL_EE25XX_H +#define HAL_EE25XX_H #include "hal.h" @@ -60,4 +60,4 @@ EepromFileStream *SPIEepromFileOpen(SPIEepromFileStream *efs, #endif /* #if defined(EEPROM_USE_EE25XX) && EEPROM_USE_EE25XX */ -#endif // EE25XX_H +#endif // HAL_EE25XX_H diff --git a/os/hal/include/hal_eeprom.h b/os/hal/include/hal_eeprom.h index cd05e14..6f53fb9 100644 --- a/os/hal/include/hal_eeprom.h +++ b/os/hal/include/hal_eeprom.h @@ -26,8 +26,8 @@ The work is provided "as is" without warranty of any kind, neither express nor implied. */ -#ifndef __EEPROM_H__ -#define __EEPROM_H__ +#ifndef HAL_EEPROM_H_ +#define HAL_EEPROM_H_ #include "ch.h" #include "hal.h" @@ -140,4 +140,4 @@ msg_t eepfs_get(void *ip); #include "hal_ee25xx.h" #endif /* #if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM */ -#endif /* __EEPROM_H__ */ +#endif /* HAL_EEPROM_H_ */ diff --git a/os/hal/include/hal_eicu.h b/os/hal/include/hal_eicu.h index d4b0ed2..8b4b07d 100644 --- a/os/hal/include/hal_eicu.h +++ b/os/hal/include/hal_eicu.h @@ -22,8 +22,8 @@ 32-bit timers and timers with single capture/compare channels. */ -#ifndef _EICU_H_ -#define _EICU_H_ +#ifndef HAL_EICU_H_ +#define HAL_EICU_H_ #if (HAL_USE_EICU == TRUE) || defined(__DOXYGEN__) @@ -186,6 +186,6 @@ extern "C" { #endif /* HAL_USE_EICU */ -#endif /* _EICU_H_ */ +#endif /* HAL_EICU_H_ */ /** @} */ diff --git a/os/hal/include/hal_nand.h b/os/hal/include/hal_nand.h index d5a1c04..ace3e5d 100644 --- a/os/hal/include/hal_nand.h +++ b/os/hal/include/hal_nand.h @@ -15,15 +15,15 @@ */ /** - * @file nand.h + * @file hal_nand.h * @brief NAND Driver macros and structures. * * @addtogroup NAND * @{ */ -#ifndef _NAND_H_ -#define _NAND_H_ +#ifndef HAL_NAND_H_ +#define HAL_NAND_H_ #if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) diff --git a/os/hal/include/hal_onewire.h b/os/hal/include/hal_onewire.h index 9fb5be2..bbaf77b 100644 --- a/os/hal/include/hal_onewire.h +++ b/os/hal/include/hal_onewire.h @@ -15,15 +15,15 @@ */ /** - * @file onewire.h + * @file hal_onewire.h * @brief 1-wire Driver macros and structures. * * @addtogroup onewire * @{ */ -#ifndef _ONEWIRE_H_ -#define _ONEWIRE_H_ +#ifndef HAL_ONEWIRE_H_ +#define HAL_ONEWIRE_H_ #if (HAL_USE_ONEWIRE == TRUE) || defined(__DOXYGEN__) @@ -59,11 +59,13 @@ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ +#if ONEWIRE_SYNTH_SEARCH_TEST && !ONEWIRE_USE_SEARCH_ROM +#error "Synthetic search rom test needs ONEWIRE_USE_SEARCH_ROM" +#endif /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ - #if !HAL_USE_PWM #error "1-wire Driver requires HAL_USE_PWM" #endif @@ -328,7 +330,6 @@ extern onewireDriver OWD1; #ifdef __cplusplus extern "C" { #endif - void onewireInit(void); void onewireObjectInit(onewireDriver *owp); void onewireStart(onewireDriver *owp, const onewireConfig *config); void onewireStop(onewireDriver *owp); @@ -352,7 +353,7 @@ extern "C" { #endif /* HAL_USE_ONEWIRE */ -#endif /* _ONEWIRE_H_ */ +#endif /* HAL_ONEWIRE_H_ */ /** @} */ diff --git a/os/hal/include/hal_rng.h b/os/hal/include/hal_rng.h index 0e3c484..dc146c7 100644 --- a/os/hal/include/hal_rng.h +++ b/os/hal/include/hal_rng.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef _RNG_H_ -#define _RNG_H_ +#ifndef HAL_RNG_H_ +#define HAL_RNG_H_ #if (HAL_USE_RNG == TRUE) || defined(__DOXYGEN__) @@ -131,6 +131,6 @@ extern "C" { #endif /* HAL_USE_RNG */ -#endif /* _RNG_H_ */ +#endif /* HAL_RNG_H_ */ /** @} */ diff --git a/os/hal/include/hal_timcap.h b/os/hal/include/hal_timcap.h index bd43dd1..61c7fc5 100644 --- a/os/hal/include/hal_timcap.h +++ b/os/hal/include/hal_timcap.h @@ -19,15 +19,15 @@ */ /** - * @file timcap.h + * @file hal_timcap.h * @brief TIMCAP Driver macros and structures. * * @addtogroup TIMCAP * @{ */ -#ifndef _TIMCAP_H_ -#define _TIMCAP_H_ +#ifndef HAL_TIMCAP_H_ +#define HAL_TIMCAP_H_ #include "ch.h" #include "hal.h" @@ -201,6 +201,6 @@ extern "C" { #endif /* HAL_USE_TIMCAP */ -#endif /* _TIMCAP_H_ */ +#endif /* HAL_TIMCAP_H_ */ /** @} */ diff --git a/os/hal/include/hal_usb_msd.h b/os/hal/include/hal_usb_msd.h new file mode 100644 index 0000000..08241df --- /dev/null +++ b/os/hal/include/hal_usb_msd.h @@ -0,0 +1,192 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_usb_msd.h + * @brief USM mass storage device driver macros and structures. + * + * @addtogroup usb_msd + * @{ + */ + +#ifndef HAL_USB_MSD_H +#define HAL_USB_MSD_H + +#if (HAL_USE_USB_MSD == TRUE) || defined(__DOXYGEN__) + +#include "lib_scsi.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define USB_MSD_DATA_EP 0x01 +#define USB_MSD_EP_SIZE 0x40 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !HAL_USE_USB +#error "Mass storage Driver requires HAL_USE_USB" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an USB mass storage driver. + */ +typedef struct USBMassStorageDriver USBMassStorageDriver; + +/** + * @brief Type of a driver state machine possible states. + */ +typedef enum { + USB_MSD_UNINIT = 0, + USB_MSD_STOP, + USB_MSD_READY, +} usbmsdstate_t; + +/** + * @brief Represents command block wrapper structure. + * @details See USB Mass Storage Class Specification. + */ +typedef struct PACKED_VAR { + uint32_t signature; + uint32_t tag; + uint32_t data_len; + uint8_t flags; + uint8_t lun; + uint8_t cmd_len; + uint8_t cmd_data[16]; +} msd_cbw_t; + +/** + * @brief Represents command status wrapper structure. + * @details See USB Mass Storage Class Specification. + */ +typedef struct PACKED_VAR { + uint32_t signature; + uint32_t tag; + uint32_t data_residue; + uint8_t status; +} msd_csw_t; + +/** + * @brief Transport handler passed to SCSI layer. + */ +typedef struct { + /** + * @brief Pointer to the @p USBDriver object. + */ + USBDriver *usbp; + /** + * @brief USB endpoint number. + */ + usbep_t ep; +} usb_scsi_transport_handler_t; + + +/** + * @brief Structure representing an USB mass storage driver. + */ +struct USBMassStorageDriver { + /** + * @brief Pointer to the @p USBDriver object. + */ + USBDriver *usbp; + /** + * @brief Driver state. + */ + usbmsdstate_t state; + /** + * @brief CBW structure. + */ + msd_cbw_t cbw; + /** + * @brief CSW structure. + */ + msd_csw_t csw; + /** + * @brief Thread working area. + */ + THD_WORKING_AREA( waMSDWorker, 512); + /** + * @brief Worker thread handler. + */ + thread_reference_t worker; + /** + * @brief SCSI target driver structure. + */ + SCSITarget scsi_target; + /** + * @brief SCSI target configuration structure. + */ + SCSITargetConfig scsi_config; + /** + * @brief SCSI transport structure. + */ + SCSITransport scsi_transport; + /** + * @brief SCSI over USB transport handler structure. + */ + usb_scsi_transport_handler_t usb_scsi_transport_handler; +}; + + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern USBMassStorageDriver USBMSD1; + +#ifdef __cplusplus +extern "C" { +#endif + void msdObjectInit(USBMassStorageDriver *msdp); + void msdStart(USBMassStorageDriver *msdp, USBDriver *usbp, + BaseBlockDevice *blkdev, uint8_t *blkbuf, + const scsi_inquiry_response_t *scsi_inquiry_response); + void msdStop(USBMassStorageDriver *msdp); + bool msd_request_hook(USBDriver *usbp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB_MSD */ + +#endif /* HAL_USB_MSD_H */ + +/** @} */ + + + + + + + + + diff --git a/os/hal/include/hal_usbh.h b/os/hal/include/hal_usbh.h index 5fd0047..63be93e 100644 --- a/os/hal/include/hal_usbh.h +++ b/os/hal/include/hal_usbh.h @@ -15,8 +15,8 @@ limitations under the License. */ -#ifndef USBH_H_ -#define USBH_H_ +#ifndef HAL_USBH_H_ +#define HAL_USBH_H_ #include "hal.h" @@ -433,4 +433,4 @@ struct usbh_baseclassdriver { #endif -#endif /* USBH_H_ */ +#endif /* HAL_USBH_H_ */ diff --git a/os/hal/ports/MSP430X/hal_adc_lld.c b/os/hal/ports/MSP430X/hal_adc_lld.c new file mode 100644 index 0000000..42d3cbe --- /dev/null +++ b/os/hal/ports/MSP430X/hal_adc_lld.c @@ -0,0 +1,354 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_adc_lld.c
+ * @brief MSP430X ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC1 driver identifier.
+ */
+#if (MSP430X_ADC_USE_ADC1 == TRUE) || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void restart_dma(ADCDriver * adcp) {
+ /* TODO timeouts? */
+ /* Restart DMA transfer */
+ if (adcp->dma.registers == NULL) {
+ /* Acquire a DMA stream because dmaTransfer can be called from ISRs */
+ osalSysLockFromISR();
+ dmaAcquireI(&(adcp->dma), adcp->dma.index);
+ osalSysUnlockFromISR();
+ dmaTransfer(&(adcp->dma), &(adcp->req));
+ }
+ else {
+ dmaTransfer(&(adcp->dma), &(adcp->req));
+ }
+}
+
+static void dma_callback(void * args) {
+ ADCDriver * adcp = (ADCDriver *)args;
+
+ if (adcp->grpp == NULL)
+ return;
+
+ adcp->count++;
+
+ if (adcp->count == adcp->depth / 2) {
+ /* half-full interrupt */
+ _adc_isr_half_code(adcp);
+ }
+
+ if (adcp->count == adcp->depth) {
+ /* full interrupt */
+
+ /* adc_lld_stop_conversion is called automatically here if needed */
+ _adc_isr_full_code(adcp);
+ /* after isr_full, adcp->grpp is only non-NULL if it's a circular group */
+ if (adcp->grpp) {
+ /* Reset the buffer pointer */
+ adcp->req.dest_addr = adcp->samples;
+
+ restart_dma(adcp);
+
+ /* Reset the count */
+ adcp->count = 0;
+
+ /* Start next sequence */
+ adcp->regs->ctl[0] |= ADC12SC;
+ }
+ }
+ else {
+ /* Advance the buffer pointer */
+ adcp->req.dest_addr = adcp->samples + (adcp->req.size * adcp->count);
+
+ restart_dma(adcp);
+
+ /* Start next sequence */
+ adcp->regs->ctl[0] |= ADC12SC;
+ }
+}
+
+static void populate_tlv(ADCDriver * adcp) {
+ uint8_t * tlv_addr = (uint8_t *)TLV_START;
+
+ while (*tlv_addr != TLV_TAGEND && tlv_addr < (uint8_t *)TLV_END) {
+ if (*tlv_addr == TLV_ADC12CAL) {
+ adcp->adc_cal = (msp430x_adc_cal_t *)(tlv_addr + 2);
+ }
+ else if (*tlv_addr == TLV_REFCAL) {
+ adcp->ref_cal = (msp430x_ref_cal_t *)(tlv_addr + 2);
+ }
+ tlv_addr += (tlv_addr[1] + 2);
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+PORT_IRQ_HANDLER(ADC12_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ switch (__even_in_range(ADC12IV, ADC12IV_ADC12TOVIFG)) {
+
+ case ADC12IV_ADC12OVIFG: {
+ if (ADCD1.grpp == NULL)
+ break;
+ _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
+ break;
+ }
+ case ADC12IV_ADC12TOVIFG: {
+ if (ADCD1.grpp == NULL)
+ break;
+ _adc_isr_error_code(&ADCD1, ADC_ERR_AWD);
+ break;
+ }
+ default:
+ osalDbgAssert(false, "unhandled ADC exception");
+ _adc_isr_error_code(&ADCD1, ADC_ERR_UNKNOWN);
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if MSP430X_ADC_USE_ADC1 == TRUE
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD1);
+ ADCD1.regs = (msp430x_adc_reg_t *)(&ADC12CTL0);
+ populate_tlv(&ADCD1);
+#endif
+}
+
+/**
+ * @brief Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver * adcp) {
+
+ if (adcp->state == ADC_STOP) {
+ /* Enables the peripheral.*/
+ adcp->regs->ctl[0] = ADC12ON | ADC12MSC;
+ adcp->regs->ctl[1] =
+ MSP430X_ADC1_PDIV | MSP430X_ADC1_DIV | MSP430X_ADC1_SSEL | ADC12SHP;
+ adcp->regs->ctl[3] = ADC12ICH3MAP | ADC12ICH2MAP | ADC12ICH1MAP |
+ ADC12ICH0MAP | ADC12TCMAP | ADC12BATMAP;
+ adcp->regs->ier[2] = ADC12TOVIE | ADC12OVIE;
+ adcp->req.trigger = DMA_TRIGGER_MNEM(ADC12IFG);
+#if MSP430X_ADC_COMPACT_SAMPLES == TRUE
+ adcp->req.data_mode = MSP430X_DMA_SRCWORD | MSP430X_DMA_DSTBYTE;
+#else
+ adcp->req.data_mode = MSP430X_DMA_SRCWORD | MSP430X_DMA_DSTWORD;
+#endif
+ adcp->req.addr_mode = MSP430X_DMA_SRCINCR | MSP430X_DMA_DSTINCR;
+ adcp->req.transfer_mode = MSP430X_DMA_SINGLE;
+ adcp->req.callback.callback = dma_callback;
+ adcp->req.callback.args = adcp;
+
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ bool b;
+ if (adcp->config->dma_index < MSP430X_DMA_CHANNELS) {
+ b = dmaAcquireI(&adcp->dma, adcp->config->dma_index);
+ osalDbgAssert(!b, "stream already allocated");
+ }
+ else {
+#endif
+ adcp->dma.registers = NULL;
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ }
+#endif
+ }
+ /* Configures the peripheral.*/
+}
+
+/**
+ * @brief Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver * adcp) {
+
+ if (adcp->state == ADC_READY) {
+/* Resets the peripheral.*/
+
+/* Disables the peripheral.*/
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ if (adcp->config->dma_index < MSP430X_DMA_CHANNELS) {
+ dmaRelease(&(adcp->dma));
+ }
+#endif
+ adcp->regs->ctl[0] = 0;
+ }
+}
+
+/**
+ * @brief Starts an ADC conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver * adcp) {
+
+ /* always use sequential transfer mode - this is fine */
+ adcp->regs->ctl[1] |= ADC12CONSEQ0;
+
+ /* set resolution */
+ adcp->regs->ctl[2] |= adcp->grpp->res;
+ /* start from MEM0 */
+ adcp->regs->ctl[3] &= ~(ADC12CSTARTADD_31);
+
+ /* Configure voltage reference */
+ while (REFCTL0 & REFGENBUSY)
+ ;
+ REFCTL0 = adcp->grpp->vref_src;
+
+ for (int i = 0; i < adcp->grpp->num_channels; i++) {
+ osalDbgAssert(adcp->grpp->channels[i] < 32, "invalid channel number");
+ adcp->regs->mctl[i] = adcp->grpp->ref | adcp->grpp->channels[i];
+ }
+
+ adcp->regs->mctl[adcp->grpp->num_channels - 1] |= ADC12EOS;
+
+ adcp->req.source_addr = adcp->regs->mem;
+ adcp->req.dest_addr = adcp->samples;
+ adcp->req.size = adcp->grpp->num_channels;
+ adcp->count = 0;
+
+/* TODO timeouts? */
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ if (adcp->config->dma_index >= MSP430X_DMA_CHANNELS) {
+ adcp->dma.index = dmaRequestS(&(adcp->req), TIME_INFINITE);
+ }
+ else {
+ dmaTransfer(&(adcp->dma), &(adcp->req));
+ }
+#else
+ adcp->dma.index = dmaRequestS(&(adcp->req), TIME_INFINITE);
+#endif
+
+ adcp->regs->ctl[0] |= adcp->grpp->rate | ADC12MSC | ADC12ENC | ADC12SC;
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver * adcp) {
+
+ /* TODO stop DMA transfers here */
+ adcp->regs->ctl[0] &= ~(ADC12ENC | ADC12SC);
+
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ if (adcp->config->dma_index >= MSP430X_DMA_CHANNELS) {
+#endif
+ if (adcp->dma.registers != NULL) {
+ dmaRelease(&(adcp->dma));
+ adcp->dma.registers = NULL;
+ }
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ }
+#endif
+}
+
+adcsample_t adcMSP430XAdjustResult(ADCConversionGroup * grpp,
+ adcsample_t sample) {
+ uint32_t tmp;
+ uint16_t fact;
+ if (grpp->ref == MSP430X_ADC_VSS_VREF_BUF ||
+ grpp->ref == MSP430X_ADC_VEREF_P_VREF_BUF ||
+ grpp->ref == MSP430X_ADC_VREF_BUF_VCC ||
+ grpp->ref == MSP430X_ADC_VREF_BUF_VEREF_P ||
+ grpp->ref == MSP430X_ADC_VEREF_N_VREF_BUF) {
+ /* Retrieve proper reference correction factor from TLV */
+ fact = (&(ADCD1.ref_cal->CAL_ADC_12VREF_FACTOR))[grpp->vref_src >> 4];
+ /* Calculate corrected value */
+ tmp = (uint32_t)(sample << 1) * (uint32_t)fact;
+ sample = tmp >> 16;
+ }
+
+ /* Gain correction */
+ fact = ADCD1.adc_cal->CAL_ADC_GAIN_FACTOR;
+ tmp = (uint32_t)(sample << 1) * (uint32_t)fact;
+ sample = tmp >> 16;
+
+ /* Offset correction */
+ sample += ADCD1.adc_cal->CAL_ADC_OFFSET;
+
+ return sample;
+}
+
+adcsample_t adcMSP430XAdjustTemp(ADCConversionGroup * grpp,
+ adcsample_t sample) {
+ uint16_t t30;
+ uint16_t t85;
+
+ /* Retrieve proper T = 30 correction value from TLV */
+ t30 = (&(ADCD1.adc_cal->CAL_ADC_12T30))[grpp->vref_src >> 3];
+ /* Retrieve proper T = 85 correction value from TLV */
+ t85 = (&(ADCD1.adc_cal->CAL_ADC_12T30))[(grpp->vref_src >> 3) + 1];
+
+ return ((((int32_t)sample - (int32_t)t30) * (85 - 30)) / (t85 - t30)) + 30;
+}
+
+#endif /* HAL_USE_ADC == TRUE */
+
+/** @} */
diff --git a/os/hal/ports/MSP430X/hal_adc_lld.h b/os/hal/ports/MSP430X/hal_adc_lld.h new file mode 100644 index 0000000..1cca36b --- /dev/null +++ b/os/hal/ports/MSP430X/hal_adc_lld.h @@ -0,0 +1,516 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_adc_lld.h
+ * @brief MSP430X ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
+
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Sampling rates
+ * @{
+ */
+typedef enum {
+ MSP430X_ADC_SHT_4 = 0x0000,
+ MSP430X_ADC_SHT_8 = 0x1100,
+ MSP430X_ADC_SHT_16 = 0x2200,
+ MSP430X_ADC_SHT_32 = 0x3300,
+ MSP430X_ADC_SHT_64 = 0x4400,
+ MSP430X_ADC_SHT_96 = 0x5500,
+ MSP430X_ADC_SHT_128 = 0x6600,
+ MSP430X_ADC_SHT_192 = 0x7700,
+ MSP430X_ADC_SHT_256 = 0x8800,
+ MSP430X_ADC_SHT_384 = 0x9900,
+ MSP430X_ADC_SHT_512 = 0xAA00
+} MSP430XADCSampleRates;
+/** @} */
+
+/**
+ * @name Resolution
+ * @{
+ */
+typedef enum {
+ MSP430X_ADC_RES_8BIT = 0x0000,
+ MSP430X_ADC_RES_10BIT = 0x0010,
+ MSP430X_ADC_RES_12BIT = 0x0020
+} MSP430XADCResolution;
+/** @} */
+
+/**
+ * @name References
+ * @{
+ */
+typedef enum {
+ MSP430X_ADC_VSS_VCC = 0x0000,
+ MSP430X_ADC_VSS_VREF_BUF = 0x0100,
+ MSP430X_ADC_VSS_VEREF_N = 0x0200,
+ MSP430X_ADC_VSS_VEREF_P_BUF = 0x0300,
+ MSP430X_ADC_VSS_VEREF_P = 0x0400,
+ MSP430X_ADC_VEREF_P_BUF_VCC = 0x0500,
+ MSP430X_ADC_VEREF_P_VCC = 0x0600,
+ MSP430X_ADC_VEREF_P_VREF_BUF = 0x0700,
+ MSP430X_ADC_VREF_BUF_VCC = 0x0900,
+ MSP430X_ADC_VREF_BUF_VEREF_P = 0x0B00,
+ MSP430X_ADC_VEREF_N_VCC = 0x0C00,
+ MSP430X_ADC_VEREF_N_VREF_BUF = 0x0D00,
+ MSP430X_ADC_VEREF_N_VEREF_P = 0x0E00,
+ MSP430X_ADC_VEREF_N_VEREF_P_BUF = 0x0F00
+} MSP430XADCReferences;
+
+typedef enum {
+ MSP430X_REF_1V2 = 0x0000,
+ MSP430X_REF_2V0 = 0x0010,
+ MSP430X_REF_2V5 = 0x0020,
+ MSP430X_REF_1V2_EXT = 0x0002,
+ MSP430X_REF_2V0_EXT = 0x0012,
+ MSP430X_REF_2V5_EXT = 0x0022
+} MSP430XREFSources;
+
+#define MSP430X_REF_NONE MSP430X_REF_1V2
+
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name MSP430X configuration options
+ * @{
+ */
+/**
+ * @brief Stores ADC samples in an 8 bit integer.
+ * @note 10 and 12 bit sampling modes must not be used when this option is
+ * enabled.
+ */
+#if !defined(MSP430X_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)
+#define MSP430X_ADC_COMPACT_SAMPLES FALSE
+#endif
+
+/**
+ * @brief ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(MSP430X_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define MSP430X_ADC_USE_ADC1 TRUE
+#endif
+
+/**]
+ * @brief Exclusive DMA enable switch.
+ * @details If set to @p TRUE the support for exclusive DMA is included.
+ * @note This increases the size of the compiled executable somewhat.
+ * @note The default is @p FALSE.
+ */
+#if !defined(MSP430X_ADC_EXCLUSIVE_DMA) || defined(__DOXYGEN__)
+#define MSP430X_ADC_EXCLUSIVE_DMA FALSE
+#endif
+
+#if MSP430X_ADC_USE_ADC1
+
+/**
+ * @brief ADC1 clock source configuration
+ */
+#if !defined(MSP430X_ADC1_CLK_SRC)
+#define MSP430X_ADC1_CLK_SRC MSP430X_MODCLK
+#endif
+
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if MSP430X_ADC_USE_ADC1
+
+#if !defined(__MSP430_HAS_ADC12_B__)
+#error "No ADC present or ADC version not supported"
+#endif
+
+#if (MSP430X_ADC1_CLK_SRC == MSP430X_MODCLK)
+#define MSP430X_ADC1_CLK_FREQ MSP430X_MODCLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_0
+#elif (MSP430X_ADC1_CLK_SRC == MSP430X_ACLK)
+#define MSP430X_ADC1_CLK_FREQ MSP430X_ACLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_1
+#elif (MSP430X_ADC1_CLK_SRC == MSP430X_MCLK)
+#define MSP$30X_ADC1_CLK_FREQ MSP430X_MCLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_2
+#elif (MSP430X_ADC1_CLK_SRC == MSP430SMCLK)
+#define MSP430X_ADC1_CLK_FREQ MSP430X_SMCLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_3
+#else
+#error "Invalid ADC1 clock source requested!"
+#endif
+
+#if !defined(MSP430X_ADC1_FREQ)
+#warning "ADC clock frequency not defined - assuming 1 for all dividers"
+#define MSP430X_ADC1_DIV_CALC(x) (x == 1)
+#else
+#define MSP430X_ADC1_DIV_CALC(x) \
+ ((MSP430X_ADC1_CLK_FREQ / x) == MSP430X_ADC1_FREQ)
+#endif
+
+/**
+ * @brief ADC1 prescaler calculations
+ */
+#if MSP430X_ADC1_DIV_CALC(1)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(2)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_1
+#elif MSP430X_ADC1_DIV_CALC(3)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(4)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(5)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(6)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_5
+#elif MSP430X_ADC1_DIV_CALC(7)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(8)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(12)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(16)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_3
+#elif MSP430X_ADC1_DIV_CALC(20)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(24)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_5
+#elif MSP430X_ADC1_DIV_CALC(28)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(32)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(64)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(96)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(128)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_1
+#elif MSP430X_ADC1_DIV_CALC(160)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(192)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(224)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(256)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_3
+#elif MSP430X_ADC1_DIV_CALC(320)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(384)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_5
+#elif MSP430X_ADC1_DIV_CALC(448)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(512)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_7
+#else
+#error "MSP430X_ADC1_FREQ not achievable with MSP430X_ADC1_CLK_SRC"
+#endif
+
+#endif /* MSP430X_ADC_USE_ADC1 */
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC sample data type.
+ */
+#if !MSP430X_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__)
+typedef uint16_t adcsample_t;
+#else
+typedef uint8_t adcsample_t;
+#endif
+
+/**
+ * @brief Channels number in a conversion group.
+ */
+typedef uint8_t adc_channels_num_t;
+
+/**
+ * @brief Possible ADC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ ADC_ERR_UNKNOWN = 0, /**< Unknown error has occurred */
+ ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
+ ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */
+} adcerror_t;
+
+/**
+ * @brief Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief ADC notification callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] buffer pointer to the most recent samples data
+ * @param[in] n number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver * adcp, adcsample_t * buffer, size_t n);
+
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver * adcp, adcerror_t err);
+
+/**
+ * @brief MSP430X ADC register structure.
+ */
+typedef struct {
+ uint16_t ctl[4];
+ uint16_t lo;
+ uint16_t hi;
+ uint16_t ifgr[3];
+ uint16_t ier[3];
+ uint16_t iv;
+ uint16_t padding[3];
+ uint16_t mctl[32];
+ uint16_t mem[32];
+} msp430x_adc_reg_t;
+
+/**
+ * @brief MSP430X ADC calibration structure.
+ */
+typedef struct {
+ uint16_t CAL_ADC_GAIN_FACTOR;
+ uint16_t CAL_ADC_OFFSET;
+ uint16_t CAL_ADC_12T30;
+ uint16_t CAL_ADC_12T85;
+ uint16_t CAL_ADC_20T30;
+ uint16_t CAL_ADC_20T85;
+ uint16_t CAL_ADC_25T30;
+ uint16_t CAL_ADC_25T85;
+} msp430x_adc_cal_t;
+
+/**
+ * @brief MSP430X REF calibration structure.
+ */
+typedef struct {
+ uint16_t CAL_ADC_12VREF_FACTOR;
+ uint16_t CAL_ADC_20VREF_FACTOR;
+ uint16_t CAL_ADC_25VREF_FACTOR;
+} msp430x_ref_cal_t;
+
+/**
+ * @brief Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ * operation.
+ * @note The use of this configuration structure requires knowledge of
+ * MSP430X ADC cell registers interface, please refer to the MSP430X
+ * reference manual for details.
+ */
+typedef struct {
+ /**
+ * @brief Enables the circular buffer mode for the group.
+ */
+ bool circular;
+ /**
+ * @brief Number of the analog channels belonging to the conversion group.
+ */
+ adc_channels_num_t num_channels;
+ /**
+ * @brief Callback function associated to the group or @p NULL.
+ */
+ adccallback_t end_cb;
+ /**
+ * @brief Error callback or @p NULL.
+ */
+ adcerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Sequence of analog channels belonging to the conversion group.
+ * @note Only the first num_channels are valid.
+ */
+ uint8_t channels[32];
+ /**
+ * @brief Sample resolution
+ */
+ MSP430XADCResolution res;
+ /**
+ * @brief Sampling time in clock cycles
+ */
+ MSP430XADCSampleRates rate;
+ /**
+ * @brief Voltage references to use
+ */
+ MSP430XADCReferences ref;
+ /**
+ * @brief VREF source
+ */
+ MSP430XREFSources vref_src;
+} ADCConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)
+ /**
+ * @brief The index of the DMA channel.
+ * @note This may be >MSP430X_DMA_CHANNELS to indicate that exclusive DMA
+ * is not used.
+ */
+ uint8_t dma_index;
+#endif
+} ADCConfig;
+
+/**
+ * @brief Structure representing an ADC driver.
+ */
+struct ADCDriver {
+ /**
+ * @brief Driver state.
+ */
+ adcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const ADCConfig * config;
+ /**
+ * @brief Current samples buffer pointer or @p NULL.
+ */
+ adcsample_t * samples;
+ /**
+ * @brief Current samples buffer depth or @p 0.
+ */
+ size_t depth;
+ /**
+ * @brief Current conversion group pointer or @p NULL.
+ */
+ const ADCConversionGroup * grpp;
+#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+#if (ADC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif
+#if defined(ADC_DRIVER_EXT_FIELDS)
+ ADC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Base address of ADC12_B registers
+ */
+ msp430x_adc_reg_t * regs;
+ /**
+ * @brief DMA request structure
+ */
+ msp430x_dma_req_t req;
+ /**
+ * @brief ADC calibration structure from TLV
+ */
+ msp430x_adc_cal_t * adc_cal;
+ /**
+ * @brief REF calibration structure from TLV
+ */
+ msp430x_ref_cal_t * ref_cal;
+ /**
+ * @brief Count of times DMA callback has been called
+ */
+ uint8_t count;
+ /**
+ * @brief DMA stream
+ */
+ msp430x_dma_ch_t dma;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if (MSP430X_ADC_USE_ADC1 == TRUE) && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void adc_lld_init(void);
+void adc_lld_start(ADCDriver * adcp);
+void adc_lld_stop(ADCDriver * adcp);
+void adc_lld_start_conversion(ADCDriver * adcp);
+void adc_lld_stop_conversion(ADCDriver * adcp);
+adcsample_t adcMSP430XAdjustResult(ADCConversionGroup * grpp,
+ adcsample_t sample);
+adcsample_t adcMSP430XAdjustTemp(ADCConversionGroup * grpp, adcsample_t sample);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC == TRUE */
+
+#endif /* HAL_ADC_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/MSP430X/hal_dma_lld.c b/os/hal/ports/MSP430X/hal_dma_lld.c index 43e1d6c..82bf39f 100644 --- a/os/hal/ports/MSP430X/hal_dma_lld.c +++ b/os/hal/ports/MSP430X/hal_dma_lld.c @@ -44,9 +44,8 @@ static msp430x_dma_ch_reg_t * const dma_channels = (msp430x_dma_ch_reg_t *)&DMA0CTL;
static msp430x_dma_cb_t callbacks[MSP430X_DMA_CHANNELS];
-#if CH_CFG_USE_SEMAPHORES
-static semaphore_t dma_lock;
-#endif
+static threads_queue_t dma_queue;
+static unsigned int queue_length;
/*===========================================================================*/
/* Driver local functions. */
@@ -88,9 +87,9 @@ PORT_IRQ_HANDLER(DMA_VECTOR) { index = (DMAIV >> 1) - 1;
if (index < MSP430X_DMA_CHANNELS) {
-#if CH_CFG_USE_SEMAPHORES
- chSemSignalI(&dma_lock);
-#endif
+ osalSysLockFromISR();
+ osalThreadDequeueNextI(&dma_queue, MSG_OK);
+ osalSysUnlockFromISR();
msp430x_dma_cb_t * cb = &callbacks[index];
@@ -113,9 +112,7 @@ PORT_IRQ_HANDLER(DMA_VECTOR) { * @init
*/
void dmaInit(void) {
-#if CH_CFG_USE_SEMAPHORES
- chSemObjectInit(&dma_lock, MSP430X_DMA_CHANNELS);
-#endif
+ osalThreadQueueObjectInit(&dma_queue);
}
/**
@@ -125,134 +122,124 @@ void dmaInit(void) { * semaphores are enabled, the calling thread will sleep until a
* channel is available or the request times out. If semaphores are
* disabled, the calling thread will busy-wait instead of sleeping.
+ *
+ * @sclass
*/
-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout) {
-/* Check if a DMA channel is available */
-#if CH_CFG_USE_SEMAPHORES
- msg_t semresult = chSemWaitTimeout(&dma_lock, timeout);
- if (semresult != MSG_OK)
- return true;
-#endif
-
-#if !(CH_CFG_USE_SEMAPHORES)
- systime_t start = chVTGetSystemTimeX();
-
- do {
-#endif
- /* Grab the correct DMA channel to use */
- int i = 0;
- for (i = 0; i < MSP430X_DMA_CHANNELS; i++) {
- if (!(dma_channels[i].ctl & DMAEN)) {
- break;
- }
- }
-#if !(CH_CFG_USE_SEMAPHORES)
- while (chVTTimeElapsedSinceX(start) < timeout)
- ;
-#endif
-
-#if !(CH_CFG_USE_SEMAPHORES)
- if (i == MSP430X_DMA_CHANNELS) {
- return true;
+int dmaRequestS(msp430x_dma_req_t * request, systime_t timeout) {
+
+ osalDbgCheckClassS();
+
+ /* Check if a DMA channel is available */
+ if (queue_length >= MSP430X_DMA_CHANNELS) {
+ msg_t queueresult = osalThreadEnqueueTimeoutS(&dma_queue, timeout);
+ if (queueresult != MSG_OK)
+ return -1;
+ }
+
+ /* Grab the correct DMA channel to use */
+ int i = 0;
+ for (i = 0; i < MSP430X_DMA_CHANNELS; i++) {
+ if (!(dma_channels[i].ctl & DMAEN)) {
+ break;
}
-#endif
+ }
+
+ /* Make the request */
+ init_request(request, i);
+
+ return i;
+}
- /* Make the request */
- init_request(request, i);
+/**
+ * @brief Acquires exclusive control of a DMA channel.
+ * @pre The channel must not be already acquired or an error is returned.
+ * @note If the channel is in use by the DMA engine, blocks until acquired.
+ * @post This channel must be interacted with using only the functions
+ * defined in this module.
+ *
+ * @param[out] channel The channel handle. Must be pre-allocated.
+ * @param[in] index The index of the channel (< MSP430X_DMA_CHANNELS).
+ * @return The operation status.
+ * @retval false no error, channel acquired.
+ * @retval true error, channel already acquired.
+ *
+ * @iclass
+ */
+bool dmaAcquireI(msp430x_dma_ch_t * channel, uint8_t index) {
+
+ osalDbgCheckClassI();
- return false;
+ /* Is the channel already acquired? */
+ osalDbgAssert(index < MSP430X_DMA_CHANNELS, "invalid channel index");
+ if (dma_channels[index].ctl & DMADT_4) {
+ return true;
}
- /**
- * @brief Acquires exclusive control of a DMA channel.
- * @pre The channel must not be already acquired or an error is returned.
- * @note If the channel is in use by the DMA engine, blocks until acquired.
- * @post This channel must be interacted with using only the functions
- * defined in this module.
- *
- * @param[out] channel The channel handle. Must be pre-allocated.
- * @param[in] index The index of the channel (< MSP430X_DMA_CHANNELS).
- * @return The operation status.
- * @retval false no error, channel acquired.
- * @retval true error, channel already acquired.
- */
- bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index) {
- /* Acquire the channel in an idle mode */
-
- /* Is the channel already acquired? */
- osalDbgAssert(index < MSP430X_DMA_CHANNELS, "invalid channel index");
- if (dma_channels[index].ctl & DMADT_4) {
- return true;
- }
+ /* Increment the DMA counter */
+ queue_length++;
-/* Increment the DMA counter */
-#if CH_CFG_USE_SEMAPHORES
- msg_t semresult = chSemWait(&dma_lock);
- if (semresult != MSG_OK)
- return true;
-#endif
+ while (dma_channels[index].ctl & DMAEN)
+ ;
- while (dma_channels[index].ctl & DMAEN)
- ;
+ /* Acquire the channel in an idle mode */
+ dma_trigger_set(index, DMA_TRIGGER_MNEM(DMAREQ));
+ dma_channels[index].sz = 0;
+ dma_channels[index].ctl = DMAEN | DMAABORT | DMADT_4;
- dma_trigger_set(index, DMA_TRIGGER_MNEM(DMAREQ));
- dma_channels[index].sz = 0;
- dma_channels[index].ctl = DMAEN | DMAABORT | DMADT_4;
+ channel->registers = dma_channels + index;
+ channel->index = index;
+ channel->cb = callbacks + index;
+
+ return false;
+}
- channel->registers = dma_channels + index;
- channel->index = index;
- channel->cb = callbacks + index;
+/**
+ * @brief Initiates a DMA transfer operation using an acquired channel.
+ * @pre The channel must have been acquired using @p dmaAcquire().
+ *
+ * @param[in] channel pointer to a DMA channel from @p dmaAcquire().
+ * @param[in] request pointer to a DMA request object.
+ */
+void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request) {
- return false;
- }
+ dma_trigger_set(channel->index, request->trigger);
+ /**(channel->ctl) = request->trigger;*/
- /**
- * @brief Initiates a DMA transfer operation using an acquired channel.
- * @pre The channel must have been acquired using @p dmaAcquire().
- *
- * @param[in] channel pointer to a DMA channel from @p dmaAcquire().
- * @param[in] request pointer to a DMA request object.
- */
- void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request) {
-
- dma_trigger_set(channel->index, request->trigger);
- /**(channel->ctl) = request->trigger;*/
-
- channel->cb->callback = request->callback.callback;
- channel->cb->args = request->callback.args;
-
- chSysLock();
- channel->registers->ctl &= (~DMAEN);
- channel->registers->sa = (uintptr_t)request->source_addr;
- channel->registers->da = (uintptr_t)request->dest_addr;
- channel->registers->sz = request->size;
- channel->registers->ctl = DMAIE | request->data_mode | request->addr_mode |
- request->transfer_mode | DMADT_4 | DMAEN |
- DMAREQ; /* repeated transfers */
- chSysUnlock();
- }
+ channel->cb->callback = request->callback.callback;
+ channel->cb->args = request->callback.args;
- /**
- * @brief Releases exclusive control of a DMA channel.
- * @details The channel is released from control and returned to the DMA
- * engine
- * pool. Trying to release an unallocated channel is an illegal
- * operation and is trapped if assertions are enabled.
- * @pre The channel must have been acquired using @p dmaAcquire().
- * @post The channel is returned to the DMA engine pool.
- */
- void dmaRelease(msp430x_dma_ch_t * channel) {
-
- osalDbgCheck(channel != NULL);
-
- /* Release the channel in an idle mode */
- channel->registers->ctl = DMAABORT;
-
-/* release the DMA counter */
-#if CH_CFG_USE_SEMAPHORES
- chSemSignal(&dma_lock);
-#endif
- }
+ channel->registers->ctl &= (~DMAEN);
+ channel->registers->sa = (uintptr_t)request->source_addr;
+ channel->registers->da = (uintptr_t)request->dest_addr;
+ channel->registers->sz = request->size;
+ channel->registers->ctl = DMAIE | request->data_mode | request->addr_mode |
+ request->transfer_mode | DMADT_4 | DMAEN |
+ DMAREQ; /* repeated transfers */
+}
+
+/**
+ * @brief Releases exclusive control of a DMA channel.
+ * @details The channel is released from control and returned to the DMA
+ * engine
+ * pool. Trying to release an unallocated channel is an illegal
+ * operation and is trapped if assertions are enabled.
+ * @pre The channel must have been acquired using @p dmaAcquire().
+ * @post The channel is returned to the DMA engine pool.
+ */
+void dmaRelease(msp430x_dma_ch_t * channel) {
+ syssts_t sts;
+
+ sts = osalSysGetStatusAndLockX();
+ osalDbgCheck(channel != NULL);
+
+ /* Release the channel in an idle mode */
+ channel->registers->ctl = DMAABORT;
+
+ /* release the DMA counter */
+ osalThreadDequeueAllI(&dma_queue, MSG_RESET);
+ queue_length = 0;
+ osalSysRestoreStatusX(sts);
+}
#endif /* HAL_USE_DMA == TRUE */
diff --git a/os/hal/ports/MSP430X/hal_dma_lld.h b/os/hal/ports/MSP430X/hal_dma_lld.h index d1495d2..f558e78 100644 --- a/os/hal/ports/MSP430X/hal_dma_lld.h +++ b/os/hal/ports/MSP430X/hal_dma_lld.h @@ -159,8 +159,8 @@ typedef struct { extern "C" {
#endif
void dmaInit(void);
-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout);
-bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index);
+int dmaRequestS(msp430x_dma_req_t * request, systime_t timeout);
+bool dmaAcquireI(msp430x_dma_ch_t * channel, uint8_t index);
void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request);
void dmaRelease(msp430x_dma_ch_t * channel);
diff --git a/os/hal/ports/MSP430X/hal_lld.c b/os/hal/ports/MSP430X/hal_lld.c index 872fe97..812a0cf 100644 --- a/os/hal/ports/MSP430X/hal_lld.c +++ b/os/hal/ports/MSP430X/hal_lld.c @@ -82,6 +82,10 @@ void hal_lld_init(void) { } while (SFRIFG1 & OFIFG);
#endif
CSCTL0_H = 0xFF; /* Lock clock system */
+
+#if (HAL_USE_DMA == TRUE)
+ dmaInit();
+#endif
}
/** @} */
diff --git a/os/hal/ports/MSP430X/hal_lld.h b/os/hal/ports/MSP430X/hal_lld.h index 9549453..62f07e9 100644 --- a/os/hal/ports/MSP430X/hal_lld.h +++ b/os/hal/ports/MSP430X/hal_lld.h @@ -25,6 +25,8 @@ #ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
+#include "hal_dma_lld.h"
+
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
diff --git a/os/hal/ports/MSP430X/hal_serial_lld.c b/os/hal/ports/MSP430X/hal_serial_lld.c index 0d9aa1c..feb00ac 100644 --- a/os/hal/ports/MSP430X/hal_serial_lld.c +++ b/os/hal/ports/MSP430X/hal_serial_lld.c @@ -374,11 +374,11 @@ PORT_IRQ_HANDLER(USCI_A0_VECTOR) { if (oqIsEmptyI(&SD0.oqueue))
chnAddFlagsI(&SD0, CHN_TRANSMISSION_END);
UCA0IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
@@ -432,11 +432,11 @@ PORT_IRQ_HANDLER(USCI_A1_VECTOR) { if (oqIsEmptyI(&SD1.oqueue))
chnAddFlagsI(&SD1, CHN_TRANSMISSION_END);
UCA1IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
@@ -490,11 +490,11 @@ PORT_IRQ_HANDLER(USCI_A2_VECTOR) { if (oqIsEmptyI(&SD2.oqueue))
chnAddFlagsI(&SD2, CHN_TRANSMISSION_END);
UCA2IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
@@ -548,11 +548,11 @@ PORT_IRQ_HANDLER(USCI_A3_VECTOR) { if (oqIsEmptyI(&SD3.oqueue))
chnAddFlagsI(&SD3, CHN_TRANSMISSION_END);
UCA3IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
diff --git a/os/hal/ports/MSP430X/hal_spi_lld.c b/os/hal/ports/MSP430X/hal_spi_lld.c index 70a357e..3a54b1e 100644 --- a/os/hal/ports/MSP430X/hal_spi_lld.c +++ b/os/hal/ports/MSP430X/hal_spi_lld.c @@ -104,21 +104,21 @@ static uint16_t dummyrx; static void init_transfer(SPIDriver * spip) {
#if MSP430X_SPI_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)
- if (spip->config->dmarx_index > MSP430X_DMA_CHANNELS) {
- dmaRequest(&(spip->rx_req), TIME_INFINITE);
+ if (spip->config->dmarx_index >= MSP430X_DMA_CHANNELS) {
+ dmaRequestS(&(spip->rx_req), TIME_INFINITE);
}
else {
dmaTransfer(&(spip->dmarx), &(spip->rx_req));
}
- if (spip->config->dmatx_index > MSP430X_DMA_CHANNELS) {
- dmaRequest(&(spip->tx_req), TIME_INFINITE);
+ if (spip->config->dmatx_index >= MSP430X_DMA_CHANNELS) {
+ dmaRequestS(&(spip->tx_req), TIME_INFINITE);
}
else {
dmaTransfer(&(spip->dmatx), &(spip->tx_req));
}
#else
- dmaRequest(&(spip->rx_req), TIME_INFINITE);
- dmaRequest(&(spip->tx_req), TIME_INFINITE);
+ dmaRequestS(&(spip->rx_req), TIME_INFINITE);
+ dmaRequestS(&(spip->tx_req), TIME_INFINITE);
#endif
*(spip->ifg) |= UCTXIFG;
@@ -325,11 +325,11 @@ void spi_lld_start(SPIDriver * spip) { /* Claim DMA streams here */
bool b;
if (spip->config->dmatx_index < MSP430X_DMA_CHANNELS) {
- b = dmaAcquire(&(spip->dmatx), spip->config->dmatx_index);
+ b = dmaAcquireI(&(spip->dmatx), spip->config->dmatx_index);
osalDbgAssert(!b, "stream already allocated");
}
if (spip->config->dmarx_index < MSP430X_DMA_CHANNELS) {
- b = dmaAcquire(&(spip->dmarx), spip->config->dmarx_index);
+ b = dmaAcquireI(&(spip->dmarx), spip->config->dmarx_index);
osalDbgAssert(!b, "stream already allocated");
}
#endif /* MSP430X_SPI_EXCLUSIVE_DMA */
@@ -388,10 +388,11 @@ void spi_lld_start(SPIDriver * spip) { spip->regs->ctlw0 = UCSWRST;
spip->regs->brw = brw;
spip->regs->ctlw0 =
- (spip->config->spi_mode << 14) | (spip->config->bit_order << 13) |
+ ((spip->config->spi_mode ^ 0x02) << 14) | (spip->config->bit_order << 13) |
(spip->config->data_size << 12) | (UCMST) |
((spip->config->ss_line ? 0 : 2) << 9) | (UCSYNC) | (ssel) | (UCSTEM);
*(spip->ifg) = 0;
+ spi_lld_unselect(spip);
}
/**
@@ -406,8 +407,12 @@ void spi_lld_stop(SPIDriver * spip) { if (spip->state == SPI_READY) {
/* Disables the peripheral.*/
#if MSP430X_SPI_EXCLUSIVE_DMA == TRUE
- dmaRelease(&(spip->dmatx));
- dmaRelease(&(spip->dmarx));
+ if (spip->config->dmatx_index < MSP430X_DMA_CHANNELS) {
+ dmaRelease(&(spip->dmatx));
+ }
+ if (spip->config->dmarx_index < MSP430X_DMA_CHANNELS) {
+ dmaRelease(&(spip->dmarx));
+ }
#endif
spip->regs->ctlw0 = UCSWRST;
}
@@ -561,15 +566,12 @@ void spi_lld_receive(SPIDriver * spip, size_t n, void * rxbuf) { * @param[in] frame the data frame to send over the SPI bus
* @return The received data frame from the SPI bus.
*/
-uint16_t spi_lld_polled_exchange(SPIDriver * spip, uint16_t frame) {
-
- osalDbgAssert(!(frame & 0xFF00U), "16-bit transfers not supported");
+uint8_t spi_lld_polled_exchange(SPIDriver * spip, uint8_t frame) {
- while (!(*(spip->ifg) & UCTXIFG))
- ;
spip->regs->txbuf = frame;
while (!(*(spip->ifg) & UCRXIFG))
;
+ *(spip->ifg) &= ~(UCRXIFG | UCTXIFG);
return spip->regs->rxbuf;
}
diff --git a/os/hal/ports/MSP430X/hal_spi_lld.h b/os/hal/ports/MSP430X/hal_spi_lld.h index ebf14c8..949a8a0 100644 --- a/os/hal/ports/MSP430X/hal_spi_lld.h +++ b/os/hal/ports/MSP430X/hal_spi_lld.h @@ -118,7 +118,7 @@ * @note This increases the size of the compiled executable somewhat.
* @note The default is @p FALSE.
*/
-#if !defined(MSP430X_SPI_EXCLUSIVE_DMA) | defined(__DOXYGEN__)
+#if !defined(MSP430X_SPI_EXCLUSIVE_DMA) || defined(__DOXYGEN__)
#define MSP430X_SPI_EXCLUSIVE_DMA FALSE
#endif
@@ -630,7 +630,7 @@ extern "C" { const void *txbuf, void *rxbuf);
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
- uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
+ uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame);
#ifdef __cplusplus
}
#endif
diff --git a/os/hal/ports/MSP430X/platform.mk b/os/hal/ports/MSP430X/platform.mk index 832814b..627a2f0 100644 --- a/os/hal/ports/MSP430X/platform.mk +++ b/os/hal/ports/MSP430X/platform.mk @@ -4,7 +4,8 @@ PLATFORMSRC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_serial_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_pal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_dma_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_spi_lld.c
+ ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_spi_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_adc_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c index 601deca..f8178f1 100644 --- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c +++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c @@ -15,7 +15,7 @@ */ /** - * @file STM32/CRCv1/crc_lld.c + * @file STM32/CRCv1/hal_crc_lld.c * @brief STM32 CRC subsystem low level driver source. * * @addtogroup CRC diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h index ecdaf81..213d346 100644 --- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h +++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h @@ -15,15 +15,15 @@ */ /** - * @file STM32/CRCv1/crc_lld.h + * @file STM32/CRCv1/hal_crc_lld.h * @brief STM32 CRC subsystem low level driver header. * * @addtogroup CRC * @{ */ -#ifndef _CRC_LLD_H_ -#define _CRC_LLD_H_ +#ifndef HAL_CRC_LLD_H_ +#define HAL_CRC_LLD_H_ #if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) @@ -244,6 +244,6 @@ extern "C" { #endif /* HAL_USE_CRC */ -#endif /* _CRC_LLD_H_ */ +#endif /* HAL_CRC_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c index aba029f..6751202 100644 --- a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c +++ b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c @@ -15,7 +15,7 @@ */ /** - * @file stm32_dma2d.c + * @file hal_stm32_dma2d.c * @brief DMA2D/Chrom-ART driver. */ diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h index 01f0941..c06ab62 100644 --- a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h +++ b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h @@ -15,15 +15,15 @@ */ /** - * @file stm32_dma2d.h + * @file hal_stm32_dma2d.h * @brief DMA2D/Chrom-ART driver. * * @addtogroup dma2d * @{ */ -#ifndef _STM32_DMA2D_H_ -#define _STM32_DMA2D_H_ +#ifndef HAL_STM32_DMA2D_H_ +#define HAL_STM32_DMA2D_H_ /** * @brief Using the DMA2D driver. @@ -659,6 +659,6 @@ extern "C" { #endif /* STM32_DMA2D_USE_DMA2D */ -#endif /* _STM32_DMA2D_H_ */ +#endif /* HAL_STM32_DMA2D_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c index 40ad05c..b4c2938 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c @@ -15,7 +15,7 @@ */ /** - * @file fsmc.c + * @file hal_fsmc.c * @brief FSMC Driver subsystem low level driver source template. * * @addtogroup FSMC @@ -125,7 +125,7 @@ void fsmc_start(FSMCDriver *fsmcp) { rccResetFSMC(); #endif rccEnableFSMC(FALSE); -#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND) +#if HAL_USE_NAND nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY); #endif } @@ -153,7 +153,7 @@ void fsmc_stop(FSMCDriver *fsmcp) { /* Disables the peripheral.*/ #if STM32_FSMC_USE_FSMC1 if (&FSMCD1 == fsmcp) { -#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND) +#if HAL_USE_NAND nvicDisableVector(STM32_FSMC_NUMBER); #endif rccDisableFSMC(FALSE); @@ -164,7 +164,6 @@ void fsmc_stop(FSMCDriver *fsmcp) { } } -#if !STM32_NAND_USE_EXT_INT /** * @brief FSMC shared interrupt handler. * @@ -185,7 +184,6 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { #endif CH_IRQ_EPILOGUE(); } -#endif /* !STM32_NAND_USE_EXT_INT */ #endif /* HAL_USE_FSMC */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h index f9d8a60..f0d4c65 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h @@ -15,15 +15,15 @@ */ /** - * @file fsmc.h + * @file hal_fsmc.h * @brief FSMC Driver subsystem low level driver header. * * @addtogroup FSMC * @{ */ -#ifndef _FSMC_H_ -#define _FSMC_H_ +#ifndef HAL_FSMC_H_ +#define HAL_FSMC_H_ #if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) @@ -247,15 +247,6 @@ typedef struct { #define STM32_FSMC_USE_FSMC1 FALSE #endif -/** - * @brief Internal FSMC interrupt enable switch - * @details MCUs in 100-pin package has no dedicated interrupt pin for FSMC. - * You have to use EXTI module instead to workaround this issue. - */ -#if !defined(STM32_NAND_USE_EXT_INT) || defined(__DOXYGEN__) -#define STM32_NAND_USE_EXT_INT FALSE -#endif - /** @} */ /*===========================================================================*/ @@ -344,6 +335,6 @@ extern "C" { #endif /* HAL_USE_FSMC */ -#endif /* _FSMC_H_ */ +#endif /* HAL_FSMC_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c index 95f47d5..ac83477 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c @@ -18,7 +18,7 @@ */ /** - * @file fsmc_sdram.c + * @file hal_fsmc_sdram.c * @brief SDRAM Driver subsystem low level driver source. * * @addtogroup SDRAM diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h index cef6772..b419168 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h @@ -18,15 +18,15 @@ */ /** - * @file fsmc_sdram.h + * @file hal_fsmc_sdram.h * @brief SDRAM Driver subsystem low level driver header. * * @addtogroup SDRAM * @{ */ -#ifndef _FMC_SDRAM_H_ -#define _FMC_SDRAM_H_ +#ifndef HAL_FMC_SDRAM_H_ +#define HAL_FMC_SDRAM_H_ #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx)) @@ -166,6 +166,6 @@ extern "C" { #endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ -#endif /* _FMC_SDRAM_H_ */ +#endif /* HAL_FMC_SDRAM_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c index 6f710d4..333362f 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c @@ -15,7 +15,7 @@ */ /** - * @file fsmc_sram.c + * @file hal_fsmc_sram.c * @brief SRAM Driver subsystem low level driver source. * * @addtogroup SRAM diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h index 529bdc7..5e749a8 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h @@ -15,15 +15,15 @@ */ /** - * @file fsmc_sram.h + * @file hal_fsmc_sram.h * @brief SRAM Driver subsystem low level driver header. * * @addtogroup SRAM * @{ */ -#ifndef _FSMC_SRAM_H_ -#define _FSMC_SRAM_H_ +#ifndef HAL_FSMC_SRAM_H_ +#define HAL_FSMC_SRAM_H_ #include "hal_fsmc.h" @@ -167,6 +167,6 @@ extern "C" { #endif /* STM32_USE_FSMC_SRAM */ -#endif /* _FSMC_SRAM_H_ */ +#endif /* HAL_FSMC_SRAM_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c index b37c026..f39ff35 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c @@ -15,7 +15,7 @@ */ /** - * @file nand_lld.c + * @file hal_nand_lld.c * @brief NAND Driver subsystem low level driver source. * * @addtogroup NAND @@ -117,13 +117,10 @@ static uint32_t calc_eccps(NANDDriver *nandp) { * @notapi */ static void nand_ready_isr_enable(NANDDriver *nandp) { -#if STM32_NAND_USE_EXT_INT - nandp->config->ext_nand_isr_enable(); -#else + nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | - FSMC_SR_ILEN | FSMC_SR_IFEN); + FSMC_SR_ILEN | FSMC_SR_IFEN); nandp->nand->SR |= FSMC_SR_IREN; -#endif } /** @@ -134,11 +131,8 @@ static void nand_ready_isr_enable(NANDDriver *nandp) { * @notapi */ static void nand_ready_isr_disable(NANDDriver *nandp) { -#if STM32_NAND_USE_EXT_INT - nandp->config->ext_nand_isr_disable(); -#else + nandp->nand->SR &= ~FSMC_SR_IREN; -#endif } /** @@ -152,10 +146,8 @@ static void nand_isr_handler (NANDDriver *nandp) { osalSysLockFromISR(); -#if !STM32_NAND_USE_EXT_INT osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */ nandp->nand->SR &= ~FSMC_SR_IRS; -#endif switch (nandp->state){ case NAND_READ: @@ -501,12 +493,13 @@ void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { */ uint8_t nand_lld_read_status(NANDDriver *nandp) { - uint8_t status[1] = {0x01}; /* presume worse */ + uint8_t status; + status = 1; /* presume worse */ nand_lld_write_cmd(nandp, NAND_CMD_STATUS); - nand_lld_polled_read_data(nandp, status, 1); + nand_lld_polled_read_data(nandp, &status, 1); - return status[0]; + return status; } #endif /* HAL_USE_NAND */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h index 8dca42f..de7a0c4 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h @@ -15,15 +15,15 @@ */ /** - * @file nand_lld.h + * @file hal_nand_lld.h * @brief NAND Driver subsystem low level driver header. * * @addtogroup NAND * @{ */ -#ifndef _NAND_LLD_H_ -#define _NAND_LLD_H_ +#ifndef HAL_NAND_LLD_H_ +#define HAL_NAND_LLD_H_ #include "hal_fsmc.h" #include "bitmap.h" @@ -120,10 +120,6 @@ #error "FSMC not present in the selected device" #endif -#if STM32_NAND_USE_EXT_INT && !HAL_USE_EXT -#error "External interrupt controller must be enabled to use this feature" -#endif - #if !defined(STM32_DMA_REQUIRED) #define STM32_DMA_REQUIRED #endif @@ -133,11 +129,6 @@ /*===========================================================================*/ /** - * @brief NAND driver condition flags type. - */ -typedef uint32_t nandflags_t; - -/** * @brief Type of a structure representing an NAND driver. */ typedef struct NANDDriver NANDDriver; @@ -147,23 +138,12 @@ typedef struct NANDDriver NANDDriver; */ typedef void (*nandisrhandler_t)(NANDDriver *nandp); -#if STM32_NAND_USE_EXT_INT -/** - * @brief Type of function switching external interrupts on and off. - */ -typedef void (*nandisrswitch_t)(void); -#endif /* STM32_NAND_USE_EXT_INT */ - /** * @brief Driver configuration structure. * @note It could be empty on some architectures. */ typedef struct { /** - * @brief Pointer to lower level driver. - */ - //const FSMCDriver *fsmcp; - /** * @brief Number of erase blocks in NAND device. */ uint32_t blocks; @@ -197,16 +177,6 @@ typedef struct { * from STMicroelectronics. */ uint32_t pmem; -#if STM32_NAND_USE_EXT_INT - /** - * @brief Function enabling interrupts from EXTI - */ - nandisrswitch_t ext_nand_isr_enable; - /** - * @brief Function disabling interrupts from EXTI - */ - nandisrswitch_t ext_nand_isr_disable; -#endif /* STM32_NAND_USE_EXT_INT */ } NANDConfig; /** @@ -319,6 +289,6 @@ extern "C" { #endif /* HAL_USE_NAND */ -#endif /* _NAND_LLD_H_ */ +#endif /* HAL_NAND_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c index e5f9a09..f0fd289 100644 --- a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c +++ b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c @@ -15,7 +15,7 @@ */ /** - * @file stm32_ltdc.c + * @file hal_stm32_ltdc.c * @brief LCD-TFT Controller Driver. */ diff --git a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h index 16b38ca..5db89e2 100644 --- a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h +++ b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h @@ -15,15 +15,15 @@ */ /** - * @file stm32_ltdc.h + * @file hal_stm32_ltdc.h * @brief LCD-TFT Controller Driver. * * @addtogroup ltdc * @{ */ -#ifndef _STM32_LTDC_H_ -#define _STM32_LTDC_H_ +#ifndef HAL_STM32_LTDC_H_ +#define HAL_STM32_LTDC_H_ /** * @brief Using the LTDC driver. @@ -731,6 +731,6 @@ extern "C" { #endif /* STM32_LTDC_USE_LTDC */ -#endif /* _STM32_LTDC_H_ */ +#endif /* HAL_STM32_LTDC_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h index 927eb6f..e72098e 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h @@ -22,8 +22,8 @@ 32-bit timers and timers with single capture/compare channels. */ -#ifndef __EICU_LLD_H -#define __EICU_LLD_H +#ifndef HAL_EICU_LLD_H +#define HAL_EICU_LLD_H #include "stm32_tim.h" @@ -551,4 +551,4 @@ extern "C" { #endif /* HAL_USE_EICU */ -#endif /* __EICU_LLD_H */ +#endif /* HAL_EICU_LLD_H */ diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c index 8ab6176..c55fae2 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c @@ -24,7 +24,7 @@ /** - * @file STM32/timcap_lld.c + * @file STM32/hal_timcap_lld.c * @brief STM32 TIMCAP subsystem low level driver header. * * @addtogroup TIMCAP diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h index d39c438..643798a 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h @@ -22,8 +22,8 @@ * @{ */ -#ifndef _TIMCAP_LLD_H_ -#define _TIMCAP_LLD_H_ +#ifndef HAL_TIMCAP_LLD_H_ +#define HAL_TIMCAP_LLD_H_ #include "ch.h" #include "hal.h" diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h b/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h index ca2dc49..b88e620 100644 --- a/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h +++ b/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h @@ -15,7 +15,7 @@ */ /** - * @file stm32_otg.h + * @file hal_stm32_otg.h * @brief STM32 OTG registers layout header. * * @addtogroup USB @@ -23,8 +23,8 @@ */ -#ifndef _STM32_OTG_H_ -#define _STM32_OTG_H_ +#ifndef HAL_STM32_OTG_H_ +#define HAL_STM32_OTG_H_ /** * @brief Number of the implemented endpoints in OTG_FS. diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h index e8df749..5c0ac40 100644 --- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h +++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h @@ -15,8 +15,8 @@ limitations under the License. */ -#ifndef USBH_LLD_H_ -#define USBH_LLD_H_ +#ifndef HAL_USBH_LLD_H_ +#define HAL_USBH_LLD_H_ #include "hal.h" @@ -150,4 +150,4 @@ uint8_t usbh_lld_roothub_get_statuschange_bitmap(USBHDriver *usbh); #endif -#endif /* USBH_LLD_H_ */ +#endif /* HAL_USBH_LLD_H_ */ diff --git a/os/hal/src/hal_nand.c b/os/hal/src/hal_nand.c index 24dd6de..e1b298a 100644 --- a/os/hal/src/hal_nand.c +++ b/os/hal/src/hal_nand.c @@ -80,16 +80,13 @@ static void pagesize_check(size_t page_data_size) { */ static void calc_addr(const NANDConfig *cfg, uint32_t block, uint32_t page, uint32_t page_offset, uint8_t *addr, size_t addr_len) { - size_t i = 0; - uint32_t row = 0; + size_t i; + uint32_t row; - /* Incorrect buffer length.*/ osalDbgCheck(cfg->rowcycles + cfg->colcycles == addr_len); osalDbgCheck((block < cfg->blocks) && (page < cfg->pages_per_block) && (page_offset < cfg->page_data_size + cfg->page_spare_size)); - /* convert address to NAND specific */ - memset(addr, 0, addr_len); row = (block * cfg->pages_per_block) + page; for (i=0; i<cfg->colcycles; i++){ addr[i] = page_offset & 0xFF; @@ -115,17 +112,14 @@ static void calc_addr(const NANDConfig *cfg, uint32_t block, uint32_t page, */ static void calc_blk_addr(const NANDConfig *cfg, uint32_t block, uint8_t *addr, size_t addr_len) { - size_t i = 0; - uint32_t row = 0; + size_t i; + uint32_t row; - /* Incorrect buffer length.*/ - osalDbgCheck(cfg->rowcycles == addr_len); - osalDbgCheck((block < cfg->blocks)); + osalDbgCheck(cfg->rowcycles == addr_len); /* Incorrect buffer length */ + osalDbgCheck(block < cfg->blocks); /* Overflow */ - /* convert address to NAND specific */ - memset(addr, 0, addr_len); row = block * cfg->pages_per_block; - for (i=0; i<addr_len; i++){ + for (i=0; i<addr_len; i++) { addr[i] = row & 0xFF; row = row >> 8; } @@ -415,7 +409,6 @@ void nandReadPageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, const uint8_t *spare, size_t sparelen) { - uint8_t retVal; const NANDConfig *cfg = nandp->config; uint8_t addr[8]; size_t addrlen = cfg->rowcycles + cfg->colcycles; @@ -425,8 +418,7 @@ uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, osalDbgAssert(nandp->state == NAND_READY, "invalid state"); calc_addr(cfg, block, page, cfg->page_data_size, addr, addrlen); - retVal = nand_lld_write_data(nandp, spare, sparelen, addr, addrlen, NULL); - return retVal; + return nand_lld_write_data(nandp, spare, sparelen, addr, addrlen, NULL); } /** @@ -478,7 +470,6 @@ uint8_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page) { */ uint8_t nandErase(NANDDriver *nandp, uint32_t block) { - uint8_t retVal; const NANDConfig *cfg = nandp->config; uint8_t addr[4]; size_t addrlen = cfg->rowcycles; @@ -487,8 +478,7 @@ uint8_t nandErase(NANDDriver *nandp, uint32_t block) { osalDbgAssert(nandp->state == NAND_READY, "invalid state"); calc_blk_addr(cfg, block, addr, addrlen); - retVal = nand_lld_erase(nandp, addr, addrlen); - return retVal; + return nand_lld_erase(nandp, addr, addrlen); } /** diff --git a/os/hal/src/hal_onewire.c b/os/hal/src/hal_onewire.c index a93eec0..4e80807 100644 --- a/os/hal/src/hal_onewire.c +++ b/os/hal/src/hal_onewire.c @@ -46,7 +46,7 @@ on every timer overflow event. */ /** - * @file onewire.c + * @file hal_onewire.c * @brief 1-wire Driver code. * * @addtogroup onewire @@ -251,7 +251,6 @@ static void ow_write_bit_I(onewireDriver *owp, ioline_t bit) { static void ow_reset_cb(PWMDriver *pwmp, onewireDriver *owp) { owp->reg.slave_present = (PAL_LOW == ow_read_bit(owp)); - osalSysLockFromISR(); pwmDisableChannelI(pwmp, owp->config->sample_channel); osalThreadResumeI(&owp->thread, MSG_OK); @@ -661,7 +660,7 @@ bool onewireReset(onewireDriver *owp) { pwmcfg->channels[mch].callback = NULL; pwmcfg->channels[mch].mode = owp->config->pwmmode; pwmcfg->channels[sch].callback = pwm_reset_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW; + pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED; ow_bus_active(owp); @@ -714,7 +713,7 @@ void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) { pwmcfg->channels[mch].callback = NULL; pwmcfg->channels[mch].mode = owp->config->pwmmode; pwmcfg->channels[sch].callback = pwm_read_bit_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW; + pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED; ow_bus_active(owp); osalSysLock(); @@ -848,7 +847,7 @@ size_t onewireSearchRom(onewireDriver *owp, uint8_t *result, pwmcfg->channels[mch].callback = NULL; pwmcfg->channels[mch].mode = owp->config->pwmmode; pwmcfg->channels[sch].callback = pwm_search_rom_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW; + pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED; ow_bus_active(owp); osalSysLock(); @@ -882,7 +881,7 @@ size_t onewireSearchRom(onewireDriver *owp, uint8_t *result, * Include test code (if enabled). */ #if ONEWIRE_SYNTH_SEARCH_TEST -#include "search_rom_synth.c" +#include "synth_searchrom.c" #endif #endif /* HAL_USE_ONEWIRE */ diff --git a/os/hal/src/hal_timcap.c b/os/hal/src/hal_timcap.c index a352490..309c147 100644 --- a/os/hal/src/hal_timcap.c +++ b/os/hal/src/hal_timcap.c @@ -19,7 +19,7 @@ */ /** - * @file timcap.c + * @file hal_timcap.c * @brief TIMCAP Driver code. * * @addtogroup TIMCAP diff --git a/os/hal/src/hal_usb_msd.c b/os/hal/src/hal_usb_msd.c new file mode 100644 index 0000000..068d698 --- /dev/null +++ b/os/hal/src/hal_usb_msd.c @@ -0,0 +1,408 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_usb_msd.c + * @brief USM mass storage device code. + * + * @addtogroup usb_msd + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_USB_MSD == TRUE) || defined(__DOXYGEN__) + +#include <string.h> + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define MSD_REQ_RESET 0xFF +#define MSD_GET_MAX_LUN 0xFE + +#define MSD_CBW_SIGNATURE 0x43425355 +#define MSD_CSW_SIGNATURE 0x53425355 + +#define MSD_THD_PRIO NORMALPRIO + +#define CBW_FLAGS_RESERVED_MASK 0b01111111 +#define CBW_LUN_RESERVED_MASK 0b11110000 +#define CBW_CMD_LEN_RESERVED_MASK 0b11000000 + +#define CSW_STATUS_PASSED 0x00 +#define CSW_STATUS_FAILED 0x01 +#define CSW_STATUS_PHASE_ERROR 0x02 + +#define MSD_SETUP_WORD(setup, index) (uint16_t)(((uint16_t)setup[index+1] << 8)\ + | (setup[index] & 0x00FF)) + +#define MSD_SETUP_VALUE(setup) MSD_SETUP_WORD(setup, 2) +#define MSD_SETUP_INDEX(setup) MSD_SETUP_WORD(setup, 4) +#define MSD_SETUP_LENGTH(setup) MSD_SETUP_WORD(setup, 6) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ +/** + * @brief USB mass storage driver identifier. + */ +USBMassStorageDriver USBMSD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Hardcoded default SCSI inquiry response structure. + */ +static const scsi_inquiry_response_t default_scsi_inquiry_response = { + 0x00, /* direct access block device */ + 0x80, /* removable */ + 0x04, /* SPC-2 */ + 0x02, /* response data format */ + 0x20, /* response has 0x20 + 4 bytes */ + 0x00, + 0x00, + 0x00, + "Chibios", + "Mass Storage", + {'v',CH_KERNEL_MAJOR+'0','.',CH_KERNEL_MINOR+'0'} +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Checks validity of CBW content. + * @details The device shall consider the CBW valid when: + * • The CBW was received after the device had sent a CSW or after a reset, + * • the CBW is 31 (1Fh) bytes in length, + * • and the dCBWSignature is equal to 43425355h. + * + * @param[in] cbw pointer to the @p msd_cbw_t object + * @param[in] recvd number of received bytes + * + * @return Operation status. + * @retval true CBW is meaningful. + * @retval false CBW is bad. + * + * @notapi + */ +static bool cbw_valid(const msd_cbw_t *cbw, msg_t recvd) { + if ((sizeof(msd_cbw_t) != recvd) || (cbw->signature != MSD_CBW_SIGNATURE)) { + return false; + } + else { + return true; + } +} + +/** + * @brief Checks meaningfulness of CBW content. + * @details The device shall consider the contents of a valid CBW meaningful when: + * • no reserved bits are set, + * • the bCBWLUN contains a valid LUN supported by the device, + * • and both bCBWCBLength and the content of the CBWCB are in + * accordance with bInterfaceSubClass. + * + * @param[in] cbw pointer to the @p msd_cbw_t object + * + * @return Operation status. + * @retval true CBW is meaningful. + * @retval false CBW is bad. + * + * @notapi + */ +static bool cbw_meaningful(const msd_cbw_t *cbw) { + if (((cbw->cmd_len & CBW_CMD_LEN_RESERVED_MASK) != 0) + || ((cbw->flags & CBW_FLAGS_RESERVED_MASK) != 0) + || (cbw->lun != 0)) { + return false; + } + else { + return true; + } +} + +/** + * @brief SCSI transport transmit function. + * + * @param[in] transport pointer to the @p SCSITransport object + * @param[in] data payload + * @param[in] len number of bytes to be transmitted + * + * @return Number of successfully transmitted bytes. + + * @notapi + */ +static uint32_t scsi_transport_transmit(const SCSITransport *transport, + const uint8_t *data, size_t len) { + + usb_scsi_transport_handler_t *trp = transport->handler; + msg_t status = usbTransmit(trp->usbp, trp->ep, data, len); + if (MSG_OK == status) + return len; + else + return 0; +} + +/** + * @brief SCSI transport receive function. + * + * @param[in] transport pointer to the @p SCSITransport object + * @param[in] data payload + * @param[in] len number bytes to be received + * + * @return Number of successfully received bytes. + + * @notapi + */ +static uint32_t scsi_transport_receive(const SCSITransport *transport, + uint8_t *data, size_t len) { + + usb_scsi_transport_handler_t *trp = transport->handler; + msg_t status = usbReceive(trp->usbp, trp->ep, data, len); + if (MSG_RESET != status) + return status; + else + return 0; +} + +/** + * @brief Fills and sends CSW message. + * + * @param[in] msdp pointer to the @p USBMassStorageDriver object + * @param[in] status status returned by SCSI layer + * @param[in] residue number of residue bytes in case of failed transaction + * + * @notapi + */ +static void send_csw(USBMassStorageDriver *msdp, uint8_t status, + uint32_t residue) { + + msdp->csw.signature = MSD_CSW_SIGNATURE; + msdp->csw.data_residue = residue; + msdp->csw.tag = msdp->cbw.tag; + msdp->csw.status = status; + + usbTransmit(msdp->usbp, USB_MSD_DATA_EP, (uint8_t *)&msdp->csw, + sizeof(msd_csw_t)); +} + +/** + * @brief Mass storage worker thread. + * + * @param[in] arg pointer to the @p USBMassStorageDriver object + * + * @notapi + */ +static THD_FUNCTION(usb_msd_worker, arg) { + USBMassStorageDriver *msdp = arg; + + while(! chThdShouldTerminateX()) { + const msg_t status = usbReceive(msdp->usbp, USB_MSD_DATA_EP, + (uint8_t *)&msdp->cbw, sizeof(msd_cbw_t)); + if (MSG_RESET == status) { + osalThreadSleepMilliseconds(50); + } + else if (cbw_valid(&msdp->cbw, status) && cbw_meaningful(&msdp->cbw)) { + if (SCSI_SUCCESS == scsiExecCmd(&msdp->scsi_target, msdp->cbw.cmd_data)) { + send_csw(msdp, CSW_STATUS_PASSED, 0); + } + else { + send_csw(msdp, CSW_STATUS_FAILED, scsiResidue(&msdp->scsi_target)); + } + } + else { + ; /* do NOT send CSW here. Incorrect CBW must be silently ignored */ + } + } + + chThdExit(MSG_OK); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Mass storage specific request hook for USB. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +bool msd_request_hook(USBDriver *usbp) { + + if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) && + ((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE)) { + /* check that the request is for interface 0.*/ + if (MSD_SETUP_INDEX(usbp->setup) != 0) + return false; + + /* act depending on bRequest = setup[1] */ + switch(usbp->setup[1]) { + case MSD_REQ_RESET: + /* check that it is a HOST2DEV request */ + if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) != USB_RTYPE_DIR_HOST2DEV) || + (MSD_SETUP_LENGTH(usbp->setup) != 0) || + (MSD_SETUP_VALUE(usbp->setup) != 0)) { + return false; + } + + /* + As required by the BOT specification, the Bulk-only mass storage reset request (classspecific + request) is implemented. This request is used to reset the mass storage device and + its associated interface. This class-specific request should prepare the device for the next + CBW from the host. + To generate the BOT Mass Storage Reset, the host must send a device request on the + default pipe of: + • bmRequestType: Class, interface, host to device + • bRequest field set to 255 (FFh) + • wValue field set to ‘0’ + • wIndex field set to the interface number + • wLength field set to ‘0’ + */ + chSysLockFromISR(); + + /* release and abandon current transmission */ + usbStallReceiveI(usbp, 1); + usbStallTransmitI(usbp, 1); + /* The device shall NAK the status stage of the device request until + * the Bulk-Only Mass Storage Reset is complete. + * NAK EP1 in and out */ + usbp->otg->ie[1].DIEPCTL = DIEPCTL_SNAK; + usbp->otg->oe[1].DOEPCTL = DOEPCTL_SNAK; + + chSysUnlockFromISR(); + + /* response to this request using EP0 */ + usbSetupTransfer(usbp, 0, 0, NULL); + return true; + + case MSD_GET_MAX_LUN: + /* check that it is a DEV2HOST request */ + if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) != USB_RTYPE_DIR_DEV2HOST) || + (MSD_SETUP_LENGTH(usbp->setup) != 1) || + (MSD_SETUP_VALUE(usbp->setup) != 0)) { + return false; + } + + /* stall to indicate that we don't support LUN */ + osalSysLockFromISR(); + usbStallTransmitI(usbp, 0); + osalSysUnlockFromISR(); + return true; + + default: + return false; + break; + } + } + return false; +} + +/** + * @brief Initializes the standard part of a @p USBMassStorageDriver structure. + * + * @param[out] msdp pointer to the @p USBMassStorageDriver object + * + * @init + */ +void msdObjectInit(USBMassStorageDriver *msdp) { + + memset(msdp, 0x55, sizeof(USBMassStorageDriver)); + msdp->state = USB_MSD_STOP; + msdp->usbp = NULL; + msdp->worker = NULL; + + scsiObjectInit(&msdp->scsi_target); +} + +/** + * @brief Stops the USB mass storage driver. + * + * @param[in] msdp pointer to the @p USBMassStorageDriver object + * + * @api + */ +void msdStop(USBMassStorageDriver *msdp) { + + osalDbgCheck(msdp != NULL); + osalDbgAssert((msdp->state == USB_MSD_READY), "invalid state"); + + chThdTerminate(msdp->worker); + chThdWait(msdp->worker); + + scsiStop(&msdp->scsi_target); + + msdp->worker = NULL; + msdp->state = USB_MSD_STOP; + msdp->usbp = NULL; +} + +/** + * @brief Configures and activates the USB mass storage driver. + * + * @param[in] msdp pointer to the @p USBMassStorageDriver object + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] blkdev pointer to the @p BaseBlockDevice object + * @param[in] blkbuf pointer to the working area buffer, must be allocated + * by user, must be big enough to store 1 data block + * @param[in] inquiry pointer to the SCSI inquiry response structure, + * set it to @p NULL to use default hardcoded value. + * + * @api + */ +void msdStart(USBMassStorageDriver *msdp, USBDriver *usbp, + BaseBlockDevice *blkdev, uint8_t *blkbuf, + const scsi_inquiry_response_t *inquiry) { + + osalDbgCheck((msdp != NULL) && (usbp != NULL) + && (blkdev != NULL) && (blkbuf != NULL)); + osalDbgAssert((msdp->state == USB_MSD_STOP), "invalid state"); + + msdp->usbp = usbp; + + msdp->usb_scsi_transport_handler.usbp = msdp->usbp; + msdp->usb_scsi_transport_handler.ep = USB_MSD_DATA_EP; + msdp->scsi_transport.handler = &msdp->usb_scsi_transport_handler; + msdp->scsi_transport.transmit = scsi_transport_transmit; + msdp->scsi_transport.receive = scsi_transport_receive; + + if (NULL == inquiry) { + msdp->scsi_config.inquiry_response = &default_scsi_inquiry_response; + } + else { + msdp->scsi_config.inquiry_response = inquiry; + } + msdp->scsi_config.blkbuf = blkbuf; + msdp->scsi_config.blkdev = blkdev; + msdp->scsi_config.transport = &msdp->scsi_transport; + + scsiStart(&msdp->scsi_target, &msdp->scsi_config); + + msdp->state = USB_MSD_READY; + msdp->worker = chThdCreateStatic(msdp->waMSDWorker, sizeof(msdp->waMSDWorker), + MSD_THD_PRIO, usb_msd_worker, msdp); +} + +#endif /* HAL_USE_USB_MSD */ + +/** @} */ diff --git a/os/various/bitmap.h b/os/various/bitmap.h index d7831aa..115b54c 100644 --- a/os/various/bitmap.h +++ b/os/various/bitmap.h @@ -22,8 +22,8 @@ * @{ */ -#ifndef _BITMAP_H_ -#define _BITMAP_H_ +#ifndef BITMAP_H_ +#define BITMAP_H_ /*===========================================================================*/ /* Module constants. */ @@ -72,6 +72,6 @@ extern "C" { } #endif -#endif /* _BITMAP_H_ */ +#endif /* BITMAP_H_ */ /** @} */ diff --git a/os/various/dbgtrace.h b/os/various/dbgtrace.h new file mode 100644 index 0000000..b1fc297 --- /dev/null +++ b/os/various/dbgtrace.h @@ -0,0 +1,41 @@ +#ifndef DBGTRACE_H_ +#define DBGTRACE_H_ + +#include "chprintf.h" + +#if !defined(DEBUG_TRACE_PRINT) +#define DEBUG_TRACE_PRINT FALSE +#endif + +#if !defined(DEBUG_TRACE_WARNING) +#define DEBUG_TRACE_WARNING FALSE +#endif + +#if !defined(DEBUG_TRACE_ERROR) +#define DEBUG_TRACE_ERROR FALSE +#endif + +/* user must provide correctly initialized pointer to print channel */ +#if DEBUG_TRACE_PRINT || DEBUG_TRACE_WARNING || DEBUG_TRACE_ERROR +extern BaseSequentialStream *GlobalDebugChannel; +#endif + +#if DEBUG_TRACE_PRINT +#define dbgprintf(fmt, ...) chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__) +#else +#define dbgprintf(fmt, ...) do {} while(0) +#endif + +#if DEBUG_TRACE_WARNING +#define warnprintf(fmt, ...) chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__) +#else +#define warnprintf(fmt, ...) do {} while(0) +#endif + +#if DEBUG_TRACE_ERROR +#define errprintf(fmt, ...) chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__) +#else +#define errprintf(fmt, ...) do {} while(0) +#endif + +#endif /* DBGTRACE_H_ */ diff --git a/os/various/lib_scsi.c b/os/various/lib_scsi.c new file mode 100644 index 0000000..55aeb7e --- /dev/null +++ b/os/various/lib_scsi.c @@ -0,0 +1,507 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file lib_scsi.c + * @brief SCSI target driver source code. + * + * @addtogroup SCSI + * @{ + */ + +#include <string.h> + +#include "hal.h" + +#include "lib_scsi.h" + +#define DEBUG_TRACE_PRINT FALSE +#define DEBUG_TRACE_WARNING FALSE +#define DEBUG_TRACE_ERROR FALSE +#include "dbgtrace.h" + +#define ARCH_LITTLE_ENDIAN +#include "bswap.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +typedef struct { + uint32_t first_lba; + uint16_t blk_cnt; +} data_request_t; + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Combines data request from byte array. + * + * @notapi + */ +static data_request_t decode_data_request(const uint8_t *cmd) { + + data_request_t req; + uint32_t lba; + uint16_t blk; + + memcpy(&lba, &cmd[2], sizeof(lba)); + memcpy(&blk, &cmd[7], sizeof(blk)); + + req.first_lba = be32_to_cpu(lba); + req.blk_cnt = be16_to_cpu(blk); + + return req; +} + +/** + * @brief Fills sense structure. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] key SCSI sense key + * @param[in] code SCSI sense code + * @param[in] qual SCSI sense qualifier + * + * @notapi + */ +static void set_sense(SCSITarget *scsip, uint8_t key, + uint8_t code, uint8_t qual) { + + scsi_sense_response_t *sense = &scsip->sense; + memset(sense, 0 , sizeof(scsi_sense_response_t)); + + sense->byte[0] = 0x70; + sense->byte[2] = key; + sense->byte[7] = 8; + sense->byte[12] = code; + sense->byte[13] = qual; +} + +/** + * @brief Sets all values in sense data to 'success' condition. + * + * @param[in] scsip pointer to @p SCSITarget structure + * + * @notapi + */ +static void set_sense_ok(SCSITarget *scsip) { + set_sense(scsip, SCSI_SENSE_KEY_GOOD, + SCSI_ASENSE_NO_ADDITIONAL_INFORMATION, + SCSI_ASENSEQ_NO_QUALIFIER); +} + +/** + * @brief Transmits data via transport channel. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] data pointer to data buffer + * @param[in] len number of bytes to be transmitted + * + * @return The operation status. + * + * @notapi + */ +static bool transmit_data(SCSITarget *scsip, const uint8_t *data, uint32_t len) { + + const SCSITransport *trp = scsip->config->transport; + const uint32_t residue = len - trp->transmit(trp, data, len); + + if (residue > 0) { + scsip->residue = residue; + return SCSI_FAILED; + } + else { + return SCSI_SUCCESS; + } +} + +/** + * @brief Stub for unhandled SCSI commands. + * @details Sets error flags in sense data structure and returns error error. + */ +static bool cmd_unhandled(SCSITarget *scsip, const uint8_t *cmd) { + (void)cmd; + + set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, + SCSI_ASENSE_INVALID_COMMAND, + SCSI_ASENSEQ_NO_QUALIFIER); + return SCSI_FAILED; +} + +/** + * @brief Stub for unrealized but required SCSI commands. + * @details Sets sense data in 'all OK' condition and returns success status. + */ +static bool cmd_ignored(SCSITarget *scsip, const uint8_t *cmd) { + (void)scsip; + (void)cmd; + + set_sense_ok(scsip); + return SCSI_SUCCESS; +} + +/** + * @brief SCSI inquiry command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool inquiry(SCSITarget *scsip, const uint8_t *cmd) { + + if ((cmd[1] & 0b11) || cmd[2] != 0) { + set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, + SCSI_ASENSE_INVALID_FIELD_IN_CDB, + SCSI_ASENSEQ_NO_QUALIFIER); + return SCSI_FAILED; + } + else { + return transmit_data(scsip, (const uint8_t *)scsip->config->inquiry_response, + sizeof(scsi_inquiry_response_t)); + } +} + +/** + * @brief SCSI request sense command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool request_sense(SCSITarget *scsip, const uint8_t *cmd) { + + uint32_t tmp; + memcpy(&tmp, &cmd[1], 3); + + if ((tmp != 0) || (cmd[4] != sizeof(scsi_sense_response_t))) { + set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, + SCSI_ASENSE_INVALID_FIELD_IN_CDB, + SCSI_ASENSEQ_NO_QUALIFIER); + return SCSI_FAILED; + } + else { + return transmit_data(scsip, (uint8_t *)&scsip->sense, + sizeof(scsi_sense_response_t)); + } +} + +/** + * @brief SCSI mode sense (6) command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool mode_sense6(SCSITarget *scsip, const uint8_t *cmd) { + (void)cmd; + + scsip->mode_sense.byte[0] = sizeof(scsi_mode_sense6_response_t) - 1; + scsip->mode_sense.byte[1] = 0; + if (blkIsWriteProtected(scsip->config->blkdev)) { + scsip->mode_sense.byte[2] = 0x01 << 7; + } + else { + scsip->mode_sense.byte[2] = 0; + } + scsip->mode_sense.byte[3] = 0; + + return transmit_data(scsip, (uint8_t *)&scsip->mode_sense, + sizeof(scsi_mode_sense6_response_t)); +} + +/** + * @brief SCSI read format capacities command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool read_format_capacities(SCSITarget *scsip, const uint8_t *cmd) { + + /* An Allocation Length of zero indicates that no data shall be transferred. + This condition shall not be considered as an error. The Logical Unit + shall terminate the data transfer when Allocation Length bytes have + been transferred or when all available data have been transferred to + the Initiator, whatever is less. */ + + uint16_t len = cmd[7] << 8 | cmd[8]; + + if (0 == len) { + return SCSI_SUCCESS; + } + else { + scsi_read_format_capacities_response_t ret; + BlockDeviceInfo bdi; + blkGetInfo(scsip->config->blkdev, &bdi); + + uint32_t tmp = cpu_to_be32(bdi.blk_num); + memcpy(ret.blocknum, &tmp, 4); + + uint8_t formatted_media = 0b10; + uint16_t blocklen = bdi.blk_size; + ret.blocklen[0] = formatted_media; + ret.blocklen[1] = 0; + ret.blocklen[2] = blocklen >> 8; + ret.blocklen[3] = blocklen & 0xFF; + + ret.header[3] = 1 * 8; + + return transmit_data(scsip, (uint8_t *)&ret, + sizeof(scsi_read_format_capacities_response_t)); + } +} + +/** + * @brief SCSI read capacity (10) command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool read_capacity10(SCSITarget *scsip, const uint8_t *cmd) { + + (void)cmd; + + BlockDeviceInfo bdi; + blkGetInfo(scsip->config->blkdev, &bdi); + scsi_read_capacity10_response_t ret; + ret.block_size = cpu_to_be32(bdi.blk_size); + ret.last_block_addr = cpu_to_be32(bdi.blk_num - 1); + + return transmit_data(scsip, (uint8_t *)&ret, + sizeof(scsi_read_capacity10_response_t)); +} + +/** + * @brief Checks data request for media overflow. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * @retval true When media overflow detected. + * @retval false Otherwise. + * + * @notapi + */ +static bool data_overflow(SCSITarget *scsip, const data_request_t *req) { + + BlockDeviceInfo bdi; + blkGetInfo(scsip->config->blkdev, &bdi); + + if (req->first_lba + req->blk_cnt > bdi.blk_num) { + set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, + SCSI_ASENSE_LBA_OUT_OF_RANGE, + SCSI_ASENSEQ_NO_QUALIFIER); + return true; + } + else { + return false; + } +} + +/** + * @brief SCSI read/write (10) command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool data_read_write10(SCSITarget *scsip, const uint8_t *cmd) { + + data_request_t req = decode_data_request(cmd); + + if (data_overflow(scsip, &req)) { + return SCSI_FAILED; + } + else { + const SCSITransport *tr = scsip->config->transport; + BaseBlockDevice *blkdev = scsip->config->blkdev; + BlockDeviceInfo bdi; + blkGetInfo(blkdev, &bdi); + size_t bs = bdi.blk_size; + uint8_t *buf = scsip->config->blkbuf; + + for (size_t i=0; i<req.blk_cnt; i++) { + if (cmd[0] == SCSI_CMD_READ_10) { + // TODO: block error handling + blkRead(blkdev, req.first_lba + i, buf, 1); + tr->transmit(tr, buf, bs); + } + else { + // TODO: block error handling + tr->receive(tr, buf, bs); + blkWrite(blkdev, req.first_lba + i, buf, 1); + } + } + } + return SCSI_SUCCESS; +} +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Executes SCSI command encoded in byte array. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @api + */ +bool scsiExecCmd(SCSITarget *scsip, const uint8_t *cmd) { + + /* status will be overwritten later in case of error */ + set_sense_ok(scsip); + + switch (cmd[0]) { + case SCSI_CMD_INQUIRY: + dbgprintf("SCSI_CMD_INQUIRY\r\n"); + return inquiry(scsip, cmd); + + case SCSI_CMD_REQUEST_SENSE: + dbgprintf("SCSI_CMD_REQUEST_SENSE\r\n"); + return request_sense(scsip, cmd); + + case SCSI_CMD_READ_CAPACITY_10: + dbgprintf("SCSI_CMD_READ_CAPACITY_10\r\n"); + return read_capacity10(scsip, cmd); + + case SCSI_CMD_READ_10: + dbgprintf("SCSI_CMD_READ_10\r\n"); + return data_read_write10(scsip, cmd); + + case SCSI_CMD_WRITE_10: + dbgprintf("SCSI_CMD_WRITE_10\r\n"); + return data_read_write10(scsip, cmd); + + case SCSI_CMD_TEST_UNIT_READY: + dbgprintf("SCSI_CMD_TEST_UNIT_READY\r\n"); + return cmd_ignored(scsip, cmd); + + case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL: + dbgprintf("SCSI_CMD_ALLOW_MEDIUM_REMOVAL\r\n"); + return cmd_ignored(scsip, cmd); + + case SCSI_CMD_MODE_SENSE_6: + dbgprintf("SCSI_CMD_MODE_SENSE_6\r\n"); + return mode_sense6(scsip, cmd); + + case SCSI_CMD_READ_FORMAT_CAPACITIES: + dbgprintf("SCSI_CMD_READ_FORMAT_CAPACITIES\r\n"); + return read_format_capacities(scsip, cmd); + + case SCSI_CMD_VERIFY_10: + dbgprintf("SCSI_CMD_VERIFY_10\r\n"); + return cmd_ignored(scsip, cmd); + + default: + warnprintf("SCSI unhandled command: %X\r\n", cmd[0]); + return cmd_unhandled(scsip, cmd); + } +} + +/** + * @brief Driver structure initialization. + * + * @param[in] scsip pointer to @p SCSITarget structure + * + * @api + */ +void scsiObjectInit(SCSITarget *scsip) { + + scsip->config = NULL; + scsip->residue = 0; + memset(&scsip->sense, 0 , sizeof(scsi_sense_response_t)); + scsip->state = SCSI_TRGT_STOP; +} + +/** + * @brief Starts SCSITarget driver. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] config pointer to @p SCSITargetConfig structure + * + * @api + */ +void scsiStart(SCSITarget *scsip, const SCSITargetConfig *config) { + + scsip->config = config; + scsip->state = SCSI_TRGT_READY; +} + +/** + * @brief Stops SCSITarget driver. + * + * @param[in] scsip pointer to @p SCSITarget structure + * + * @api + */ +void scsiStop(SCSITarget *scsip) { + + scsip->config = NULL; + scsip->state = SCSI_TRGT_STOP; +} + +/** + * @brief Retrieves residue bytes. + * + * @param[in] scsip pointer to @p SCSITarget structure + * + * @return Residue bytes. + * + * @api + */ +uint32_t scsiResidue(const SCSITarget *scsip) { + + return scsip->residue; +} + +/** @} */ diff --git a/os/various/lib_scsi.h b/os/various/lib_scsi.h new file mode 100644 index 0000000..97badb0 --- /dev/null +++ b/os/various/lib_scsi.h @@ -0,0 +1,278 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file wdg_lld.h + * @brief WDG Driver subsystem low level driver header template. + * + * @addtogroup WDG + * @{ + */ + +#ifndef LIB_SCSI_H_ +#define LIB_SCSI_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SCSI_CMD_TEST_UNIT_READY 0x00 +#define SCSI_CMD_REQUEST_SENSE 0x03 +#define SCSI_CMD_INQUIRY 0x12 +#define SCSI_CMD_MODE_SENSE_6 0x1A +#define SCSI_CMD_START_STOP_UNIT 0x1B +#define SCSI_CMD_SEND_DIAGNOSTIC 0x1D +#define SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E +#define SCSI_CMD_READ_CAPACITY_10 0x25 +#define SCSI_CMD_READ_FORMAT_CAPACITIES 0x23 +#define SCSI_CMD_READ_10 0x28 +#define SCSI_CMD_WRITE_10 0x2A +#define SCSI_CMD_VERIFY_10 0x2F + +#define SCSI_SENSE_KEY_GOOD 0x00 +#define SCSI_SENSE_KEY_RECOVERED_ERROR 0x01 +#define SCSI_SENSE_KEY_NOT_READY 0x02 +#define SCSI_SENSE_KEY_MEDIUM_ERROR 0x03 +#define SCSI_SENSE_KEY_HARDWARE_ERROR 0x04 +#define SCSI_SENSE_KEY_ILLEGAL_REQUEST 0x05 +#define SCSI_SENSE_KEY_UNIT_ATTENTION 0x06 +#define SCSI_SENSE_KEY_DATA_PROTECT 0x07 +#define SCSI_SENSE_KEY_BLANK_CHECK 0x08 +#define SCSI_SENSE_KEY_VENDOR_SPECIFIC 0x09 +#define SCSI_SENSE_KEY_COPY_ABORTED 0x0A +#define SCSI_SENSE_KEY_ABORTED_COMMAND 0x0B +#define SCSI_SENSE_KEY_VOLUME_OVERFLOW 0x0D +#define SCSI_SENSE_KEY_MISCOMPARE 0x0E + +#define SCSI_ASENSE_NO_ADDITIONAL_INFORMATION 0x00 +#define SCSI_ASENSE_LOGICAL_UNIT_NOT_READY 0x04 +#define SCSI_ASENSE_INVALID_FIELD_IN_CDB 0x24 +#define SCSI_ASENSE_NOT_READY_TO_READY_CHANGE 0x28 +#define SCSI_ASENSE_WRITE_PROTECTED 0x27 +#define SCSI_ASENSE_FORMAT_ERROR 0x31 +#define SCSI_ASENSE_INVALID_COMMAND 0x20 +#define SCSI_ASENSE_LBA_OUT_OF_RANGE 0x21 +#define SCSI_ASENSE_MEDIUM_NOT_PRESENT 0x3A + +#define SCSI_ASENSEQ_NO_QUALIFIER 0x00 +#define SCSI_ASENSEQ_FORMAT_COMMAND_FAILED 0x01 +#define SCSI_ASENSEQ_INIT_COMMAND_REQUIRED 0x02 +#define SCSI_ASENSEQ_OPERATION_IN_PROGRESS 0x07 + +#define SCSI_SUCCESS HAL_SUCCESS +#define SCSI_FAILED HAL_FAILED + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SCSI target. + */ +typedef struct SCSITarget SCSITarget; + +/** + * @brief Type of a structure representing an SCSI transport. + */ +typedef struct SCSITransport SCSITransport; + +/** + * @brief State of SCSI target. + */ +typedef enum { + SCSI_TRGT_UNINIT = 0, + SCSI_TRGT_STOP, + SCSI_TRGT_READY, +} scsitrgtstate_t; + +/** + * @brief Represents SCSI sense data structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR { + uint8_t byte[18]; +} scsi_sense_response_t; + +/** + * @brief Represents SCSI inquiry response structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR { + uint8_t peripheral; + uint8_t removable; + uint8_t version; + uint8_t response_data_format; + uint8_t additional_length; + uint8_t sccstp; + uint8_t bqueetc; + uint8_t cmdque; + uint8_t vendorID[8]; + uint8_t productID[16]; + uint8_t productRev[4]; +} scsi_inquiry_response_t; + +/** + * @brief Represents SCSI mode sense (6) request structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR { + uint8_t byte[6]; +} scsi_mode_sense6_request_t; + +/** + * @brief Represents SCSI mode sense (6) response structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR{ + uint8_t byte[4]; +} scsi_mode_sense6_response_t; + +/** + * @brief Represents SCSI read capacity (10) response structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR { + uint32_t last_block_addr; + uint32_t block_size; +} scsi_read_capacity10_response_t; + +/** + * @brief Represents SCSI read format capacity response structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR { + uint8_t header[4]; + uint8_t blocknum[4]; + uint8_t blocklen[4]; +} scsi_read_format_capacities_response_t; + +/** + * @brief Type of a SCSI transport transmit call. + * + * @param[in] usbp pointer to the @p SCSITransport object + * @param[in] data pointer to payload buffer + * @param[in] len payload length + */ +typedef uint32_t (*scsi_transport_transmit_t)(const SCSITransport *transport, + const uint8_t *data, size_t len); + +/** + * @brief Type of a SCSI transport transmit call. + * + * @param[in] usbp pointer to the @p SCSITransport object + * @param[out] data pointer to receive buffer + * @param[in] len number of bytes to be received + */ +typedef uint32_t (*scsi_transport_receive_t)(const SCSITransport *transport, + uint8_t *data, size_t len); + +/** + * @brief SCSI transport structure. + */ +struct SCSITransport { + /** + * @brief Transmit call provided by lower level driver. + */ + scsi_transport_transmit_t transmit; + /** + * @brief Receive call provided by lower level driver. + */ + scsi_transport_receive_t receive; + /** + * @brief Transport handler provided by lower level driver. + */ + void *handler; +}; + +/** + * @brief SCSI target config structure. + */ +typedef struct { + /** + * @brief Pointer to @p SCSITransport object. + */ + const SCSITransport *transport; + /** + * @brief Pointer to @p BaseBlockDevice object. + */ + BaseBlockDevice *blkdev; + /** + * @brief Pointer to data buffer for single block. + */ + uint8_t *blkbuf; + /** + * @brief Pointer to SCSI inquiry response object. + */ + const scsi_inquiry_response_t *inquiry_response; +} SCSITargetConfig; + +/** + * + */ +struct SCSITarget { + /** + * @brief Pointer to @p SCSITargetConfig object. + */ + const SCSITargetConfig *config; + /** + * @brief Target state. + */ + scsitrgtstate_t state; + /** + * @brief SCSI sense response structure. + */ + scsi_sense_response_t sense; + /** + * @brief SCSI mode sense (6) response structure. + */ + scsi_mode_sense6_response_t mode_sense; + /** + * @brief Residue bytes. + */ + uint32_t residue; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void scsiObjectInit(SCSITarget *scsip); + void scsiStart(SCSITarget *scsip, const SCSITargetConfig *config); + void scsiStop(SCSITarget *scsip); + bool scsiExecCmd(SCSITarget *scsip, const uint8_t *cmd); + uint32_t scsiResidue(const SCSITarget *scsip); +#ifdef __cplusplus +} +#endif + +#endif /* LIB_SCSI_H_ */ + +/** @} */ diff --git a/os/various/ramdisk.c b/os/various/ramdisk.c new file mode 100644 index 0000000..08abdca --- /dev/null +++ b/os/various/ramdisk.c @@ -0,0 +1,219 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ramdisk.c + * @brief Virtual block devise driver source. + * + * @addtogroup ramdisk + * @{ + */ + +#include "hal.h" + +#include "ramdisk.h" + +#include <string.h> + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/* + * Interface implementation. + */ +static bool overflow(const RamDisk *rd, uint32_t startblk, uint32_t n) { + return (startblk + n) > rd->blk_num; +} + +static bool is_inserted(void *instance) { + (void)instance; + return true; +} + +static bool is_protected(void *instance) { + RamDisk *rd = instance; + if (BLK_READY == rd->state) { + return rd->readonly; + } + else { + return true; + } +} + +static bool connect(void *instance) { + RamDisk *rd = instance; + if (BLK_STOP == rd->state) { + rd->state = BLK_READY; + } + return HAL_SUCCESS; +} + +static bool disconnect(void *instance) { + RamDisk *rd = instance; + if (BLK_STOP != rd->state) { + rd->state = BLK_STOP; + } + return HAL_SUCCESS; +} + +static bool read(void *instance, uint32_t startblk, + uint8_t *buffer, uint32_t n) { + + RamDisk *rd = instance; + + if (overflow(rd, startblk, n)) { + return HAL_FAILED; + } + else { + const uint32_t bs = rd->blk_size; + memcpy(buffer, &rd->storage[startblk * bs], n * bs); + return HAL_SUCCESS; + } +} + +static bool write(void *instance, uint32_t startblk, + const uint8_t *buffer, uint32_t n) { + + RamDisk *rd = instance; + if (overflow(rd, startblk, n)) { + return HAL_FAILED; + } + else { + const uint32_t bs = rd->blk_size; + memcpy(&rd->storage[startblk * bs], buffer, n * bs); + return HAL_SUCCESS; + } +} + +static bool sync(void *instance) { + + RamDisk *rd = instance; + if (BLK_READY != rd->state) { + return HAL_FAILED; + } + else { + return HAL_SUCCESS; + } +} + +static bool get_info(void *instance, BlockDeviceInfo *bdip) { + + RamDisk *rd = instance; + if (BLK_READY != rd->state) { + return HAL_FAILED; + } + else { + bdip->blk_num = rd->blk_num; + bdip->blk_size = rd->blk_size; + return HAL_SUCCESS; + } +} + +/** + * + */ +static const struct BaseBlockDeviceVMT vmt = { + is_inserted, + is_protected, + connect, + disconnect, + read, + write, + sync, + get_info +}; + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief RAM disk object initialization. + * + * @param[in] rdp pointer to @p RamDisk object + * + * @init + */ +void ramdiskObjectInit(RamDisk *rdp) { + + rdp->vmt = &vmt; + rdp->state = SD_STOP; +} + +/** + * @brief Starts RAM disk. + * + * @param[in] rdp pointer to @p RamDisk object + * @param[in] storage pointer to array representing disk storage + * @param[in] blksize size of blocks in bytes + * @param[in] blknum total number of blocks in device + * @param[in] readonly read only flag + * + * @api + */ +void ramdiskStart(RamDisk *rdp, uint8_t *storage, uint32_t blksize, + uint32_t blknum, bool readonly) { + + osalDbgCheck(rdp != NULL); + + osalSysLock(); + osalDbgAssert((rdp->state == BLK_STOP) || (rdp->state == BLK_READY), + "invalid state"); + rdp->blk_num = blknum; + rdp->blk_size = blksize; + rdp->readonly = readonly; + rdp->storage = storage; + rdp->state = BLK_READY; + osalSysUnlock(); +} + +/** + * @brief Stops RAM disk. + * + * @param[in] rdp pointer to @p RamDisk object + * + * @api + */ +void ramdiskStop(RamDisk *rdp) { + + osalDbgCheck(rdp != NULL); + + osalSysLock(); + osalDbgAssert((rdp->state == BLK_STOP) || (rdp->state == BLK_READY), + "invalid state"); + rdp->storage = NULL; + rdp->state = BLK_STOP; + osalSysUnlock(); +} + +/** @} */ diff --git a/os/various/ramdisk.h b/os/various/ramdisk.h new file mode 100644 index 0000000..0860662 --- /dev/null +++ b/os/various/ramdisk.h @@ -0,0 +1,86 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ramdisk.h + * @brief Virtual block devise driver header. + * + * @addtogroup ramdisk + * @{ + */ + +#ifndef RAMDISK_H_ +#define RAMDISK_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +typedef struct RamDisk RamDisk; + +/** + * + */ +#define _ramdisk_device_data \ + _base_block_device_data \ + uint8_t *storage; \ + uint32_t blk_size; \ + uint32_t blk_num; \ + bool readonly; + +/** + * + */ +struct RamDisk { + /** @brief Virtual Methods Table.*/ + const struct BaseBlockDeviceVMT *vmt; + _ramdisk_device_data +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ramdiskObjectInit(RamDisk *rdp); + void ramdiskStart(RamDisk *rdp, uint8_t *storage, uint32_t blksize, + uint32_t blknum, bool readonly); + void ramdiskStop(RamDisk *rdp); +#ifdef __cplusplus +} +#endif + +#endif /* RAMDISK_H_ */ + +/** @} */ diff --git a/os/various/tribuf.h b/os/various/tribuf.h index 4ba3f25..8d8f9f4 100644 --- a/os/various/tribuf.h +++ b/os/various/tribuf.h @@ -22,8 +22,8 @@ * @{
*/
-#ifndef _TRIBUF_H_
-#define _TRIBUF_H_
+#ifndef TRIBUF_H_
+#define TRIBUF_H_
/*===========================================================================*/
/* Driver constants. */
@@ -221,5 +221,5 @@ extern "C" { }
#endif
-#endif /* _TRIBUF_H_ */
+#endif /* TRIBUF_H_ */
/** @} */
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/Makefile b/testhal/MSP430X/EXP430FR5969/ADC/Makefile new file mode 100644 index 0000000..cf81f18 --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/Makefile @@ -0,0 +1,206 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Optimization level, can be [0, 1, 2, 3, s].
+# 0 = turn off optimization. s = optimize for size.
+# (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
+OPTIMIZE = 0
+
+# Debugging format.
+DEBUG =
+#DEBUG = stabs
+
+# Memory/data model
+MODEL = small
+
+# Object files directory
+# To put object files in current directory, use a dot (.), do NOT make
+# this an empty or blank macro!
+OBJDIR = .
+
+# Compiler flag to set the C Standard level.
+# c89 = "ANSI" C
+# gnu89 = c89 plus GCC extensions
+# c99 = ISO C99 standard (not yet fully implemented)
+# gnu99 = c99 plus GCC extensions
+CSTANDARD = -std=gnu11
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O$(OPTIMIZE) -g$(DEBUG)
+ USE_OPT += -funsigned-char -fshort-enums
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# Enable the selected hardware multiplier
+ifeq ($(USE_HWMULT),)
+ USE_HWMULT = f5series
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = yes
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the idle thread stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_IDLE_STACKSIZE),)
+ USE_IDLE_STACKSIZE = 0xC00
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = nil
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = ../../../..
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC/mk/startup_msp430fr5xxx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/EXP430FR5969/board.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/MSP430X/platform.mk
+include $(CHIBIOS)/os/hal/osal/nil/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/nil/nil.mk
+include $(CHIBIOS_CONTRIB)/os/common/ports/MSP430X/compilers/GCC/mk/port.mk
+# Other files (optional).
+
+# Define linker script file here
+LDSCRIPT = $(STARTUPLD)/msp430fr5969.ld
+
+# C sources
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ msp_vectors.c \
+ main.c
+
+# C++ sources
+CPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(CHIBIOS)/os/license \
+ $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = msp430fr5969
+
+TRGT = msp430-elf-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# MSP430-specific options here
+MOPT = -m$(MODEL)
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/chconf.h b/testhal/MSP430X/EXP430FR5969/ADC/chconf.h new file mode 100644 index 0000000..3b7a8e1 --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/chconf.h @@ -0,0 +1,274 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file nilconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef CHCONF_H
+#define CHCONF_H
+
+#define _CHIBIOS_NIL_CONF_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Number of user threads in the application.
+ * @note This number is not inclusive of the idle thread which is
+ * Implicitly handled.
+ */
+#define CH_CFG_NUM_THREADS 1
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name System timer settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 16
+
+/**
+ * @brief System tick frequency.
+ * @note This value together with the @p CH_CFG_ST_RESOLUTION
+ * option defines the maximum amount of time allowed for
+ * timeouts.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note Feature not currently implemented.
+ * @note The default is @p FALSE.
+ */
+#define CH_CFG_USE_MUTEXES FALSE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note Feature not currently implemented.
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief System assertions.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Stack check.
+ *
+ *@note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System initialization hook.
+ */
+#if !defined(CH_CFG_SYSTEM_INIT_HOOK) || defined(__DOXYGEN__)
+#define CH_CFG_SYSTEM_INIT_HOOK() { \
+}
+#endif
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXT_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ */
+#define CH_CFG_THREAD_EXT_INIT_HOOK(tr) { \
+ /* Add custom threads initialization code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief System halt hook.
+ */
+#if !defined(CH_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in nilcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/halconf.h b/testhal/MSP430X/EXP430FR5969/ADC/halconf.h new file mode 100644 index 0000000..2982a63 --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/halconf.h @@ -0,0 +1,388 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef HALCONF_H
+#define HALCONF_H
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the DMA subsystem.
+ */
+#if !defined(HAL_USE_DMA) || defined(__DOXYGEN__)
+#define HAL_USE_DMA TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC TRUE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE FALSE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS FALSE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING FALSE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING FALSE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 16 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 256 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/**
+ * @brief Serial over USB number of buffers.
+ * @note The default is 2 buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_NUMBER 2
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* UART driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
+#define UART_USE_WAIT FALSE
+#endif
+
+/**
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define UART_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/main.c b/testhal/MSP430X/EXP430FR5969/ADC/main.c new file mode 100644 index 0000000..8a530ec --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/main.c @@ -0,0 +1,270 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "string.h"
+#include "stdio.h" /* eesh */
+
+/* Disable watchdog because of lousy startup code in newlib */
+static void __attribute__((naked, section(".crt_0042disable_watchdog"), used))
+disable_watchdog(void) {
+ WDTCTL = WDTPW | WDTHOLD;
+}
+
+const char * start_msg = "\r\n\r\nExecuting ADC test suite...\r\n";
+const char * test_1_msg = "\r\nTEST 1: 1 channel, depth 1, no circular\r\n";
+const char * test_2_msg = "\r\nTEST 2: 1 channel, depth 8, no circular\r\n";
+const char * test_3_msg = "\r\nTEST 3: 4 channels, depth 1, no circular\r\n";
+const char * test_4_msg = "\r\nTEST 4: 4 channels, depth 8, no circular\r\n";
+const char * test_5_msg = "\r\nTEST 5: 1 channel, depth 1, circular\r\n";
+const char * test_6_msg = "\r\nTEST 6: 1 channel, depth 8, circular\r\n";
+const char * test_7_msg = "\r\nTEST 7: 4 channel, depth 1, circular\r\n";
+const char * test_8_msg = "\r\nTEST 8: 4 channel, depth 8, circular\r\n";
+const char * test_9_msg = "\r\nTEST 9: 1 channel, depth 1, synchronous\r\n";
+const char * test_10_msg = "\r\nTEST 9: 1 channel, depth 1, exclusive\r\n";
+
+const char * success_string = "\r\nSUCCESS\r\n";
+const char * fail_string = "\r\nFAILURE\r\n";
+
+char out_string[128];
+const char * raw_fmt_string = "Raw Value: %d\r\n";
+const char * cooked_fmt_string = "Cooked Value: %d\r\n";
+const char * chn_fmt_string = "\r\nCHANNEL %d\r\n";
+
+uint16_t buffer_margin[72];
+uint16_t * buffer = buffer_margin + 4;
+uint8_t depth;
+uint8_t cb_arg = 0;
+uint16_t cb_expect;
+
+static const int test = 0;
+
+ADCConfig config = {
+ 255 /* dma_index */
+};
+
+ADCConversionGroup group = {
+ false, /* circular */
+ 1, /* num_channels */
+ NULL, /* end_cb */
+ NULL, /* error_cb */
+ {
+ 30, 31, 30, 31, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, /* channels */
+ MSP430X_ADC_RES_12BIT, /* res */
+ MSP430X_ADC_SHT_32, /* rate */
+ MSP430X_ADC_VSS_VREF_BUF, /* ref */
+ MSP430X_REF_2V5 /* vref_src */
+};
+
+void print(const char * msg) {
+
+ if (!test) {
+ chnWrite(&SD0, (const uint8_t *)msg, strlen(msg));
+ }
+}
+
+void adc_callback(ADCDriver * adcp, adcsample_t *buffer, size_t n) {
+ (void)adcp;
+ (void)buffer;
+ (void)n;
+
+ cb_arg++;
+
+ if (adcp->grpp->circular && cb_arg == cb_expect) {
+ osalSysLockFromISR();
+ adcStopConversionI(adcp);
+ osalSysUnlockFromISR();
+ }
+}
+
+void run_test(const char * test_msg, uint8_t num_channels, uint8_t depth,
+ bool circular) {
+ print(test_msg);
+
+ cb_arg = 0;
+
+ group.num_channels = num_channels;
+ group.circular = circular;
+ group.end_cb = adc_callback;
+
+ if (depth > 1) cb_expect = 2;
+ else cb_expect = 1;
+ if (circular) cb_expect *= 3;
+
+ adcStartConversion(&ADCD1, &group, buffer, depth);
+
+ while (ADCD1.state == ADC_ACTIVE) ;
+
+
+ int index = 0;
+ for (int j = 0; j < depth; j++) {
+ for (int i = 0; i < group.num_channels; i++) {
+ index = i + (j * group.num_channels);
+ sniprintf(out_string, 128, chn_fmt_string, group.channels[i]);
+ print(out_string);
+
+ sniprintf(out_string, 128, raw_fmt_string, buffer[index]);
+ print(out_string);
+
+ if (group.channels[i] == 30) { /* internal temp sensor */
+ buffer[index] = adcMSP430XAdjustTemp(&group, buffer[index]);
+ }
+ else {
+ buffer[index] = adcMSP430XAdjustResult(&group, buffer[index]);
+ }
+
+ sniprintf(out_string, 128, cooked_fmt_string, buffer[index]);
+ print(out_string);
+ }
+ }
+
+ if (cb_arg == cb_expect) {
+ print(success_string);
+ }
+ else {
+ print(fail_string);
+ }
+}
+
+/*
+ * Thread 2.
+ */
+THD_WORKING_AREA(waThread1, 4096);
+THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+
+ /*
+ * Activate the serial driver 0 using the driver default configuration.
+ */
+ sdStart(&SD0, NULL);
+
+
+ while (chnGetTimeout(&SD0, TIME_INFINITE)) {
+ print(start_msg);
+ chThdSleepMilliseconds(2000);
+
+ /* Activate the ADC driver 1 using its config */
+ adcStart(&ADCD1, &config);
+
+ /* Test 1 - 1ch1d, no circular */
+ run_test(test_1_msg, 1, 1, false);
+
+ /* Test 2 - 1ch8d, no circular */
+ run_test(test_2_msg, 1, 8, false);
+
+ /* Test 3 - 4chd1, no circular */
+ run_test(test_3_msg, 4, 1, false);
+
+ /* Test 4 - 4ch8d, no circular */
+ run_test(test_4_msg, 4, 8, false);
+
+ /* Test 5 - 1ch1d, circular */
+ run_test(test_5_msg, 1, 1, true);
+
+ /* Test 6 - 1ch8d, circular */
+ run_test(test_6_msg, 1, 8, true);
+
+ /* Test 7 - 4ch1d, circular */
+ run_test(test_7_msg, 4, 1, true);
+
+ /* Test 8 - 4ch8d, circular */
+ run_test(test_8_msg, 4, 8, true);
+
+ /* Test 9 - 1ch1d, synchronous */
+ print(test_9_msg);
+ cb_arg = 0;
+
+ group.num_channels = 1;
+ group.circular = false;
+ group.end_cb = adc_callback;
+
+ cb_expect = 1;
+
+ adcConvert(&ADCD1, &group, buffer, 1);
+
+ while (ADCD1.state == ADC_ACTIVE) ;
+
+ sniprintf(out_string, 128, chn_fmt_string, group.channels[0]);
+ print(out_string);
+
+ sniprintf(out_string, 128, raw_fmt_string, buffer[0]);
+ print(out_string);
+
+ buffer[0] = adcMSP430XAdjustTemp(&group, buffer[0]);
+
+ sniprintf(out_string, 128, cooked_fmt_string, buffer[0]);
+ print(out_string);
+
+ if (cb_arg == cb_expect) {
+ print(success_string);
+ }
+ else {
+ print(fail_string);
+ }
+
+ /* Test 10 - 1ch1d, exclusive */
+ adcStop(&ADCD1);
+
+ config.dma_index = 0;
+
+ adcStart(&ADCD1, &config);
+
+ run_test(test_10_msg, 1, 1, false);
+
+ adcStop(&ADCD1);
+
+ config.dma_index = 255;
+ }
+}
+
+/*
+ * Threads static table, one entry per thread. The number of entries must
+ * match NIL_CFG_NUM_THREADS.
+ */
+THD_TABLE_BEGIN
+ THD_TABLE_ENTRY(waThread1, "adc_test", Thread1, NULL)
+THD_TABLE_END
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ WDTCTL = WDTPW | WDTHOLD;
+
+ halInit();
+ chSysInit();
+
+ /* This is now the idle thread loop, you may perform here a low priority
+ task but you must never try to sleep or wait in this loop. Note that
+ this tasks runs at the lowest priority level so any instruction added
+ here will be executed after all other tasks have been started.*/
+ while (true) {
+ }
+}
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/mcuconf.h b/testhal/MSP430X/EXP430FR5969/ADC/mcuconf.h new file mode 100644 index 0000000..70e29ff --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/mcuconf.h @@ -0,0 +1,68 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * MSP430X drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the driver
+ * is enabled in halconf.h.
+ *
+ */
+
+#define MSP430X_MCUCONF
+
+/* HAL driver system settings */
+#define MSP430X_ACLK_SRC MSP430X_VLOCLK
+#define MSP430X_LFXTCLK_FREQ 0
+#define MSP430X_HFXTCLK_FREQ 0
+#define MSP430X_DCOCLK_FREQ 8000000
+#define MSP430X_MCLK_DIV 1
+#define MSP430X_SMCLK_DIV 32
+
+/*
+ * SERIAL driver system settings.
+ */
+#define MSP430X_SERIAL_USE_USART0 TRUE
+#define MSP430X_USART0_CLK_SRC MSP430X_SMCLK_SRC
+#define MSP430X_SERIAL_USE_USART1 FALSE
+#define MSP430X_SERIAL_USE_USART2 FALSE
+#define MSP430X_SERIAL_USE_USART3 FALSE
+
+/*
+ * ST driver system settings.
+ */
+#define MSP430X_ST_CLK_SRC MSP430X_SMCLK_SRC
+#define MSP430X_ST_TIMER_TYPE B
+#define MSP430X_ST_TIMER_INDEX 0
+
+/*
+ * SPI driver system settings.
+ */
+#define MSP430X_SPI_USE_SPIA1 FALSE
+#define MSP430X_SPI_USE_SPIB0 FALSE
+#define MSP430X_SPI_EXCLUSIVE_DMA TRUE
+
+/*
+ * ADC driver system settings
+ */
+#define MSP430X_ADC_EXCLUSIVE_DMA TRUE
+#define MSP430X_ADC1_FREQ 5000000 / 256
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/msp_vectors.c b/testhal/MSP430X/EXP430FR5969/ADC/msp_vectors.c new file mode 100644 index 0000000..d12ed53 --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/msp_vectors.c @@ -0,0 +1,286 @@ +#include <msp430.h>
+
+__attribute__((interrupt(1)))
+void Vector1(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(2)))
+void Vector2(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(3)))
+void Vector3(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(4)))
+void Vector4(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(5)))
+void Vector5(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(6)))
+void Vector6(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(7)))
+void Vector7(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(8)))
+void Vector8(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(9)))
+void Vector9(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(10)))
+void Vector10(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(11)))
+void Vector11(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(12)))
+void Vector12(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(13)))
+void Vector13(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(14)))
+void Vector14(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(15)))
+void Vector15(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(16)))
+void Vector16(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(17)))
+void Vector17(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(18)))
+void Vector18(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(19)))
+void Vector19(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(20)))
+void Vector20(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(21)))
+void Vector21(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(22)))
+void Vector22(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(23)))
+void Vector23(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(24)))
+void Vector24(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(25)))
+void Vector25(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(26)))
+void Vector26(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(27)))
+void Vector27(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(28)))
+void Vector28(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(29)))
+void Vector29(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(30)))
+void Vector30(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(31)))
+void Vector31(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(32)))
+void Vector32(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(35)))
+void Vector35(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(36)))
+void Vector36(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(38)))
+void Vector38(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(39)))
+void Vector39(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(41)))
+void Vector41(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(42)))
+void Vector42(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(44)))
+void Vector44(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(45)))
+void Vector45(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(46)))
+void Vector46(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(48)))
+void Vector48(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(50)))
+void Vector50(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(51)))
+void Vector51(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(53)))
+void Vector53(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(54)))
+void Vector54(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(55)))
+void Vector55(void) {
+
+ while (1) {
+ }
+}
+
+
diff --git a/testhal/MSP430X/EXP430FR5969/DMA/main.c b/testhal/MSP430X/EXP430FR5969/DMA/main.c index 1929af1..757eedc 100644 --- a/testhal/MSP430X/EXP430FR5969/DMA/main.c +++ b/testhal/MSP430X/EXP430FR5969/DMA/main.c @@ -35,6 +35,8 @@ const char * test_6_msg = "TEST 6: Attempt to claim already claimed DMA " "and succeed.\r\n";
const char * test_7_msg = "TEST 7: Claim DMA channel 1, perform a Word-to-word "
"memcpy, and release it\r\n";
+const char * test_8_msg = "TEST 8: Claim all three DMA channels, try to issue dmaRequest, "
+ "fail\r\n";
const char * succeed_string = "SUCCESS\r\n\r\n";
const char * fail_string = "FAILURE\r\n\r\n";
@@ -43,6 +45,8 @@ char instring[256]; char outstring[256];
msp430x_dma_req_t * request;
uint8_t cb_arg = 1;
+bool result;
+int result_i;
void dma_callback_test(void * args) {
@@ -120,6 +124,8 @@ msp430x_dma_req_t test_5_req = { };
msp430x_dma_ch_t ch = { NULL, 0, NULL };
+msp430x_dma_ch_t ch1 = { NULL, 0, NULL };
+msp430x_dma_ch_t ch2 = { NULL, 0, NULL };
/*
* Thread 2.
@@ -146,7 +152,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_1_req;
- dmaRequest(request, TIME_INFINITE);
+ chSysLock();
+ dmaRequestS(request, TIME_INFINITE);
+ chSysUnlock();
if (strcmp("After DMA test \r\n", outstring)) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
@@ -162,7 +170,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_2_req;
- dmaRequest(request, TIME_INFINITE);
+ chSysLock();
+ dmaRequestS(request, TIME_INFINITE);
+ chSysUnlock();
if (strcmp("After DMA test \r\n", outstring)) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
@@ -178,7 +188,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_3_req;
- dmaRequest(request, TIME_INFINITE);
+ chSysLock();
+ dmaRequestS(request, TIME_INFINITE);
+ chSysUnlock();
if (strcmp("AAAAAAAAAAAAAAAA\r\n", outstring)) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
@@ -196,7 +208,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_4_req;
- dmaRequest(request, TIME_INFINITE);
+ chSysLock();
+ dmaRequestS(request, TIME_INFINITE);
+ chSysUnlock();
if (strcmp("After DMA test \r\n", outstring) || cb_arg) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
@@ -213,7 +227,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_5_req;
- dmaAcquire(&ch, 0);
+ chSysLock();
+ dmaAcquireI(&ch, 0);
+ chSysUnlock();
dmaTransfer(&ch, request);
if (strcmp("After DMA test \r\n", outstring)) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
@@ -225,11 +241,17 @@ THD_FUNCTION(Thread1, arg) { /* Test 6 - Attempt to claim DMA channel 0, fail, release it, attempt to
* claim it again */
chnWrite(&SD0, (const uint8_t *)test_6_msg, strlen(test_6_msg));
- if (!dmaAcquire(&ch, 0)) {
+ chSysLock();
+ result = dmaAcquireI(&ch, 0);
+ chSysUnlock();
+ if (!result) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
dmaRelease(&ch);
- if (dmaAcquire(&ch, 0)) {
+ chSysLock();
+ result = dmaAcquireI(&ch, 0);
+ chSysUnlock();
+ if (result) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
else {
@@ -246,7 +268,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_5_req;
- dmaAcquire(&ch, 1);
+ chSysLock();
+ dmaAcquireI(&ch, 1);
+ chSysUnlock();
dmaTransfer(&ch, request);
if (strcmp("After DMA test \r\n", outstring)) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
@@ -255,6 +279,40 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)succeed_string, strlen(succeed_string));
}
dmaRelease(&ch);
+
+ /* Test 8 - Claim all 3 DMA channels, attempt dmaRequest, fail */
+ chnWrite(&SD0, (const uint8_t *)test_8_msg, strlen(test_8_msg));
+ chSysLock();
+ result = dmaAcquireI(&ch, 0);
+ chSysUnlock();
+ if (result) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ chSysLock();
+ result = dmaAcquireI(&ch1, 1);
+ chSysUnlock();
+ if (result) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ chSysLock();
+ result = dmaAcquireI(&ch2, 2);
+ chSysUnlock();
+ if (result) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ chSysLock();
+ result_i = dmaRequestS(request, TIME_IMMEDIATE);
+ chSysUnlock();
+ if (result_i > 0) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ else {
+ chnWrite(&SD0, (const uint8_t *)succeed_string, strlen(succeed_string));
+ }
+ dmaRelease(&ch);
+ dmaRelease(&ch1);
+ dmaRelease(&ch2);
+
}
}
diff --git a/testhal/MSP430X/EXP430FR5969/DMA/msp_vectors.c b/testhal/MSP430X/EXP430FR5969/DMA/msp_vectors.c index 8968fb9..f5ad4b6 100644 --- a/testhal/MSP430X/EXP430FR5969/DMA/msp_vectors.c +++ b/testhal/MSP430X/EXP430FR5969/DMA/msp_vectors.c @@ -192,18 +192,6 @@ void Vector32(void) { while (1) {
}
}
-__attribute__((interrupt(33)))
-void Vector33(void) {
-
- while (1) {
- }
-}
-__attribute__((interrupt(34)))
-void Vector34(void) {
-
- while (1) {
- }
-}
__attribute__((interrupt(35)))
void Vector35(void) {
@@ -216,12 +204,7 @@ void Vector36(void) { while (1) {
}
}
-__attribute__((interrupt(37)))
-void Vector37(void) {
- while (1) {
- }
-}
__attribute__((interrupt(38)))
void Vector38(void) {
@@ -234,12 +217,7 @@ void Vector39(void) { while (1) {
}
}
-__attribute__((interrupt(40)))
-void Vector40(void) {
- while (1) {
- }
-}
__attribute__((interrupt(41)))
void Vector41(void) {
diff --git a/testhal/MSP430X/EXP430FR5969/SPI/main.c b/testhal/MSP430X/EXP430FR5969/SPI/main.c index 17f5c86..8d28198 100644 --- a/testhal/MSP430X/EXP430FR5969/SPI/main.c +++ b/testhal/MSP430X/EXP430FR5969/SPI/main.c @@ -34,11 +34,12 @@ const char * test_5_msg = "TEST 5: spiIgnore\r\n"; const char * test_6_msg = "TEST 6: spiExchange\r\n";
const char * test_7_msg = "TEST 7: spiSend\r\n";
const char * test_8_msg = "TEST 8: spiReceive\r\n";
-const char * test_9_msg = "TEST 9: spiStartExchange with exclusive DMA\r\n";
-const char * test_10_msg =
- "TEST 10: spiStartExchange with exclusive DMA for TX\r\n";
+const char * test_9_msg = "TEST 9: spiPolledExchange\r\n";
+const char * test_10_msg = "TEST 10: spiStartExchange with exclusive DMA\r\n";
const char * test_11_msg =
- "TEST 11: spiStartExchange with exclusive DMA for RX\r\n";
+ "TEST 11: spiStartExchange with exclusive DMA for TX\r\n";
+const char * test_12_msg =
+ "TEST 12: spiStartExchange with exclusive DMA for RX\r\n";
const char * succeed_string = "SUCCESS\r\n\r\n";
const char * fail_string = "FAILURE\r\n\r\n";
@@ -270,6 +271,25 @@ THD_FUNCTION(Thread1, arg) { else {
chnWrite(&SD0, (const uint8_t *)succeed_string, strlen(succeed_string));
}
+
+ /* Test 9 - spiPolledExchange */
+ chnWrite(&SD0, (const uint8_t *)test_9_msg, strlen(test_9_msg));
+ strcpy(outstring, "After SPI test \r\n");
+ strcpy(instring, "Before SPI test \r\n");
+ if (strcmp("Before SPI test \r\n", instring) ||
+ strcmp("After SPI test \r\n", outstring)) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ spiSelect(&SPIDB0);
+ outstring[0] = spiPolledExchange(&SPIDB0, instring[0]);
+ spiUnselect(&SPIDB0);
+ if (strcmp("Bfter SPI test \r\n", outstring) ||
+ strcmp("Before SPI test \r\n", instring)) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ else {
+ chnWrite(&SD0, (const uint8_t *)succeed_string, strlen(succeed_string));
+ }
/* Reconfigure SPIDA1 to use exclusive DMA for both */
spiStop(&SPIDA1);
@@ -278,8 +298,8 @@ THD_FUNCTION(Thread1, arg) { SPIDA1_config.spi_mode = 1; /* because why not get coverage */
spiStart(&SPIDA1, &SPIDA1_config);
- /* Test 9 - spiStartExchange with exclusive DMA */
- chnWrite(&SD0, (const uint8_t *)test_9_msg, strlen(test_9_msg));
+ /* Test 10 - spiStartExchange with exclusive DMA */
+ chnWrite(&SD0, (const uint8_t *)test_10_msg, strlen(test_10_msg));
strcpy(outstring, "After SPI test \r\n");
strcpy(instring, "Before SPI test \r\n");
cb_arg = 1;
@@ -307,8 +327,8 @@ THD_FUNCTION(Thread1, arg) { SPIDA1_config.spi_mode = 2; /* because why not get coverage */
spiStart(&SPIDA1, &SPIDA1_config);
- /* Test 10 - spiStartExchange with exclusive DMA for TX */
- chnWrite(&SD0, (const uint8_t *)test_10_msg, strlen(test_10_msg));
+ /* Test 11 - spiStartExchange with exclusive DMA for TX */
+ chnWrite(&SD0, (const uint8_t *)test_11_msg, strlen(test_11_msg));
strcpy(outstring, "After SPI test \r\n");
strcpy(instring, "Before SPI test \r\n");
cb_arg = 1;
@@ -336,8 +356,8 @@ THD_FUNCTION(Thread1, arg) { SPIDA1_config.spi_mode = 3; /* because why not get coverage */
spiStart(&SPIDA1, &SPIDA1_config);
- /* Test 11 - spiStartExchange with exclusive DMA for RX */
- chnWrite(&SD0, (const uint8_t *)test_11_msg, strlen(test_11_msg));
+ /* Test 12 - spiStartExchange with exclusive DMA for RX */
+ chnWrite(&SD0, (const uint8_t *)test_12_msg, strlen(test_12_msg));
strcpy(outstring, "After SPI test \r\n");
strcpy(instring, "Before SPI test \r\n");
cb_arg = 1;
diff --git a/testhal/MSP430X/EXP430FR5969/SPI/msp_vectors.c b/testhal/MSP430X/EXP430FR5969/SPI/msp_vectors.c index 8968fb9..c23cbc8 100644 --- a/testhal/MSP430X/EXP430FR5969/SPI/msp_vectors.c +++ b/testhal/MSP430X/EXP430FR5969/SPI/msp_vectors.c @@ -192,18 +192,6 @@ void Vector32(void) { while (1) {
}
}
-__attribute__((interrupt(33)))
-void Vector33(void) {
-
- while (1) {
- }
-}
-__attribute__((interrupt(34)))
-void Vector34(void) {
-
- while (1) {
- }
-}
__attribute__((interrupt(35)))
void Vector35(void) {
@@ -216,12 +204,6 @@ void Vector36(void) { while (1) {
}
}
-__attribute__((interrupt(37)))
-void Vector37(void) {
-
- while (1) {
- }
-}
__attribute__((interrupt(38)))
void Vector38(void) {
@@ -234,12 +216,6 @@ void Vector39(void) { while (1) {
}
}
-__attribute__((interrupt(40)))
-void Vector40(void) {
-
- while (1) {
- }
-}
__attribute__((interrupt(41)))
void Vector41(void) {
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/Makefile b/testhal/MSP430X/EXP430FR6989/ADC/Makefile new file mode 100644 index 0000000..b86021e --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/Makefile @@ -0,0 +1,206 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Optimization level, can be [0, 1, 2, 3, s].
+# 0 = turn off optimization. s = optimize for size.
+# (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
+OPTIMIZE = 0
+
+# Debugging format.
+DEBUG =
+#DEBUG = stabs
+
+# Memory/data model
+MODEL = small
+
+# Object files directory
+# To put object files in current directory, use a dot (.), do NOT make
+# this an empty or blank macro!
+OBJDIR = .
+
+# Compiler flag to set the C Standard level.
+# c89 = "ANSI" C
+# gnu89 = c89 plus GCC extensions
+# c99 = ISO C99 standard (not yet fully implemented)
+# gnu99 = c99 plus GCC extensions
+CSTANDARD = -std=gnu11
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O$(OPTIMIZE) -g$(DEBUG)
+ USE_OPT += -funsigned-char -fshort-enums
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# Enable the selected hardware multiplier
+ifeq ($(USE_HWMULT),)
+ USE_HWMULT = f5series
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = yes
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the idle thread stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_IDLE_STACKSIZE),)
+ USE_IDLE_STACKSIZE = 0xC00
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = nil
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = ../../../..
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC/mk/startup_msp430fr5xxx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/EXP430FR6989/board.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/MSP430X/platform.mk
+include $(CHIBIOS)/os/hal/osal/nil/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/nil/nil.mk
+include $(CHIBIOS_CONTRIB)/os/common/ports/MSP430X/compilers/GCC/mk/port.mk
+# Other files (optional).
+
+# Define linker script file here
+LDSCRIPT = $(STARTUPLD)/msp430fr6989.ld
+
+# C sources
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ msp_vectors.c \
+ main.c
+
+# C++ sources
+CPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(CHIBIOS)/os/license \
+ $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = msp430fr6989
+
+TRGT = msp430-elf-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# MSP430-specific options here
+MOPT = -m$(MODEL)
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/chconf.h b/testhal/MSP430X/EXP430FR6989/ADC/chconf.h new file mode 100644 index 0000000..3b7a8e1 --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/chconf.h @@ -0,0 +1,274 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file nilconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef CHCONF_H
+#define CHCONF_H
+
+#define _CHIBIOS_NIL_CONF_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Number of user threads in the application.
+ * @note This number is not inclusive of the idle thread which is
+ * Implicitly handled.
+ */
+#define CH_CFG_NUM_THREADS 1
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name System timer settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 16
+
+/**
+ * @brief System tick frequency.
+ * @note This value together with the @p CH_CFG_ST_RESOLUTION
+ * option defines the maximum amount of time allowed for
+ * timeouts.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note Feature not currently implemented.
+ * @note The default is @p FALSE.
+ */
+#define CH_CFG_USE_MUTEXES FALSE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note Feature not currently implemented.
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief System assertions.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Stack check.
+ *
+ *@note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System initialization hook.
+ */
+#if !defined(CH_CFG_SYSTEM_INIT_HOOK) || defined(__DOXYGEN__)
+#define CH_CFG_SYSTEM_INIT_HOOK() { \
+}
+#endif
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXT_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ */
+#define CH_CFG_THREAD_EXT_INIT_HOOK(tr) { \
+ /* Add custom threads initialization code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief System halt hook.
+ */
+#if !defined(CH_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in nilcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/halconf.h b/testhal/MSP430X/EXP430FR6989/ADC/halconf.h new file mode 100644 index 0000000..2982a63 --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/halconf.h @@ -0,0 +1,388 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef HALCONF_H
+#define HALCONF_H
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the DMA subsystem.
+ */
+#if !defined(HAL_USE_DMA) || defined(__DOXYGEN__)
+#define HAL_USE_DMA TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC TRUE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE FALSE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS FALSE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING FALSE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING FALSE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 16 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 256 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/**
+ * @brief Serial over USB number of buffers.
+ * @note The default is 2 buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_NUMBER 2
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* UART driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
+#define UART_USE_WAIT FALSE
+#endif
+
+/**
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define UART_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/main.c b/testhal/MSP430X/EXP430FR6989/ADC/main.c new file mode 100644 index 0000000..06f9a9c --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/main.c @@ -0,0 +1,254 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "string.h"
+#include "stdio.h" /* eesh */
+
+/* Disable watchdog because of lousy startup code in newlib */
+static void __attribute__((naked, section(".crt_0042disable_watchdog"), used))
+disable_watchdog(void) {
+ WDTCTL = WDTPW | WDTHOLD;
+}
+
+const char * start_msg = "\r\n\r\nExecuting ADC test suite...\r\n";
+const char * test_1_msg = "\r\nTEST 1: 1 channel, depth 1, no circular\r\n";
+const char * test_2_msg = "\r\nTEST 2: 1 channel, depth 8, no circular\r\n";
+const char * test_3_msg = "\r\nTEST 3: 4 channels, depth 1, no circular\r\n";
+const char * test_4_msg = "\r\nTEST 4: 4 channels, depth 8, no circular\r\n";
+const char * test_5_msg = "\r\nTEST 5: 1 channel, depth 1, circular\r\n";
+const char * test_6_msg = "\r\nTEST 6: 1 channel, depth 8, circular\r\n";
+const char * test_7_msg = "\r\nTEST 7: 4 channel, depth 1, circular\r\n";
+const char * test_8_msg = "\r\nTEST 8: 4 channel, depth 8, circular\r\n";
+const char * test_9_msg = "\r\nTEST 9: 1 channel, depth 1, synchronous\r\n";
+
+const char * success_string = "\r\nSUCCESS\r\n";
+const char * fail_string = "\r\nFAILURE\r\n";
+
+char out_string[128];
+const char * raw_fmt_string = "Raw Value: %d\r\n";
+const char * cooked_fmt_string = "Cooked Value: %d\r\n";
+const char * chn_fmt_string = "\r\nCHANNEL %d\r\n";
+
+uint16_t buffer_margin[72];
+uint16_t * buffer = buffer_margin + 4;
+uint8_t depth;
+uint8_t cb_arg = 0;
+uint16_t cb_expect;
+
+static const int test = 0;
+
+ADCConfig config = {
+};
+
+ADCConversionGroup group = {
+ false, /* circular */
+ 1, /* num_channels */
+ NULL, /* end_cb */
+ NULL, /* error_cb */
+ {
+ 30, 31, 30, 31, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, /* channels */
+ MSP430X_ADC_RES_12BIT, /* res */
+ MSP430X_ADC_SHT_32, /* rate */
+ MSP430X_ADC_VSS_VREF_BUF, /* ref */
+ MSP430X_REF_2V5 /* vref_src */
+};
+
+void print(const char * msg) {
+
+ if (!test) {
+ chnWrite(&SD1, (const uint8_t *)msg, strlen(msg));
+ }
+}
+
+void adc_callback(ADCDriver * adcp, adcsample_t *buffer, size_t n) {
+ (void)adcp;
+ (void)buffer;
+ (void)n;
+
+ cb_arg++;
+
+ if (adcp->grpp->circular && cb_arg == cb_expect) {
+ osalSysLockFromISR();
+ adcStopConversionI(adcp);
+ osalSysUnlockFromISR();
+ }
+}
+
+void run_test(const char * test_msg, uint8_t num_channels, uint8_t depth,
+ bool circular) {
+ print(test_msg);
+
+ cb_arg = 0;
+
+ group.num_channels = num_channels;
+ group.circular = circular;
+ group.end_cb = adc_callback;
+
+ if (depth > 1) cb_expect = 2;
+ else cb_expect = 1;
+ if (circular) cb_expect *= 3;
+
+ adcStartConversion(&ADCD1, &group, buffer, depth);
+
+ while (ADCD1.state == ADC_ACTIVE) ;
+
+
+ int index = 0;
+ for (int j = 0; j < depth; j++) {
+ for (int i = 0; i < group.num_channels; i++) {
+ index = i + (j * group.num_channels);
+ sniprintf(out_string, 128, chn_fmt_string, group.channels[i]);
+ print(out_string);
+
+ sniprintf(out_string, 128, raw_fmt_string, buffer[index]);
+ print(out_string);
+
+ if (group.channels[i] == 30) { /* internal temp sensor */
+ buffer[index] = adcMSP430XAdjustTemp(&group, buffer[index]);
+ }
+ else {
+ buffer[index] = adcMSP430XAdjustResult(&group, buffer[index]);
+ }
+
+ sniprintf(out_string, 128, cooked_fmt_string, buffer[index]);
+ print(out_string);
+ }
+ }
+
+ if (cb_arg == cb_expect) {
+ print(success_string);
+ }
+ else {
+ print(fail_string);
+ }
+}
+
+/*
+ * Thread 2.
+ */
+THD_WORKING_AREA(waThread1, 4096);
+THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+
+ /*
+ * Activate the serial driver 0 using the driver default configuration.
+ */
+ sdStart(&SD1, NULL);
+
+ /* Activate the ADC driver 1 using its config */
+ adcStart(&ADCD1, &config);
+
+ while (chnGetTimeout(&SD1, TIME_INFINITE)) {
+ print(start_msg);
+ chThdSleepMilliseconds(2000);
+
+ /* Test 1 - 1ch1d, no circular */
+ run_test(test_1_msg, 1, 1, false);
+
+ /* Test 2 - 1ch8d, no circular */
+ run_test(test_2_msg, 1, 8, false);
+
+ /* Test 3 - 4chd1, no circular */
+ run_test(test_3_msg, 4, 1, false);
+
+ /* Test 4 - 4ch8d, no circular */
+ run_test(test_4_msg, 4, 8, false);
+
+ /* Test 5 - 1ch1d, circular */
+ run_test(test_5_msg, 1, 1, true);
+
+ /* Test 6 - 1ch8d, circular */
+ run_test(test_6_msg, 1, 8, true);
+
+ /* Test 7 - 4ch1d, circular */
+ run_test(test_7_msg, 4, 1, true);
+
+ /* Test 8 - 4ch8d, circular */
+ run_test(test_8_msg, 4, 8, true);
+
+ /* Test 9 - 1ch1d, synchronous */
+ print(test_9_msg);
+ cb_arg = 0;
+
+ group.num_channels = 1;
+ group.circular = false;
+ group.end_cb = adc_callback;
+
+ cb_expect = 1;
+
+ adcConvert(&ADCD1, &group, buffer, 1);
+
+ while (ADCD1.state == ADC_ACTIVE) ;
+
+ sniprintf(out_string, 128, chn_fmt_string, group.channels[0]);
+ print(out_string);
+
+ sniprintf(out_string, 128, raw_fmt_string, buffer[0]);
+ print(out_string);
+
+ buffer[0] = adcMSP430XAdjustTemp(&group, buffer[0]);
+
+ sniprintf(out_string, 128, cooked_fmt_string, buffer[0]);
+ print(out_string);
+
+ if (cb_arg == cb_expect) {
+ print(success_string);
+ }
+ else {
+ print(fail_string);
+ }
+ }
+}
+
+/*
+ * Threads static table, one entry per thread. The number of entries must
+ * match NIL_CFG_NUM_THREADS.
+ */
+THD_TABLE_BEGIN
+ THD_TABLE_ENTRY(waThread1, "adc_test", Thread1, NULL)
+THD_TABLE_END
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ WDTCTL = WDTPW | WDTHOLD;
+
+ halInit();
+ chSysInit();
+
+ /* This is now the idle thread loop, you may perform here a low priority
+ task but you must never try to sleep or wait in this loop. Note that
+ this tasks runs at the lowest priority level so any instruction added
+ here will be executed after all other tasks have been started.*/
+ while (true) {
+ }
+}
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/mcuconf.h b/testhal/MSP430X/EXP430FR6989/ADC/mcuconf.h new file mode 100644 index 0000000..bcb0c69 --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/mcuconf.h @@ -0,0 +1,68 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * MSP430X drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the driver
+ * is enabled in halconf.h.
+ *
+ */
+
+#define MSP430X_MCUCONF
+
+/* HAL driver system settings */
+#define MSP430X_ACLK_SRC MSP430X_VLOCLK
+#define MSP430X_LFXTCLK_FREQ 0
+#define MSP430X_HFXTCLK_FREQ 0
+#define MSP430X_DCOCLK_FREQ 8000000
+#define MSP430X_MCLK_DIV 1
+#define MSP430X_SMCLK_DIV 32
+
+/*
+ * SERIAL driver system settings.
+ */
+#define MSP430X_SERIAL_USE_USART1 TRUE
+#define MSP430X_USART1_CLK_SRC MSP430X_SMCLK_SRC
+#define MSP430X_SERIAL_USE_USART0 FALSE
+#define MSP430X_SERIAL_USE_USART2 FALSE
+#define MSP430X_SERIAL_USE_USART3 FALSE
+
+/*
+ * ST driver system settings.
+ */
+#define MSP430X_ST_CLK_SRC MSP430X_SMCLK_SRC
+#define MSP430X_ST_TIMER_TYPE B
+#define MSP430X_ST_TIMER_INDEX 0
+
+/*
+ * SPI driver system settings.
+ */
+#define MSP430X_SPI_USE_SPIA1 FALSE
+#define MSP430X_SPI_USE_SPIB0 FALSE
+#define MSP430X_SPI_EXCLUSIVE_DMA FALSE
+
+/*
+ * ADC driver system settings
+ */
+#define MSP430X_ADC_EXCLUSIVE_DMA FALSE
+#define MSP430X_ADC1_FREQ 5000000 / 256
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/msp_vectors.c b/testhal/MSP430X/EXP430FR6989/ADC/msp_vectors.c new file mode 100644 index 0000000..24e2a11 --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/msp_vectors.c @@ -0,0 +1,286 @@ +#include <msp430.h>
+
+__attribute__((interrupt(1)))
+void Vector1(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(2)))
+void Vector2(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(3)))
+void Vector3(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(4)))
+void Vector4(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(5)))
+void Vector5(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(6)))
+void Vector6(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(7)))
+void Vector7(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(8)))
+void Vector8(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(9)))
+void Vector9(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(10)))
+void Vector10(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(11)))
+void Vector11(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(12)))
+void Vector12(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(13)))
+void Vector13(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(14)))
+void Vector14(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(15)))
+void Vector15(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(16)))
+void Vector16(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(17)))
+void Vector17(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(18)))
+void Vector18(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(19)))
+void Vector19(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(20)))
+void Vector20(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(21)))
+void Vector21(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(22)))
+void Vector22(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(23)))
+void Vector23(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(24)))
+void Vector24(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(25)))
+void Vector25(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(26)))
+void Vector26(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(27)))
+void Vector27(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(28)))
+void Vector28(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(29)))
+void Vector29(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(30)))
+void Vector30(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(33)))
+void Vector33(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(34)))
+void Vector34(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(36)))
+void Vector36(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(37)))
+void Vector37(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(39)))
+void Vector39(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(40)))
+void Vector40(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(42)))
+void Vector42(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(44)))
+void Vector44(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(45)))
+void Vector45(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(47)))
+void Vector47(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(48)))
+void Vector48(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(49)))
+void Vector49(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(50)))
+void Vector50(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(51)))
+void Vector51(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(53)))
+void Vector53(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(54)))
+void Vector54(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(55)))
+void Vector55(void) {
+
+ while (1) {
+ }
+}
+
+
diff --git a/testhal/STM32/STM32F0xx/onewire/.project b/testhal/STM32/STM32F0xx/onewire/.project index 6599a83..8776e6e 100644 --- a/testhal/STM32/STM32F0xx/onewire/.project +++ b/testhal/STM32/STM32F0xx/onewire/.project @@ -25,6 +25,11 @@ </natures>
<linkedResources>
<link>
+ <name>hw_abstracted</name>
+ <type>2</type>
+ <locationURI>PARENT-3-PROJECT_LOC/hw_abstracted</locationURI>
+ </link>
+ <link>
<name>os-community</name>
<type>2</type>
<locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
diff --git a/testhal/STM32/STM32F0xx/onewire/Makefile b/testhal/STM32/STM32F0xx/onewire/Makefile index d121cee..e478e3a 100644 --- a/testhal/STM32/STM32F0xx/onewire/Makefile +++ b/testhal/STM32/STM32F0xx/onewire/Makefile @@ -77,6 +77,7 @@ PROJECT = ch # Imported source files and paths
CHIBIOS = ../../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+TESTHAL = $(CHIBIOS_CONTRIB)/testhal/common/onewire
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk
# HAL-OSAL files (optional).
@@ -102,7 +103,7 @@ CSRC = $(STARTUPSRC) \ $(BOARDSRC) \
$(TESTSRC) \
main.c \
- onewire_test.c
+ $(TESTHAL)/testhal_onewire.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -135,7 +136,8 @@ ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) INCDIR = $(CHIBIOS)/os/license \
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
- $(CHIBIOS)/os/various
+ $(CHIBIOS)/os/various \
+ $(TESTHAL)
#
# Project, sources and paths
diff --git a/testhal/STM32/STM32F4xx/onewire/onewire_test.h b/testhal/STM32/STM32F0xx/onewire/boarddef.h index 1bec2d0..fd9842b 100644 --- a/testhal/STM32/STM32F4xx/onewire/onewire_test.h +++ b/testhal/STM32/STM32F0xx/onewire/boarddef.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS/RT - Copyright (C) 2016 Uladzimir Pylinsky aka barthess Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,15 +14,15 @@ limitations under the License. */ -#ifndef ONEWIRE_TEST_H_ -#define ONEWIRE_TEST_H_ +#ifndef BOARDDEF_H_ +#define BOARDDEF_H_ -#ifdef __cplusplus -extern "C" { -#endif - void onewireTest(void); -#ifdef __cplusplus -} -#endif +#define ONEWIRE_PORT GPIOB +#define ONEWIRE_PIN GPIOB_PIN0 +#define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN) +#define search_led_off() (palClearPad(GPIOC, GPIOC_LED4)) +#define search_led_on() (palSetPad(GPIOC, GPIOC_LED4)) +#define ONEWIRE_MASTER_CHANNEL 2 +#define ONEWIRE_SAMPLE_CHANNEL 3 -#endif /* ONEWIRE_TEST_H_ */ +#endif /* BOARDDEF_H_ */ diff --git a/testhal/STM32/STM32F0xx/onewire/main.c b/testhal/STM32/STM32F0xx/onewire/main.c index 793bffe..5265edc 100644 --- a/testhal/STM32/STM32F0xx/onewire/main.c +++ b/testhal/STM32/STM32F0xx/onewire/main.c @@ -17,7 +17,7 @@ #include "ch.h"
#include "hal.h"
-#include "onewire_test.h"
+#include "testhal_onewire.h"
/*
* Application entry point.
diff --git a/testhal/STM32/STM32F0xx/onewire/search_rom_synth.c b/testhal/STM32/STM32F0xx/onewire/search_rom_synth.c deleted file mode 100644 index cd2528f..0000000 --- a/testhal/STM32/STM32F0xx/onewire/search_rom_synth.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include <stdlib.h> - -/* - ****************************************************************************** - * DEFINES - ****************************************************************************** - */ - -/* do not set it more than 64 because of some fill_pattern functions - * will be broken.*/ -#define SYNTH_DEVICES_MAX 64 - -/* - * synthetic device - */ -typedef struct { - bool active; - uint64_t id; -} OWSynthDevice; - -/* - * synthetic bus - */ -typedef struct { - OWSynthDevice devices[SYNTH_DEVICES_MAX]; - size_t dev_present; - bool complement_bit; - ioline_t rom_bit; -} OWSynthBus; - -/* - ****************************************************************************** - * EXTERNS - ****************************************************************************** - */ - -/* - ****************************************************************************** - * PROTOTYPES - ****************************************************************************** - */ - -/* - ****************************************************************************** - * GLOBAL VARIABLES - ****************************************************************************** - */ - -static OWSynthBus synth_bus; - -/* - * local buffer for discovered ROMs - */ -static uint64_t detected_devices[SYNTH_DEVICES_MAX]; - -/* - ****************************************************************************** - ****************************************************************************** - * LOCAL FUNCTIONS - ****************************************************************************** - ****************************************************************************** - */ - -/* - ****************************************************************************** - * EXPORTED FUNCTIONS - ****************************************************************************** - */ - -/** - * - */ -void _synth_ow_write_bit(onewireDriver *owp, ioline_t bit) { - (void)owp; - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) { - if (((synth_bus.devices[i].id >> synth_bus.rom_bit) & 1U) != bit) { - synth_bus.devices[i].active = false; - } - } - synth_bus.rom_bit++; -} - -/** - * - */ -ioline_t _synth_ow_read_bit(void) { - ioline_t ret = 0xFF; - size_t i; - ioline_t bit; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) { - if (synth_bus.devices[i].active){ - bit = (synth_bus.devices[i].id >> synth_bus.rom_bit) & 1U; - if (synth_bus.complement_bit){ - bit ^= 1U; - } - if (0xFF == ret) - ret = bit; - else - ret &= bit; - } - } - synth_bus.complement_bit = !synth_bus.complement_bit; - return ret; -} - -/** - * - */ -static void synth_reset_pulse(void){ - size_t i; - - for (i=0; i<synth_bus.dev_present; i++){ - synth_bus.devices[i].active = true; - } -} - -/** - * - */ -static size_t synth_search_rom(onewireDriver *owp, uint8_t *result, size_t max_rom_cnt) { - - size_t i; - - search_clean_start(&owp->search_rom); - - do { - /* initialize buffer to store result */ - if (owp->search_rom.reg.devices_found >= max_rom_cnt) - owp->search_rom.retbuf = result + 8*(max_rom_cnt-1); - else - owp->search_rom.retbuf = result + 8*owp->search_rom.reg.devices_found; - memset(owp->search_rom.retbuf, 0, 8); - - /* clean iteration state */ - search_clean_iteration(&owp->search_rom); - - /**/ - synth_reset_pulse(); - synth_bus.rom_bit = 0; - synth_bus.complement_bit = false; - for (i=0; i<64*3 - 1; i++){ - ow_search_rom_cb(NULL, owp); - } - - if (ONEWIRE_SEARCH_ROM_ERROR != owp->search_rom.reg.result) { - /* store cached result for usage in next iteration */ - memcpy(owp->search_rom.prev_path, owp->search_rom.retbuf, 8); - } - } - while (ONEWIRE_SEARCH_ROM_SUCCESS == owp->search_rom.reg.result); - - /**/ - if (ONEWIRE_SEARCH_ROM_ERROR == owp->search_rom.reg.result) - return 0; - else - return owp->search_rom.reg.devices_found; -} - -/** - * - */ -static void fill_pattern_real_devices(void) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - synth_bus.devices[0].active = true; - synth_bus.devices[0].id = 0x1d00000567f5ec28; - - synth_bus.devices[1].active = true; - synth_bus.devices[1].id = 0x37000005601abd28; - - synth_bus.devices[2].active = true; - synth_bus.devices[2].id = 0x0f000005677d8328; -} - -/** - * - */ -static void fill_pattern_00(size_t devices, size_t start) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = (start + i); - } -} - -/** - * - */ -static void fill_pattern_01(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = (devices - i); - } -} - -/** - * - */ -static void fill_pattern_02(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = ((uint64_t)1 << i); - } -} - -/** - * - */ -static void fill_pattern_03(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = ((uint64_t)0x8000000000000000 >> i); - } -} - -/** - * @brief random pattern helper - */ -static bool is_id_uniq(const OWSynthDevice *dev, size_t n, uint64_t id) { - size_t i; - - for (i=0; i<n; i++) { - if (dev[i].id == id) - return false; - } - return true; -} - -/** - * - */ -static void fill_pattern_rand(size_t devices) { - size_t i; - uint64_t new_id; - - for (i=0; i<SYNTH_DEVICES_MAX; i++){ - synth_bus.devices[i].active = false; - synth_bus.devices[i].id = 0; - } - - for (i=0; i<devices; i++) { - do { - new_id = rand(); - new_id = (new_id << 32) | rand(); - } while (true != is_id_uniq(synth_bus.devices, i, new_id)); - - synth_bus.devices[i].id = new_id; - synth_bus.devices[i].active = true; - } -} - -/** - * - */ -static bool check_result(size_t detected) { - - size_t i,j; - bool match = false; - - for (i=0; i<detected; i++){ - match = false; - for (j=0; j<detected; j++){ - if (synth_bus.devices[i].id == detected_devices[j]){ - match = true; - break; - } - } - if (false == match) - return OSAL_FAILED; - } - return OSAL_SUCCESS; -} - -/** - * - */ -void synthSearchRomTest(onewireDriver *owp) { - - size_t detected = 0; - size_t i; - - synth_bus.dev_present = 3; - fill_pattern_real_devices(); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - for (i=1; i<=SYNTH_DEVICES_MAX; i++){ - synth_bus.dev_present = i; - - fill_pattern_00(synth_bus.dev_present, 0); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_00(synth_bus.dev_present, 1); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_01(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_02(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_03(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - } - - i = 0; - while (i < 1000) { - synth_bus.dev_present = 1 + (rand() & 63); - - fill_pattern_rand(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - i++; - } -} - - diff --git a/testhal/STM32/STM32F1xx/onewire/.cproject b/testhal/STM32/STM32F1xx/onewire/.cproject index 11b29ed..78e793f 100644 --- a/testhal/STM32/STM32F1xx/onewire/.cproject +++ b/testhal/STM32/STM32F1xx/onewire/.cproject @@ -52,4 +52,5 @@ </scannerConfigBuildInfo> </storageModule> <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="refreshScope"/> </cproject> diff --git a/testhal/STM32/STM32F1xx/onewire/.project b/testhal/STM32/STM32F1xx/onewire/.project index 9c1fc51..062afeb 100644 --- a/testhal/STM32/STM32F1xx/onewire/.project +++ b/testhal/STM32/STM32F1xx/onewire/.project @@ -1,6 +1,6 @@ <?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
- <name>STM32F1xx-onewire</name>
+ <name>STM32F1xx-1-Wire</name>
<comment></comment>
<projects>
</projects>
@@ -80,12 +80,18 @@ <link>
<name>os-community</name>
<type>2</type>
- <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
+ <locationURI>CHIBIOS_CONTRIB/os</locationURI>
</link>
<link>
<name>os-git</name>
<type>2</type>
- <locationURI>PARENT-5-PROJECT_LOC/ChibiOS-RT/os</locationURI>
+ <locationURI>copy_PARENT/ChibiOS-RT/os</locationURI>
</link>
</linkedResources>
+ <variableList>
+ <variable>
+ <name>copy_PARENT</name>
+ <value>$%7BPARENT-1-CHIBIOS%7D</value>
+ </variable>
+ </variableList>
</projectDescription>
diff --git a/testhal/STM32/STM32F1xx/onewire/Makefile b/testhal/STM32/STM32F1xx/onewire/Makefile index d2e25b1..e9d4238 100644 --- a/testhal/STM32/STM32F1xx/onewire/Makefile +++ b/testhal/STM32/STM32F1xx/onewire/Makefile @@ -82,6 +82,7 @@ PROJECT = ch # Imported source files and paths
CHIBIOS = ../../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+TESTHAL = $(CHIBIOS_CONTRIB)/testhal/common/onewire
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk
# HAL-OSAL files (optional).
@@ -109,7 +110,7 @@ CSRC = $(STARTUPSRC) \ $(BOARDSRC) \
$(TESTSRC) \
main.c \
- onewire_test.c
+ $(TESTHAL)/testhal_onewire.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -142,7 +143,8 @@ ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) INCDIR = $(CHIBIOS)/os/license \
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
- $(CHIBIOS)/os/various
+ $(CHIBIOS)/os/various \
+ $(TESTHAL)
#
# Project, sources and paths
diff --git a/testhal/STM32/STM32F1xx/onewire/boarddef.h b/testhal/STM32/STM32F1xx/onewire/boarddef.h new file mode 100644 index 0000000..2b1b466 --- /dev/null +++ b/testhal/STM32/STM32F1xx/onewire/boarddef.h @@ -0,0 +1,29 @@ +/* + ChibiOS/RT - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef BOARDDEF_H_ +#define BOARDDEF_H_ + +#define ONEWIRE_PORT GPIOB +#define ONEWIRE_PIN 0 +#define ONEWIRE_PAD_MODE_IDLE PAL_MODE_INPUT +#define ONEWIRE_PAD_MODE_ACTIVE PAL_MODE_STM32_ALTERNATE_OPENDRAIN +#define search_led_on() (palClearPad(GPIOC, GPIOC_LED)) +#define search_led_off() (palSetPad(GPIOC, GPIOC_LED)) +#define ONEWIRE_MASTER_CHANNEL 2 +#define ONEWIRE_SAMPLE_CHANNEL 3 + +#endif /* BOARDDEF_H_ */ diff --git a/testhal/STM32/STM32F1xx/onewire/main.c b/testhal/STM32/STM32F1xx/onewire/main.c index 793bffe..5265edc 100644 --- a/testhal/STM32/STM32F1xx/onewire/main.c +++ b/testhal/STM32/STM32F1xx/onewire/main.c @@ -17,7 +17,7 @@ #include "ch.h"
#include "hal.h"
-#include "onewire_test.h"
+#include "testhal_onewire.h"
/*
* Application entry point.
diff --git a/testhal/STM32/STM32F1xx/onewire/onewire_test.c b/testhal/STM32/STM32F1xx/onewire/onewire_test.c deleted file mode 100644 index be20dbc..0000000 --- a/testhal/STM32/STM32F1xx/onewire/onewire_test.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include <string.h> - -#include "hal.h" - -/* - ****************************************************************************** - * DEFINES - ****************************************************************************** - */ - -#if defined(BOARD_ST_STM32F4_DISCOVERY) || \ - defined(BOARD_ST_STM32F0_DISCOVERY) || \ - defined(BOARD_ST_STM32F0308_DISCOVERY) - #if ONEWIRE_USE_STRONG_PULLUP - #error "This board has not enough voltage for this feature" - #endif -#endif - -#if defined(BOARD_ST_STM32F0308_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOC, GPIOC_LED4)) - #define search_led_on() (palSetPad(GPIOC, GPIOC_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_ST_STM32F4_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOD, GPIOD_LED4)) - #define search_led_on() (palSetPad(GPIOD, GPIOD_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_OLIMEX_STM32_103STK) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN 0 - #define ONEWIRE_PAD_MODE_IDLE PAL_MODE_INPUT - #define ONEWIRE_PAD_MODE_ACTIVE PAL_MODE_STM32_ALTERNATE_OPENDRAIN - #define search_led_on() (palClearPad(GPIOC, GPIOC_LED)) - #define search_led_off() (palSetPad(GPIOC, GPIOC_LED)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#else - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_TACHOMETER - #include "pads.h" - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_on red_led_on - #define search_led_off red_led_off - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#endif - -/* - ****************************************************************************** - * EXTERNS - ****************************************************************************** - */ - -/* - ****************************************************************************** - * PROTOTYPES - ****************************************************************************** - */ -/* - * Forward declarations - */ -#if ONEWIRE_USE_STRONG_PULLUP -static void strong_pullup_assert(void); -static void strong_pullup_release(void); -#endif - -/* - ****************************************************************************** - * GLOBAL VARIABLES - ****************************************************************************** - */ - -static uint8_t testbuf[12]; - -/* stores 3 temperature values in millicelsius */ -static int32_t temperature[3]; - -/* - * Config for underlied PWM driver. - * Note! It is NOT constant because 1-wire driver needs to change them - * during functioning. - */ -static PWMConfig pwm_cfg = { - 0, - 0, - NULL, - { - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL} - }, - 0, -#if STM32_PWM_USE_ADVANCED - 0, -#endif - 0 -}; - -/* - * - */ -static const onewireConfig ow_cfg = { - &PWMD3, - &pwm_cfg, - PWM_OUTPUT_ACTIVE_LOW, - ONEWIRE_MASTER_CHANNEL, - ONEWIRE_SAMPLE_CHANNEL, - ONEWIRE_PORT, - ONEWIRE_PIN, -#if defined(STM32F1XX) - ONEWIRE_PAD_MODE_IDLE, -#endif - ONEWIRE_PAD_MODE_ACTIVE, -#if ONEWIRE_USE_STRONG_PULLUP - strong_pullup_assert, - strong_pullup_release -#endif -}; - -/* - ****************************************************************************** - ****************************************************************************** - * LOCAL FUNCTIONS - ****************************************************************************** - ****************************************************************************** - */ - -#if ONEWIRE_USE_STRONG_PULLUP -/** - * - */ -static void strong_pullup_assert(void) { - palSetPadMode(ONEWIRE_PORT, ONEWIRE_PIN, PAL_MODE_STM32_ALTERNATE_PUSHPULL); -} - -/** - * - */ -static void strong_pullup_release(void) { - palSetPadMode(ONEWIRE_PORT, ONEWIRE_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); -} -#endif /* ONEWIRE_USE_STRONG_PULLUP */ - -/* - ****************************************************************************** - * EXPORTED FUNCTIONS - ****************************************************************************** - */ - -/** - * - */ -void onewireTest(void) { - - int16_t tmp; - uint8_t rombuf[24]; - size_t devices_on_bus = 0; - size_t i = 0; - bool presence; - - onewireObjectInit(&OWD1); - onewireStart(&OWD1, &ow_cfg); - -#if ONEWIRE_SYNTH_SEARCH_TEST - synthSearchRomTest(&OWD1); -#endif - - for (i=0; i<3; i++) - temperature[i] = -666; - - while (true) { - if (true == onewireReset(&OWD1)){ - - memset(rombuf, 0x55, sizeof(rombuf)); - search_led_on(); - devices_on_bus = onewireSearchRom(&OWD1, rombuf, 3); - search_led_off(); - osalDbgCheck(devices_on_bus <= 3); - osalDbgCheck(devices_on_bus > 0); - - if (1 == devices_on_bus){ - /* test read rom command */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - testbuf[0] = ONEWIRE_CMD_READ_ROM; - onewireWrite(&OWD1, testbuf, 1, 0); - onewireRead(&OWD1, testbuf, 8); - osalDbgCheck(testbuf[7] == onewireCRC(testbuf, 7)); - osalDbgCheck(0 == memcmp(rombuf, testbuf, 8)); - } - - /* start temperature measurement on all connected devices at once */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - testbuf[0] = ONEWIRE_CMD_SKIP_ROM; - testbuf[1] = ONEWIRE_CMD_CONVERT_TEMP; - -#if ONEWIRE_USE_STRONG_PULLUP - onewireWrite(&OWD1, testbuf, 2, MS2ST(750)); -#else - onewireWrite(&OWD1, testbuf, 2, 0); - /* poll bus waiting ready signal from all connected devices */ - testbuf[0] = 0; - while (testbuf[0] == 0){ - osalThreadSleepMilliseconds(50); - onewireRead(&OWD1, testbuf, 1); - } -#endif - - for (i=0; i<devices_on_bus; i++) { - /* read temperature device by device from their scratchpads */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - - testbuf[0] = ONEWIRE_CMD_MATCH_ROM; - memcpy(&testbuf[1], &rombuf[i*8], 8); - testbuf[9] = ONEWIRE_CMD_READ_SCRATCHPAD; - onewireWrite(&OWD1, testbuf, 10, 0); - - onewireRead(&OWD1, testbuf, 9); - osalDbgCheck(testbuf[8] == onewireCRC(testbuf, 8)); - memcpy(&tmp, &testbuf, 2); - temperature[i] = ((int32_t)tmp * 625) / 10; - } - } - else { - osalSysHalt("No devices found"); - } - osalThreadSleep(1); /* enforce ChibiOS's stack overflow check */ - } - - onewireStop(&OWD1); -} diff --git a/testhal/STM32/STM32F1xx/onewire/real_roms.txt b/testhal/STM32/STM32F1xx/onewire/real_roms.txt deleted file mode 100644 index ea19c1a..0000000 --- a/testhal/STM32/STM32F1xx/onewire/real_roms.txt +++ /dev/null @@ -1,27 +0,0 @@ -rombuf[0] 0x28 -rombuf[1] 0xec -rombuf[2] 0xf5 -rombuf[3] 0x67 -rombuf[4] 0x5 -rombuf[5] 0x0 -rombuf[6] 0x0 -rombuf[7] 0x1d - -rombuf[8] 0x28 -rombuf[9] 0xbd -rombuf[10] 0x1a -rombuf[11] 0x60 -rombuf[12] 0x5 -rombuf[13] 0x0 -rombuf[14] 0x0 -rombuf[15] 0x37 - -rombuf[16] 0x28 -rombuf[17] 0x83 -rombuf[18] 0x7d -rombuf[19] 0x67 -rombuf[20] 0x5 -rombuf[21] 0x0 -rombuf[22] 0x0 -rombuf[23] 0xf - diff --git a/testhal/STM32/STM32F1xx/onewire/search_rom_synth.c b/testhal/STM32/STM32F1xx/onewire/search_rom_synth.c deleted file mode 100644 index cd2528f..0000000 --- a/testhal/STM32/STM32F1xx/onewire/search_rom_synth.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include <stdlib.h> - -/* - ****************************************************************************** - * DEFINES - ****************************************************************************** - */ - -/* do not set it more than 64 because of some fill_pattern functions - * will be broken.*/ -#define SYNTH_DEVICES_MAX 64 - -/* - * synthetic device - */ -typedef struct { - bool active; - uint64_t id; -} OWSynthDevice; - -/* - * synthetic bus - */ -typedef struct { - OWSynthDevice devices[SYNTH_DEVICES_MAX]; - size_t dev_present; - bool complement_bit; - ioline_t rom_bit; -} OWSynthBus; - -/* - ****************************************************************************** - * EXTERNS - ****************************************************************************** - */ - -/* - ****************************************************************************** - * PROTOTYPES - ****************************************************************************** - */ - -/* - ****************************************************************************** - * GLOBAL VARIABLES - ****************************************************************************** - */ - -static OWSynthBus synth_bus; - -/* - * local buffer for discovered ROMs - */ -static uint64_t detected_devices[SYNTH_DEVICES_MAX]; - -/* - ****************************************************************************** - ****************************************************************************** - * LOCAL FUNCTIONS - ****************************************************************************** - ****************************************************************************** - */ - -/* - ****************************************************************************** - * EXPORTED FUNCTIONS - ****************************************************************************** - */ - -/** - * - */ -void _synth_ow_write_bit(onewireDriver *owp, ioline_t bit) { - (void)owp; - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) { - if (((synth_bus.devices[i].id >> synth_bus.rom_bit) & 1U) != bit) { - synth_bus.devices[i].active = false; - } - } - synth_bus.rom_bit++; -} - -/** - * - */ -ioline_t _synth_ow_read_bit(void) { - ioline_t ret = 0xFF; - size_t i; - ioline_t bit; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) { - if (synth_bus.devices[i].active){ - bit = (synth_bus.devices[i].id >> synth_bus.rom_bit) & 1U; - if (synth_bus.complement_bit){ - bit ^= 1U; - } - if (0xFF == ret) - ret = bit; - else - ret &= bit; - } - } - synth_bus.complement_bit = !synth_bus.complement_bit; - return ret; -} - -/** - * - */ -static void synth_reset_pulse(void){ - size_t i; - - for (i=0; i<synth_bus.dev_present; i++){ - synth_bus.devices[i].active = true; - } -} - -/** - * - */ -static size_t synth_search_rom(onewireDriver *owp, uint8_t *result, size_t max_rom_cnt) { - - size_t i; - - search_clean_start(&owp->search_rom); - - do { - /* initialize buffer to store result */ - if (owp->search_rom.reg.devices_found >= max_rom_cnt) - owp->search_rom.retbuf = result + 8*(max_rom_cnt-1); - else - owp->search_rom.retbuf = result + 8*owp->search_rom.reg.devices_found; - memset(owp->search_rom.retbuf, 0, 8); - - /* clean iteration state */ - search_clean_iteration(&owp->search_rom); - - /**/ - synth_reset_pulse(); - synth_bus.rom_bit = 0; - synth_bus.complement_bit = false; - for (i=0; i<64*3 - 1; i++){ - ow_search_rom_cb(NULL, owp); - } - - if (ONEWIRE_SEARCH_ROM_ERROR != owp->search_rom.reg.result) { - /* store cached result for usage in next iteration */ - memcpy(owp->search_rom.prev_path, owp->search_rom.retbuf, 8); - } - } - while (ONEWIRE_SEARCH_ROM_SUCCESS == owp->search_rom.reg.result); - - /**/ - if (ONEWIRE_SEARCH_ROM_ERROR == owp->search_rom.reg.result) - return 0; - else - return owp->search_rom.reg.devices_found; -} - -/** - * - */ -static void fill_pattern_real_devices(void) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - synth_bus.devices[0].active = true; - synth_bus.devices[0].id = 0x1d00000567f5ec28; - - synth_bus.devices[1].active = true; - synth_bus.devices[1].id = 0x37000005601abd28; - - synth_bus.devices[2].active = true; - synth_bus.devices[2].id = 0x0f000005677d8328; -} - -/** - * - */ -static void fill_pattern_00(size_t devices, size_t start) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = (start + i); - } -} - -/** - * - */ -static void fill_pattern_01(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = (devices - i); - } -} - -/** - * - */ -static void fill_pattern_02(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = ((uint64_t)1 << i); - } -} - -/** - * - */ -static void fill_pattern_03(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = ((uint64_t)0x8000000000000000 >> i); - } -} - -/** - * @brief random pattern helper - */ -static bool is_id_uniq(const OWSynthDevice *dev, size_t n, uint64_t id) { - size_t i; - - for (i=0; i<n; i++) { - if (dev[i].id == id) - return false; - } - return true; -} - -/** - * - */ -static void fill_pattern_rand(size_t devices) { - size_t i; - uint64_t new_id; - - for (i=0; i<SYNTH_DEVICES_MAX; i++){ - synth_bus.devices[i].active = false; - synth_bus.devices[i].id = 0; - } - - for (i=0; i<devices; i++) { - do { - new_id = rand(); - new_id = (new_id << 32) | rand(); - } while (true != is_id_uniq(synth_bus.devices, i, new_id)); - - synth_bus.devices[i].id = new_id; - synth_bus.devices[i].active = true; - } -} - -/** - * - */ -static bool check_result(size_t detected) { - - size_t i,j; - bool match = false; - - for (i=0; i<detected; i++){ - match = false; - for (j=0; j<detected; j++){ - if (synth_bus.devices[i].id == detected_devices[j]){ - match = true; - break; - } - } - if (false == match) - return OSAL_FAILED; - } - return OSAL_SUCCESS; -} - -/** - * - */ -void synthSearchRomTest(onewireDriver *owp) { - - size_t detected = 0; - size_t i; - - synth_bus.dev_present = 3; - fill_pattern_real_devices(); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - for (i=1; i<=SYNTH_DEVICES_MAX; i++){ - synth_bus.dev_present = i; - - fill_pattern_00(synth_bus.dev_present, 0); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_00(synth_bus.dev_present, 1); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_01(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_02(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_03(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - } - - i = 0; - while (i < 1000) { - synth_bus.dev_present = 1 + (rand() & 63); - - fill_pattern_rand(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - i++; - } -} - - diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/.cproject b/testhal/STM32/STM32F4xx/FSMC_NAND/.cproject index d5451e0..034a4fc 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/.cproject +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/.cproject @@ -1,33 +1,79 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="0.1641850078"> - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.1641850078" moduleId="org.eclipse.cdt.core.settings" name="Default"> + <cconfiguration id="0.114656749"> + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.114656749" moduleId="org.eclipse.cdt.core.settings" name="Default"> <externalSettings/> <extensions> - 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<scannerConfigBuildInfo instanceId="0.1570569554"> + <scannerConfigBuildInfo instanceId="0.114656749"> <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/> </scannerConfigBuildInfo> - <scannerConfigBuildInfo instanceId="0.1641850078"> - <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - </scannerConfigBuildInfo> </storageModule> <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="refreshScope"/> </cproject> diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c index e36fbc9..3c60484 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c @@ -53,6 +53,7 @@ static const SPIConfig spicfg = { GPIOA, GPIOA_SPI1_NSS, 0, //SPI_CR1_BR_1 | SPI_CR1_BR_0 + 0 }; static uint32_t ints; diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h index e690d15..dbc1950 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h @@ -62,7 +62,7 @@ * @brief Enables the EXT subsystem. */ #if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT TRUE +#define HAL_USE_EXT FALSE #endif /** diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c index 2379a12..e75a937 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c @@ -56,8 +56,6 @@ ****************************************************************************** */ -#define USE_BAD_MAP TRUE - #define USE_KILL_BLOCK_TEST FALSE #define FSMCNAND_TIME_SET ((uint32_t) 2) //(8nS) @@ -74,7 +72,7 @@ #define NAND_COL_WRITE_CYCLES 2 #define NAND_TEST_START_BLOCK 1200 -#define NAND_TEST_END_BLOCK 1220 +#define NAND_TEST_END_BLOCK 1300 #if USE_KILL_BLOCK_TEST #define NAND_TEST_KILL_BLOCK 8000 @@ -88,6 +86,8 @@ #error "You should enable at least one NAND interface" #endif +#define BAD_MAP_LEN (NAND_BLOCKS_COUNT / (sizeof(bitmap_word_t) * 8)) + /* ****************************************************************************** * EXTERNS @@ -99,11 +99,6 @@ * PROTOTYPES ****************************************************************************** */ -#if STM32_NAND_USE_EXT_INT -static void ready_isr_enable(void); -static void ready_isr_disable(void); -static void nand_ready_cb(EXTDriver *extp, expchannel_t channel); -#endif /* ****************************************************************************** @@ -126,14 +121,14 @@ static time_measurement_t tmu_read_data; static time_measurement_t tmu_read_spare; static time_measurement_t tmu_driver_start; -#if USE_BAD_MAP -#define BAD_MAP_LEN (NAND_BLOCKS_COUNT / (sizeof(bitmap_word_t) * 8)) -static bitmap_word_t badblock_map_array[BAD_MAP_LEN]; +/* + * + */ +static bitmap_word_t badblock_map_array[BAD_MAP_LEN]; static bitmap_t badblock_map = { badblock_map_array, BAD_MAP_LEN }; -#endif /* * @@ -147,47 +142,11 @@ static const NANDConfig nandcfg = { NAND_COL_WRITE_CYCLES, /* stm32 specific fields */ ((FSMCNAND_TIME_HIZ << 24) | (FSMCNAND_TIME_HOLD << 16) | \ - (FSMCNAND_TIME_WAIT << 8) | FSMCNAND_TIME_SET), -#if STM32_NAND_USE_EXT_INT - ready_isr_enable, - ready_isr_disable -#endif + (FSMCNAND_TIME_WAIT << 8) | FSMCNAND_TIME_SET) }; -/** - * - */ -#if STM32_NAND_USE_EXT_INT -static const EXTConfig extcfg = { - { - {EXT_CH_MODE_DISABLED, NULL}, //0 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, //4 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_RISING_EDGE | EXT_MODE_GPIOD, nand_ready_cb}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, //8 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, //12 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, //16 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, //20 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - } -}; -#endif /* STM32_NAND_USE_EXT_INT */ - static volatile uint32_t BackgroundThdCnt = 0; +static thread_reference_t background_thd_ptr = NULL; #if USE_KILL_BLOCK_TEST static uint32_t KillCycle = 0; @@ -202,25 +161,10 @@ static uint32_t KillCycle = 0; */ static void nand_wp_assert(void) {palClearPad(GPIOB, GPIOB_NAND_WP);} static void nand_wp_release(void) {palSetPad(GPIOB, GPIOB_NAND_WP);} -static void red_led_on(void) {palSetPad(GPIOI, GPIOI_LED_R);} +//static void red_led_on(void) {palSetPad(GPIOI, GPIOI_LED_R);} static void red_led_off(void) {palClearPad(GPIOI, GPIOI_LED_R);} - -#if STM32_NAND_USE_EXT_INT -static void nand_ready_cb(EXTDriver *extp, expchannel_t channel){ - (void)extp; - (void)channel; - - NAND.isr_handler(&NAND); -} - -static void ready_isr_enable(void) { - extChannelEnable(&EXTD1, GPIOD_NAND_RB_NWAIT); -} - -static void ready_isr_disable(void) { - extChannelDisable(&EXTD1, GPIOD_NAND_RB_NWAIT); -} -#endif /* STM32_NAND_USE_EXT_INT */ +static void red_led_toggle(void) {palTogglePad(GPIOI, GPIOI_LED_R);} +static void green_led_toggle(void) {palTogglePad(GPIOI, GPIOI_LED_G);} /** * @@ -467,8 +411,6 @@ static void general_test (NANDDriver *nandp, size_t first, uint8_t op_status; uint32_t recc, wecc; - red_led_on(); - /* initialize time measurement units */ chTMObjectInit(&tmu_erase); chTMObjectInit(&tmu_write_data); @@ -478,16 +420,38 @@ static void general_test (NANDDriver *nandp, size_t first, /* perform basic checks */ for (block=first; block<last; block++){ + red_led_toggle(); + if (!nandIsBad(nandp, block)){ + if (!is_erased(nandp, block)){ + op_status = nandErase(nandp, block); + osalDbgCheck(0 == (op_status & 1)); /* operation failed */ + } + } + } + + /* check fail status */ + for (block=first; block<last; block++){ if (!nandIsBad(nandp, block)){ if (!is_erased(nandp, block)){ op_status = nandErase(nandp, block); osalDbgCheck(0 == (op_status & 1)); /* operation failed */ } + pattern_fill(); + op_status = nandWritePageData(nandp, block, 0, + nand_buf, nandp->config->page_data_size, &wecc); + osalDbgCheck(0 == (op_status & 1)); + + pattern_fill(); + op_status = nandWritePageData(nandp, block, 0, + nand_buf, nandp->config->page_data_size, &wecc); + /* operation must failed here because of write in unerased space */ + osalDbgCheck(1 == (op_status & 1)); } } /* write block with pattern, read it back and compare */ for (block=first; block<last; block++){ + red_led_toggle(); if (!nandIsBad(nandp, block)){ for (page=0; page<nandp->config->pages_per_block; page++){ pattern_fill(); @@ -538,17 +502,10 @@ static void general_test (NANDDriver *nandp, size_t first, red_led_off(); } - /* - ****************************************************************************** - * EXPORTED FUNCTIONS - ****************************************************************************** - */ - -/* - * Application entry point. + * */ -int main(void) { +static void nand_test(bool use_badblock_map) { /* performance counters */ int32_t adc_ints = 0; @@ -560,40 +517,26 @@ int main(void) { uint32_t background_cnt = 0; systime_t T = 0; - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - -#if STM32_NAND_USE_EXT_INT - extStart(&EXTD1, &extcfg); -#endif chTMObjectInit(&tmu_driver_start); chTMStartMeasurementX(&tmu_driver_start); -#if USE_BAD_MAP - nandStart(&NAND, &nandcfg, &badblock_map); -#else - nandStart(&NAND, &nandcfg, NULL); -#endif + if (use_badblock_map) { + nandStart(&NAND, &nandcfg, &badblock_map); + } + else { + nandStart(&NAND, &nandcfg, NULL); + } chTMStopMeasurementX(&tmu_driver_start); chThdSleepMilliseconds(4000); - chThdCreateStatic(BackgroundThreadWA, - sizeof(BackgroundThreadWA), - NORMALPRIO - 20, - BackgroundThread, - NULL); - - nand_wp_release(); + BackgroundThdCnt = 0; + if (NULL != background_thd_ptr) { + background_thd_ptr = chThdCreateStatic(BackgroundThreadWA, + sizeof(BackgroundThreadWA), NORMALPRIO - 10, BackgroundThread, NULL); + } /* - * run NAND test in parallel with DMA load and background thread + * run NAND test in parallel with DMA loads and background thread */ dma_storm_adc_start(); dma_storm_uart_start(); @@ -601,9 +544,9 @@ int main(void) { T = chVTGetSystemTimeX(); general_test(&NAND, NAND_TEST_START_BLOCK, NAND_TEST_END_BLOCK, 1); T = chVTGetSystemTimeX() - T; - adc_ints = dma_storm_adc_stop(); + adc_ints = dma_storm_adc_stop(); uart_ints = dma_storm_uart_stop(); - spi_ints = dma_storm_spi_stop(); + spi_ints = dma_storm_spi_stop(); chSysLock(); background_cnt = BackgroundThdCnt; BackgroundThdCnt = 0; @@ -632,6 +575,35 @@ int main(void) { * perform ECC calculation test */ ecc_test(&NAND, NAND_TEST_END_BLOCK); +} + +/* + ****************************************************************************** + * EXPORTED FUNCTIONS + ****************************************************************************** + */ + +/* + * Application entry point. + */ +int main(void) { + + + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + nand_wp_release(); + + nand_test(true); + nand_test(false); #if USE_KILL_BLOCK_TEST kill_block(&NAND, NAND_TEST_KILL_BLOCK); @@ -642,7 +614,9 @@ int main(void) { /* * Normal main() thread activity, in this demo it does nothing. */ + red_led_off(); while (true) { + green_led_toggle(); chThdSleepMilliseconds(500); } } diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h index 9638dbe..dd72e66 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h @@ -26,7 +26,6 @@ */ #define STM32_NAND_USE_FSMC_NAND1 TRUE #define STM32_NAND_USE_FSMC_NAND2 FALSE -#define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 #define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") diff --git a/testhal/STM32/STM32F4xx/onewire/.cproject b/testhal/STM32/STM32F4xx/onewire/.cproject index f6e2450..d2cdbd2 100644 --- a/testhal/STM32/STM32F4xx/onewire/.cproject +++ b/testhal/STM32/STM32F4xx/onewire/.cproject @@ -49,4 +49,5 @@ </scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="refreshScope"/>
</cproject>
diff --git a/testhal/STM32/STM32F4xx/onewire/.project b/testhal/STM32/STM32F4xx/onewire/.project index 30d6ff3..a82f065 100644 --- a/testhal/STM32/STM32F4xx/onewire/.project +++ b/testhal/STM32/STM32F4xx/onewire/.project @@ -1,6 +1,6 @@ <?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
- <name>STM32F4xx-onewire</name>
+ <name>STM32F4xx-1-Wire</name>
<comment></comment>
<projects>
</projects>
@@ -80,12 +80,18 @@ <link>
<name>os-community</name>
<type>2</type>
- <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
+ <locationURI>CHIBIOS_CONTRIB/os</locationURI>
</link>
<link>
<name>os-git</name>
<type>2</type>
- <locationURI>PARENT-5-PROJECT_LOC/ChibiOS-RT/os</locationURI>
+ <locationURI>copy_PARENT/ChibiOS-RT/os</locationURI>
</link>
</linkedResources>
+ <variableList>
+ <variable>
+ <name>copy_PARENT</name>
+ <value>$%7BPARENT-1-CHIBIOS%7D</value>
+ </variable>
+ </variableList>
</projectDescription>
diff --git a/testhal/STM32/STM32F4xx/onewire/Makefile b/testhal/STM32/STM32F4xx/onewire/Makefile index 02ab018..092b023 100644 --- a/testhal/STM32/STM32F4xx/onewire/Makefile +++ b/testhal/STM32/STM32F4xx/onewire/Makefile @@ -88,6 +88,7 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +TESTHAL = $(CHIBIOS_CONTRIB)/testhal/common/onewire # Startup files. include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk # HAL-OSAL files (optional). @@ -113,7 +114,7 @@ CSRC = $(STARTUPSRC) \ $(BOARDSRC) \ $(TESTSRC) \ main.c \ - onewire_test.c + $(TESTHAL)/testhal_onewire.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -146,7 +147,8 @@ ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) INCDIR = $(CHIBIOS)/os/license \ $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ - $(CHIBIOS)/os/various + $(CHIBIOS)/os/various \ + $(TESTHAL) # # Project, sources and paths diff --git a/testhal/STM32/STM32F4xx/onewire/boarddef.h b/testhal/STM32/STM32F4xx/onewire/boarddef.h new file mode 100644 index 0000000..a048dcb --- /dev/null +++ b/testhal/STM32/STM32F4xx/onewire/boarddef.h @@ -0,0 +1,28 @@ +/* + ChibiOS/RT - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef BOARDDEF_H_ +#define BOARDDEF_H_ + +#define ONEWIRE_PORT GPIOB +#define ONEWIRE_PIN GPIOB_PIN0 +#define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) +#define search_led_off() (palClearPad(GPIOD, GPIOD_LED4)) +#define search_led_on() (palSetPad(GPIOD, GPIOD_LED4)) +#define ONEWIRE_MASTER_CHANNEL 2 +#define ONEWIRE_SAMPLE_CHANNEL 3 + +#endif /* BOARDDEF_H_ */ diff --git a/testhal/STM32/STM32F4xx/onewire/main.c b/testhal/STM32/STM32F4xx/onewire/main.c index 793bffe..5265edc 100644 --- a/testhal/STM32/STM32F4xx/onewire/main.c +++ b/testhal/STM32/STM32F4xx/onewire/main.c @@ -17,7 +17,7 @@ #include "ch.h"
#include "hal.h"
-#include "onewire_test.h"
+#include "testhal_onewire.h"
/*
* Application entry point.
diff --git a/testhal/STM32/STM32F4xx/onewire/onewire_test.c b/testhal/STM32/STM32F4xx/onewire/onewire_test.c deleted file mode 100644 index be20dbc..0000000 --- a/testhal/STM32/STM32F4xx/onewire/onewire_test.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include <string.h> - -#include "hal.h" - -/* - ****************************************************************************** - * DEFINES - ****************************************************************************** - */ - -#if defined(BOARD_ST_STM32F4_DISCOVERY) || \ - defined(BOARD_ST_STM32F0_DISCOVERY) || \ - defined(BOARD_ST_STM32F0308_DISCOVERY) - #if ONEWIRE_USE_STRONG_PULLUP - #error "This board has not enough voltage for this feature" - #endif -#endif - -#if defined(BOARD_ST_STM32F0308_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOC, GPIOC_LED4)) - #define search_led_on() (palSetPad(GPIOC, GPIOC_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_ST_STM32F4_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOD, GPIOD_LED4)) - #define search_led_on() (palSetPad(GPIOD, GPIOD_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_OLIMEX_STM32_103STK) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN 0 - #define ONEWIRE_PAD_MODE_IDLE PAL_MODE_INPUT - #define ONEWIRE_PAD_MODE_ACTIVE PAL_MODE_STM32_ALTERNATE_OPENDRAIN - #define search_led_on() (palClearPad(GPIOC, GPIOC_LED)) - #define search_led_off() (palSetPad(GPIOC, GPIOC_LED)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#else - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_TACHOMETER - #include "pads.h" - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_on red_led_on - #define search_led_off red_led_off - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#endif - -/* - ****************************************************************************** - * EXTERNS - ****************************************************************************** - */ - -/* - ****************************************************************************** - * PROTOTYPES - ****************************************************************************** - */ -/* - * Forward declarations - */ -#if ONEWIRE_USE_STRONG_PULLUP -static void strong_pullup_assert(void); -static void strong_pullup_release(void); -#endif - -/* - ****************************************************************************** - * GLOBAL VARIABLES - ****************************************************************************** - */ - -static uint8_t testbuf[12]; - -/* stores 3 temperature values in millicelsius */ -static int32_t temperature[3]; - -/* - * Config for underlied PWM driver. - * Note! It is NOT constant because 1-wire driver needs to change them - * during functioning. - */ -static PWMConfig pwm_cfg = { - 0, - 0, - NULL, - { - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL} - }, - 0, -#if STM32_PWM_USE_ADVANCED - 0, -#endif - 0 -}; - -/* - * - */ -static const onewireConfig ow_cfg = { - &PWMD3, - &pwm_cfg, - PWM_OUTPUT_ACTIVE_LOW, - ONEWIRE_MASTER_CHANNEL, - ONEWIRE_SAMPLE_CHANNEL, - ONEWIRE_PORT, - ONEWIRE_PIN, -#if defined(STM32F1XX) - ONEWIRE_PAD_MODE_IDLE, -#endif - ONEWIRE_PAD_MODE_ACTIVE, -#if ONEWIRE_USE_STRONG_PULLUP - strong_pullup_assert, - strong_pullup_release -#endif -}; - -/* - ****************************************************************************** - ****************************************************************************** - * LOCAL FUNCTIONS - ****************************************************************************** - ****************************************************************************** - */ - -#if ONEWIRE_USE_STRONG_PULLUP -/** - * - */ -static void strong_pullup_assert(void) { - palSetPadMode(ONEWIRE_PORT, ONEWIRE_PIN, PAL_MODE_STM32_ALTERNATE_PUSHPULL); -} - -/** - * - */ -static void strong_pullup_release(void) { - palSetPadMode(ONEWIRE_PORT, ONEWIRE_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); -} -#endif /* ONEWIRE_USE_STRONG_PULLUP */ - -/* - ****************************************************************************** - * EXPORTED FUNCTIONS - ****************************************************************************** - */ - -/** - * - */ -void onewireTest(void) { - - int16_t tmp; - uint8_t rombuf[24]; - size_t devices_on_bus = 0; - size_t i = 0; - bool presence; - - onewireObjectInit(&OWD1); - onewireStart(&OWD1, &ow_cfg); - -#if ONEWIRE_SYNTH_SEARCH_TEST - synthSearchRomTest(&OWD1); -#endif - - for (i=0; i<3; i++) - temperature[i] = -666; - - while (true) { - if (true == onewireReset(&OWD1)){ - - memset(rombuf, 0x55, sizeof(rombuf)); - search_led_on(); - devices_on_bus = onewireSearchRom(&OWD1, rombuf, 3); - search_led_off(); - osalDbgCheck(devices_on_bus <= 3); - osalDbgCheck(devices_on_bus > 0); - - if (1 == devices_on_bus){ - /* test read rom command */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - testbuf[0] = ONEWIRE_CMD_READ_ROM; - onewireWrite(&OWD1, testbuf, 1, 0); - onewireRead(&OWD1, testbuf, 8); - osalDbgCheck(testbuf[7] == onewireCRC(testbuf, 7)); - osalDbgCheck(0 == memcmp(rombuf, testbuf, 8)); - } - - /* start temperature measurement on all connected devices at once */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - testbuf[0] = ONEWIRE_CMD_SKIP_ROM; - testbuf[1] = ONEWIRE_CMD_CONVERT_TEMP; - -#if ONEWIRE_USE_STRONG_PULLUP - onewireWrite(&OWD1, testbuf, 2, MS2ST(750)); -#else - onewireWrite(&OWD1, testbuf, 2, 0); - /* poll bus waiting ready signal from all connected devices */ - testbuf[0] = 0; - while (testbuf[0] == 0){ - osalThreadSleepMilliseconds(50); - onewireRead(&OWD1, testbuf, 1); - } -#endif - - for (i=0; i<devices_on_bus; i++) { - /* read temperature device by device from their scratchpads */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - - testbuf[0] = ONEWIRE_CMD_MATCH_ROM; - memcpy(&testbuf[1], &rombuf[i*8], 8); - testbuf[9] = ONEWIRE_CMD_READ_SCRATCHPAD; - onewireWrite(&OWD1, testbuf, 10, 0); - - onewireRead(&OWD1, testbuf, 9); - osalDbgCheck(testbuf[8] == onewireCRC(testbuf, 8)); - memcpy(&tmp, &testbuf, 2); - temperature[i] = ((int32_t)tmp * 625) / 10; - } - } - else { - osalSysHalt("No devices found"); - } - osalThreadSleep(1); /* enforce ChibiOS's stack overflow check */ - } - - onewireStop(&OWD1); -} diff --git a/testhal/STM32/STM32F4xx/onewire/real_roms.txt b/testhal/STM32/STM32F4xx/onewire/real_roms.txt deleted file mode 100644 index ea19c1a..0000000 --- a/testhal/STM32/STM32F4xx/onewire/real_roms.txt +++ /dev/null @@ -1,27 +0,0 @@ -rombuf[0] 0x28 -rombuf[1] 0xec -rombuf[2] 0xf5 -rombuf[3] 0x67 -rombuf[4] 0x5 -rombuf[5] 0x0 -rombuf[6] 0x0 -rombuf[7] 0x1d - -rombuf[8] 0x28 -rombuf[9] 0xbd -rombuf[10] 0x1a -rombuf[11] 0x60 -rombuf[12] 0x5 -rombuf[13] 0x0 -rombuf[14] 0x0 -rombuf[15] 0x37 - -rombuf[16] 0x28 -rombuf[17] 0x83 -rombuf[18] 0x7d -rombuf[19] 0x67 -rombuf[20] 0x5 -rombuf[21] 0x0 -rombuf[22] 0x0 -rombuf[23] 0xf - diff --git a/testhal/STM32/STM32F7xx/USB_MSD/.cproject b/testhal/STM32/STM32F7xx/USB_MSD/.cproject new file mode 100644 index 0000000..e263f01 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/.cproject @@ -0,0 +1,50 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> + <storageModule moduleId="org.eclipse.cdt.core.settings"> + <cconfiguration id="0.1487191575"> + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.1487191575" moduleId="org.eclipse.cdt.core.settings" name="Default"> + <externalSettings/> + <extensions> + <extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + </extensions> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <configuration artifactName="${ProjName}" buildProperties="" description="" id="0.1487191575" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg"> + <folderInfo id="0.1487191575." name="/" resourcePath=""> + <toolChain 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languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> + </tool> + <tool id="org.eclipse.cdt.build.core.settings.holder.797753085" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder"> + <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.643916244" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> + </tool> + <tool id="org.eclipse.cdt.build.core.settings.holder.626880334" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder"> + <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.154285937" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> + </tool> + </toolChain> + </folderInfo> + </configuration> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> + </cconfiguration> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <project id="STM32F7xx-USB_RAW.null.1373754647" name="STM32F7xx-USB_RAW"/> + </storageModule> + <storageModule moduleId="scannerConfiguration"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> + <scannerConfigBuildInfo instanceId="0.1487191575"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/> + </scannerConfigBuildInfo> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="refreshScope"/> +</cproject> diff --git a/testhal/STM32/STM32F7xx/USB_MSD/.project b/testhal/STM32/STM32F7xx/USB_MSD/.project new file mode 100644 index 0000000..ac40e79 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/.project @@ -0,0 +1,43 @@ +<?xml version="1.0" encoding="UTF-8"?> +<projectDescription> + <name>STM32F7xx-USB_MSD</name> + <comment></comment> + <projects> + </projects> + <buildSpec> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> + <triggers>clean,full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> + <triggers>full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + </buildSpec> + <natures> + <nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> + <linkedResources> + <link> + <name>os</name> + <type>2</type> + <locationURI>CHIBIOS/os</locationURI> + </link> + <link> + <name>os-contrib</name> + <type>2</type> + <locationURI>CHIBIOS_CONTRIB/os</locationURI> + </link> + <link> + <name>test</name> + <type>2</type> + <locationURI>CHIBIOS/test</locationURI> + </link> + </linkedResources> +</projectDescription> diff --git a/testhal/STM32/STM32F7xx/USB_MSD/Makefile b/testhal/STM32/STM32F7xx/USB_MSD/Makefile new file mode 100644 index 0000000..ac17448 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/Makefile @@ -0,0 +1,233 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 -fsingle-precision-constant +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib + +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/test/rt/test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32F767Zx.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + $(STREAMSSRC) \ + $(SHELLSRC) \ + $(CHIBIOS_CONTRIB)/os/various/ramdisk.c \ + $(CHIBIOS_CONTRIB)/os/various/lib_scsi.c \ + usbcfg.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = +ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(CHIBIOS)/os/license \ + $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(STREAMSINC) $(SHELLINC) \ + $(CHIBIOS_CONTRIB)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m7 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = ccache $(TRGT)gcc +CPPC = ccache $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/STM32/STM32F7xx/USB_MSD/chconf.h b/testhal/STM32/STM32F7xx/USB_MSD/chconf.h new file mode 100644 index 0000000..8bdd9f2 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/chconf.h @@ -0,0 +1,522 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK TRUE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS TRUE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS TRUE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK TRUE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS TRUE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#define CORTEX_VTOR_INIT 0x00200000U + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/STM32/STM32F7xx/USB_MSD/halconf.h b/testhal/STM32/STM32F7xx/USB_MSD/halconf.h new file mode 100644 index 0000000..bf1b023 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/halconf.h @@ -0,0 +1,401 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the QSPI subsystem. + */ +#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) +#define HAL_USE_QSPI FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 115200 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 80 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* Community drivers's includes */ +/*===========================================================================*/ + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h b/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h new file mode 100644 index 0000000..943992f --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h @@ -0,0 +1,105 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _HALCONF_COMMUNITY_H_ +#define _HALCONF_COMMUNITY_H_ + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD TRUE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +#endif /* _HALCONF_COMMUNITY_H_ */ + +/** @} */ diff --git a/testhal/STM32/STM32F7xx/USB_MSD/main.c b/testhal/STM32/STM32F7xx/USB_MSD/main.c new file mode 100644 index 0000000..cae2b74 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/main.c @@ -0,0 +1,126 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include <stdio.h> +#include <string.h> + +#include "ch.h" +#include "hal.h" + +#include "usbcfg.h" +#include "hal_usb_msd.h" + +#include "ramdisk.h" +#include "romfs_img.h" + +#define RAMDISK_BLOCK_SIZE 512U +#define RAMDISK_BLOCK_CNT 700U + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + systime_t time; + + time = USBD1.state == USB_ACTIVE ? 100 : 500; + palSetPad(GPIOB, GPIOB_LED1); + chThdSleepMilliseconds(time); + palClearPad(GPIOB, GPIOB_LED1); + chThdSleepMilliseconds(time); + } +} + +RamDisk ramdisk; +__attribute__((section("DATA_RAM"))) static uint8_t ramdisk_storage[RAMDISK_BLOCK_SIZE * RAMDISK_BLOCK_CNT]; +static uint8_t blkbuf[RAMDISK_BLOCK_SIZE]; + +BaseSequentialStream *GlobalDebugChannel; + +static const SerialConfig sercfg = { + 115200, + 0, + 0, + 0 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + sdStart(&SD3, &sercfg); + GlobalDebugChannel = (BaseSequentialStream *)&SD3; + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(&USBD1); + chThdSleepMilliseconds(1500); + usbStart(&USBD1, &usbcfg); + + /* + * start RAM disk + */ + ramdiskObjectInit(&ramdisk); + memset(ramdisk_storage, 0x55, sizeof(ramdisk_storage)); + osalDbgCheck(sizeof(ramdisk_storage) >= romfs_bin_len); + memcpy(ramdisk_storage, romfs_bin, romfs_bin_len); + ramdiskStart(&ramdisk, ramdisk_storage, RAMDISK_BLOCK_SIZE, + RAMDISK_BLOCK_CNT, false); + + /* + * start mass storage + */ + msdObjectInit(&USBMSD1); + msdStart(&USBMSD1, &USBD1, (BaseBlockDevice *)&ramdisk, blkbuf, NULL); + + /* + * + */ + usbConnectBus(&USBD1); + + /* + * Starting threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + chThdSleepMilliseconds(1000); + } + + msdStop(&USBMSD1); +} diff --git a/testhal/STM32/STM32F7xx/USB_MSD/mcuconf.h b/testhal/STM32/STM32F7xx/USB_MSD/mcuconf.h new file mode 100644 index 0000000..c7bf7a1 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/mcuconf.h @@ -0,0 +1,386 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/STM32/STM32F7xx/USB_MSD/readme.txt b/testhal/STM32/STM32F7xx/USB_MSD/readme.txt new file mode 100644 index 0000000..ba23a07 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/HAL - USB MSD driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST NUCLEO144-F767ZI board. + +** The Demo ** + +The application demonstrates the use of the STM32 USB (OTG) driver as +a mass storage device. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32/STM32F7xx/USB_MSD/romfs_img.h b/testhal/STM32/STM32F7xx/USB_MSD/romfs_img.h new file mode 100644 index 0000000..2755b37 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/romfs_img.h @@ -0,0 +1,3775 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +const uint8_t romfs_bin[] = { + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0xb0, 0x00, + 0x5a, 0xbe, 0xcd, 0xd1, 0x72, 0x6f, 0x6d, 0x20, 0x35, 0x37, 0x66, 0x63, + 0x61, 0x39, 0x36, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x24, 0xc9, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x2a, 0x25, 0xf9, 0xd7, 0x74, 0x65, 0x78, 0x6d, 0x61, 0x74, 0x68, 0x73, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#include "hal_usb_cdc.h" +#include "hal_usb_msd.h" +#include "usbcfg.h" + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(0x0020, /* wTotalLength. */ + 0x01, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 0x32), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x08, /* bInterfaceClass (Mass Storage) */ + 0x06, /* bInterfaceSubClass (SCSI + Transparent storage class) */ + 0x50, /* bInterfaceProtocol (Bulk Only) */ + 0), /* iInterface. (none) */ + /* Mass Storage Data In Endpoint Descriptor.*/ + USB_DESC_ENDPOINT (USB_MSD_DATA_EP | 0x80, + 0x02, /* bmAttributes (Bulk). */ + USB_MSD_EP_SIZE, /* wMaxPacketSize. */ + 0x00), /* bInterval. 1ms */ + /* Mass Storage Data Out Endpoint Descriptor.*/ + USB_DESC_ENDPOINT (USB_MSD_DATA_EP, + 0x02, /* bmAttributes (Bulk). */ + USB_MSD_EP_SIZE, /* wMaxPacketSize. */ + 0x00) /* bInterval. 1ms */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(62), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'M', 0, 'a', 0, 's', 0, 's', 0, ' ', 0, + 'S', 0, 't', 0, 'o', 0, 'r', 0, 'a', 0, 'g', 0, 'e', 0, ' ', 0, + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0 +}; + +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(26), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'A', 0, 'E', 0, 'C', 0, 'C', 0, 'E', 0, 'C', 0, 'C', 0, 'C', 0, 'C', 0, + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + NULL, + NULL, + USB_MSD_EP_SIZE, + USB_MSD_EP_SIZE, + &ep1instate, + &ep1outstate, + 4, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + chSysUnlockFromISR(); + return; + case USB_EVENT_UNCONFIGURED: + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + msd_request_hook, + NULL +}; + diff --git a/testhal/STM32/STM32F0xx/onewire/onewire_test.h b/testhal/STM32/STM32F7xx/USB_MSD/usbcfg.h index 1bec2d0..496f478 100644 --- a/testhal/STM32/STM32F0xx/onewire/onewire_test.h +++ b/testhal/STM32/STM32F7xx/USB_MSD/usbcfg.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,15 +14,15 @@ limitations under the License. */ -#ifndef ONEWIRE_TEST_H_ -#define ONEWIRE_TEST_H_ +#ifndef USBCFG_H +#define USBCFG_H -#ifdef __cplusplus -extern "C" { -#endif - void onewireTest(void); -#ifdef __cplusplus -} -#endif +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 -#endif /* ONEWIRE_TEST_H_ */ +extern const USBConfig usbcfg; + +#endif /* USBCFG_H */ + +/** @} */ diff --git a/testhal/STM32/STM32F0xx/onewire/real_roms.txt b/testhal/common/onewire/real_roms.txt index ea19c1a..ea19c1a 100644 --- a/testhal/STM32/STM32F0xx/onewire/real_roms.txt +++ b/testhal/common/onewire/real_roms.txt diff --git a/testhal/STM32/STM32F4xx/onewire/search_rom_synth.c b/testhal/common/onewire/synth_searchrom.c index cd2528f..53d4a30 100644 --- a/testhal/STM32/STM32F4xx/onewire/search_rom_synth.c +++ b/testhal/common/onewire/synth_searchrom.c @@ -23,7 +23,7 @@ */ /* do not set it more than 64 because of some fill_pattern functions - * will be broken.*/ + will be broken.*/ #define SYNTH_DEVICES_MAX 64 /* @@ -83,7 +83,7 @@ static uint64_t detected_devices[SYNTH_DEVICES_MAX]; ****************************************************************************** */ -/** +/* * */ void _synth_ow_write_bit(onewireDriver *owp, ioline_t bit) { @@ -98,7 +98,7 @@ void _synth_ow_write_bit(onewireDriver *owp, ioline_t bit) { synth_bus.rom_bit++; } -/** +/* * */ ioline_t _synth_ow_read_bit(void) { @@ -122,7 +122,7 @@ ioline_t _synth_ow_read_bit(void) { return ret; } -/** +/* * */ static void synth_reset_pulse(void){ @@ -133,7 +133,7 @@ static void synth_reset_pulse(void){ } } -/** +/* * */ static size_t synth_search_rom(onewireDriver *owp, uint8_t *result, size_t max_rom_cnt) { @@ -175,7 +175,7 @@ static size_t synth_search_rom(onewireDriver *owp, uint8_t *result, size_t max_r return owp->search_rom.reg.devices_found; } -/** +/* * */ static void fill_pattern_real_devices(void) { @@ -194,7 +194,7 @@ static void fill_pattern_real_devices(void) { synth_bus.devices[2].id = 0x0f000005677d8328; } -/** +/* * */ static void fill_pattern_00(size_t devices, size_t start) { @@ -209,7 +209,7 @@ static void fill_pattern_00(size_t devices, size_t start) { } } -/** +/* * */ static void fill_pattern_01(size_t devices) { @@ -224,7 +224,7 @@ static void fill_pattern_01(size_t devices) { } } -/** +/* * */ static void fill_pattern_02(size_t devices) { @@ -239,7 +239,7 @@ static void fill_pattern_02(size_t devices) { } } -/** +/* * */ static void fill_pattern_03(size_t devices) { @@ -254,8 +254,8 @@ static void fill_pattern_03(size_t devices) { } } -/** - * @brief random pattern helper +/* + * Random pattern helper */ static bool is_id_uniq(const OWSynthDevice *dev, size_t n, uint64_t id) { size_t i; @@ -267,7 +267,7 @@ static bool is_id_uniq(const OWSynthDevice *dev, size_t n, uint64_t id) { return true; } -/** +/* * */ static void fill_pattern_rand(size_t devices) { @@ -290,7 +290,7 @@ static void fill_pattern_rand(size_t devices) { } } -/** +/* * */ static bool check_result(size_t detected) { @@ -312,7 +312,7 @@ static bool check_result(size_t detected) { return OSAL_SUCCESS; } -/** +/* * */ void synthSearchRomTest(onewireDriver *owp) { diff --git a/testhal/STM32/STM32F0xx/onewire/onewire_test.c b/testhal/common/onewire/testhal_onewire.c index be20dbc..93dcc31 100644 --- a/testhal/STM32/STM32F0xx/onewire/onewire_test.c +++ b/testhal/common/onewire/testhal_onewire.c @@ -17,10 +17,11 @@ #include <string.h> #include "hal.h" +#include "boarddef.h" /* ****************************************************************************** - * DEFINES + * ERROR CHECKS ****************************************************************************** */ @@ -32,41 +33,11 @@ #endif #endif -#if defined(BOARD_ST_STM32F0308_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOC, GPIOC_LED4)) - #define search_led_on() (palSetPad(GPIOC, GPIOC_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_ST_STM32F4_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOD, GPIOD_LED4)) - #define search_led_on() (palSetPad(GPIOD, GPIOD_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_OLIMEX_STM32_103STK) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN 0 - #define ONEWIRE_PAD_MODE_IDLE PAL_MODE_INPUT - #define ONEWIRE_PAD_MODE_ACTIVE PAL_MODE_STM32_ALTERNATE_OPENDRAIN - #define search_led_on() (palClearPad(GPIOC, GPIOC_LED)) - #define search_led_off() (palSetPad(GPIOC, GPIOC_LED)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#else - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_TACHOMETER - #include "pads.h" - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_on red_led_on - #define search_led_off red_led_off - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#endif +/* + ****************************************************************************** + * DEFINES + ****************************************************************************** + */ /* ****************************************************************************** @@ -99,7 +70,7 @@ static uint8_t testbuf[12]; static int32_t temperature[3]; /* - * Config for underlied PWM driver. + * Config for underlying PWM driver. * Note! It is NOT constant because 1-wire driver needs to change them * during functioning. */ @@ -171,7 +142,7 @@ static void strong_pullup_release(void) { ****************************************************************************** */ -/** +/* * */ void onewireTest(void) { diff --git a/testhal/STM32/STM32F1xx/onewire/onewire_test.h b/testhal/common/onewire/testhal_onewire.h index 1bec2d0..181e09f 100644 --- a/testhal/STM32/STM32F1xx/onewire/onewire_test.h +++ b/testhal/common/onewire/testhal_onewire.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef ONEWIRE_TEST_H_ -#define ONEWIRE_TEST_H_ +#ifndef TESTHAL_ONEWIRE_H_ +#define TESTHAL_ONEWIRE_H_ #ifdef __cplusplus extern "C" { @@ -25,4 +25,4 @@ extern "C" { } #endif -#endif /* ONEWIRE_TEST_H_ */ +#endif /* TESTHAL_ONEWIRE_H_ */ |