diff options
259 files changed, 37352 insertions, 5083 deletions
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile index 894fe9d..f399710 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile @@ -119,7 +119,7 @@ CSRC = $(STARTUPSRC) \ $(STREAMSSRC) \
$(SHELLSRC) \
$(CHIBIOS_CONTRIB)/os/various/devices_lib/lcd/ili9341.c \
- main.c \
+ main.c usbcfg.c \
wolf3d_palette.c \
res/wolf3d_vgagraph_chunk87.c
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h index e9b1a23..545e595 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h @@ -139,7 +139,7 @@ * @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
-#define HAL_USE_SERIAL_USB FALSE
+#define HAL_USE_SERIAL_USB TRUE
#endif
/**
@@ -160,7 +160,7 @@ * @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
-#define HAL_USE_USB FALSE
+#define HAL_USE_USB TRUE
#endif
/**
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h index 24b3e4d..c28b90b 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef _HALCONF_COMMUNITY_H_ -#define _HALCONF_COMMUNITY_H_ +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H /** * @brief Enables the community overlay. @@ -66,7 +66,6 @@ #define HAL_USE_RNG FALSE #endif - /*===========================================================================*/ /* FSMCNAND driver related settings. */ /*===========================================================================*/ @@ -94,6 +93,6 @@ */ #define ONEWIRE_USE_SEARCH_ROM TRUE -#endif /* _HALCONF_COMMUNITY_H_ */ +#endif /* HALCONF_COMMUNITY_H */ /** @} */ diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c index aa7ac10..2d8d356 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c @@ -288,6 +288,7 @@ const SPIConfig spi_cfg5 = { GPIOC,
GPIOC_SPI5_LCD_CS,
(((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR),
+ 0
};
extern SPIDriver SPID5;
@@ -473,10 +474,6 @@ static void dma2d_test(void) { /* Command line related. */
/*===========================================================================*/
-#if (HAL_USE_SERIAL_USB == TRUE)
-/* Virtual serial port over USB.*/
-SerialUSBDriver SDU1;
-#endif
#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048)
#define TEST_WA_SIZE THD_WORKING_AREA_SIZE(256)
@@ -500,7 +497,7 @@ static const ShellCommand commands[] = { static const ShellConfig shell_cfg1 = {
#if (HAL_USE_SERIAL_USB == TRUE)
- (BaseSequentialStream *)&SDU1,
+ (BaseSequentialStream *)&SDU2,
#else
(BaseSequentialStream *)&SD1,
#endif
@@ -536,8 +533,8 @@ int main(void) { /*
* Initializes a serial-over-USB CDC driver.
*/
- sduObjectInit(&SDU1);
- sduStart(&SDU1, &serusbcfg);
+ sduObjectInit(&SDU2);
+ sduStart(&SDU2, &serusbcfg);
/*
* Activates the USB driver and then the USB bus pull-up on D+.
@@ -594,7 +591,7 @@ int main(void) { while (true) {
if (!shelltp) {
#if (HAL_USE_SERIAL_USB == TRUE)
- if (SDU1.config->usbp->state == USB_ACTIVE) {
+ if (SDU2.config->usbp->state == USB_ACTIVE) {
/* Spawns a new shell.*/
shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, "shell", NORMALPRIO, shellThread, (void *) &shell_cfg1);
}
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h index 817ed59..ba13652 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h @@ -243,8 +243,8 @@ */
#define STM32_SDC_SDIO_DMA_PRIORITY 3
#define STM32_SDC_SDIO_IRQ_PRIORITY 9
-#define STM32_SDC_WRITE_TIMEOUT_MS 250
-#define STM32_SDC_READ_TIMEOUT_MS 25
+#define STM32_SDC_WRITE_TIMEOUT_MS 1000
+#define STM32_SDC_READ_TIMEOUT_MS 1000
#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
@@ -345,7 +345,7 @@ * USB driver system settings.
*/
#define STM32_USB_USE_OTG1 FALSE
-#define STM32_USB_USE_OTG2 FALSE
+#define STM32_USB_USE_OTG2 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.c index 9f95a2a..b03209b 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.c +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.c @@ -1,5 +1,5 @@ /*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -17,6 +17,9 @@ #include "ch.h"
#include "hal.h"
+/* Virtual serial port over USB.*/
+SerialUSBDriver SDU2;
+
/*
* Endpoints to be used for USBD2.
*/
@@ -262,11 +265,9 @@ static const USBEndpointConfig ep2config = { * Handles the USB driver global events.
*/
static void usb_event(USBDriver *usbp, usbevent_t event) {
- extern SerialUSBDriver SDU1;
+ extern SerialUSBDriver SDU2;
switch (event) {
- case USB_EVENT_RESET:
- return;
case USB_EVENT_ADDRESS:
return;
case USB_EVENT_CONFIGURED:
@@ -279,13 +280,29 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config);
/* Resetting the state of the CDC subsystem.*/
- sduConfigureHookI(&SDU1);
+ sduConfigureHookI(&SDU2);
chSysUnlockFromISR();
return;
+ case USB_EVENT_RESET:
+ /* Falls into.*/
+ case USB_EVENT_UNCONFIGURED:
+ /* Falls into.*/
case USB_EVENT_SUSPEND:
+ chSysLockFromISR();
+
+ /* Disconnection event on suspend.*/
+ sduSuspendHookI(&SDU2);
+
+ chSysUnlockFromISR();
return;
case USB_EVENT_WAKEUP:
+ chSysLockFromISR();
+
+ /* Disconnection event on suspend.*/
+ sduWakeupHookI(&SDU2);
+
+ chSysUnlockFromISR();
return;
case USB_EVENT_STALLED:
return;
@@ -294,13 +311,25 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { }
/*
+ * Handles the USB driver global events.
+ */
+static void sof_handler(USBDriver *usbp) {
+
+ (void)usbp;
+
+ osalSysLockFromISR();
+ sduSOFHookI(&SDU2);
+ osalSysUnlockFromISR();
+}
+
+/*
* USB driver configuration.
*/
const USBConfig usbcfg = {
usb_event,
get_descriptor,
sduRequestsHook,
- NULL
+ sof_handler
};
/*
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.h index 2ffaa17..d23b83c 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/usbcfg.h @@ -1,5 +1,5 @@ /*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -14,12 +14,13 @@ limitations under the License.
*/
-#ifndef _USBCFG_H_
-#define _USBCFG_H_
+#ifndef USBCFG_H
+#define USBCFG_H
extern const USBConfig usbcfg;
extern SerialUSBConfig serusbcfg;
+extern SerialUSBDriver SDU2;
-#endif /* _USBCFG_H_ */
+#endif /* USBCFG_H */
/** @} */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h index cf1289f..2e8b241 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef _HALCONF_COMMUNITY_H_ -#define _HALCONF_COMMUNITY_H_ +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H /** * @brief Enables the community overlay. @@ -66,7 +66,6 @@ #define HAL_USE_RNG FALSE #endif - /*===========================================================================*/ /* FSMCNAND driver related settings. */ /*===========================================================================*/ @@ -94,6 +93,6 @@ */ #define ONEWIRE_USE_SEARCH_ROM TRUE -#endif /* _HALCONF_COMMUNITY_H_ */ +#endif /* HALCONF_COMMUNITY_H */ /** @} */ diff --git a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/.cproject b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/.cproject index 109f8d7..2a64a93 100644 --- a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/.cproject +++ b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/.cproject @@ -49,4 +49,5 @@ </scannerConfigBuildInfo> </storageModule> <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="refreshScope"/> </cproject> diff --git a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile index 322b39b..b393902 100644 --- a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile +++ b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/Makefile @@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no endif +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + # # Build global options ############################################################################## diff --git a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/mcuconf.h b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/mcuconf.h index 926cab1..b5e4213 100644 --- a/demos/TIVA/RT-TM4C123G-LAUNCHPAD/mcuconf.h +++ b/demos/TIVA/RT-TM4C123G-LAUNCHPAD/mcuconf.h @@ -30,15 +30,15 @@ /* * HAL driver system settings. */ -#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO #define TIVA_MOSC_ENABLE TRUE #define TIVA_DIV400_VALUE 1 #define TIVA_SYSDIV_VALUE 2 #define TIVA_USESYSDIV_ENABLE FALSE #define TIVA_SYSDIV2LSB_ENABLE FALSE #define TIVA_BYPASS_VALUE 0 -#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \ - TIVA_RCC_PWMDIV_8) +#define TIVA_PWM_FIELDS (SYSCTL_RCC_USEPWMDIV | \ + SYSCTL_RCC_PWMDIV_8) /* * GPIO driver system settings. diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.cproject b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.cproject index efeab1b..df70011 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.cproject +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/.cproject @@ -22,22 +22,79 @@ <tool id="org.eclipse.cdt.build.core.settings.holder.libs.2143276802" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/> <tool id="org.eclipse.cdt.build.core.settings.holder.1873650595" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder"> <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.890534880" name="Undefined Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> - <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/GPIOv1"/> - <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/UARTv1"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/osal/rt"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/various/lwip_bindings"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/various"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/ext/lwip/src/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C129x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/ports/common/ARMCMx"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/TM4C129x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/boards/TI_TM4C1294_LAUNCHPAD"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/ext/lwip/src/include/ipv4"/> + </option> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.symbols.1983692223" superClass="org.eclipse.cdt.build.core.settings.holder.undef.symbols" valueType="undefDefinedSymbols"> + <listOptionValue builtIn="false" value="THUMB_PRESENT"/> + <listOptionValue builtIn="false" value="CORTEX_USE_FPU"/> + <listOptionValue builtIn="false" value="THUMB_NO_INTERWORKING"/> </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1337802279" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> <tool id="org.eclipse.cdt.build.core.settings.holder.1707090075" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder"> <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.262251028" name="Undefined Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> - <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/GPIOv1"/> - <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/UARTv1"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/osal/rt"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/various/lwip_bindings"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/various"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/ext/lwip/src/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C129x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/ports/common/ARMCMx"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/TM4C129x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/boards/TI_TM4C1294_LAUNCHPAD"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/ext/lwip/src/include/ipv4"/> + </option> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.symbols.2109515488" superClass="org.eclipse.cdt.build.core.settings.holder.undef.symbols" valueType="undefDefinedSymbols"> + <listOptionValue builtIn="false" value="THUMB_PRESENT"/> + <listOptionValue builtIn="false" value="CORTEX_USE_FPU"/> + <listOptionValue builtIn="false" value="THUMB_NO_INTERWORKING"/> </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.338985256" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> <tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder"> <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.757265410" name="Undefined Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> - <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/GPIOv1"/> - <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios/os/hal/ports/TIVA/LLD/UARTv1"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/osal/rt"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/various/lwip_bindings"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/various"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/ext/lwip/src/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C129x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/hal/ports/common/ARMCMx"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/TM4C129x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/ports/TIVA/LLD"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/hal/boards/TI_TM4C1294_LAUNCHPAD"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/ext/lwip/src/include/ipv4"/> + </option> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.symbols.919242008" superClass="org.eclipse.cdt.build.core.settings.holder.undef.symbols" valueType="undefDefinedSymbols"> + <listOptionValue builtIn="false" value="THUMB_PRESENT"/> + <listOptionValue builtIn="false" value="CORTEX_USE_FPU"/> + <listOptionValue builtIn="false" value="THUMB_NO_INTERWORKING"/> </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile index e5cd47a..add92f1 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/Makefile @@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no endif +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + # # Build global options ############################################################################## diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h index 3abab92..c3e5921 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD-LWIP/mcuconf.h @@ -31,7 +31,7 @@ * HAL driver system settings. */ #define TIVA_MOSC_SINGLE_ENDED FALSE -#define TIVA_RSCLKCFG_OSCSRC RSCLKCFG_OSCSRC_MOSC +#define TIVA_RSCLKCFG_OSCSRC SYSCTL_RSCLKCFG_OSCSRC_MOSC /* * GPT driver system settings. diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/.cproject b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/.cproject index dff1605..989853d 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/.cproject +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/.cproject @@ -21,12 +21,159 @@ <builder autoBuildTarget="all" cleanBuildTarget="clean" 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value="THUMB_NO_INTERWORKING"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> </toolChain> diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile index 63815df..2542d28 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/Makefile @@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no endif +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + # # Build global options ############################################################################## diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/debug/RT-TM4C1294-LAUNCHPAD-LWIP (OpenOCD, Flash and Run).launch b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/debug/RT-TM4C1294-LAUNCHPAD (OpenOCD, Flash and Run).launch index c9016ed..597e58d 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/debug/RT-TM4C1294-LAUNCHPAD-LWIP (OpenOCD, Flash and Run).launch +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/debug/RT-TM4C1294-LAUNCHPAD (OpenOCD, Flash and Run).launch @@ -37,11 +37,11 @@ <stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/> <stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/> <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/> -<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-TM4C1294-LAUNCHPAD-LWIP"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-TM4C1294-LAUNCHPAD"/> <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.114656749"/> <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> -<listEntry value="/RT-TM4C1294-LAUNCHPAD-LWIP"/> +<listEntry value="/RT-TM4C1294-LAUNCHPAD"/> </listAttribute> <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> <listEntry value="4"/> diff --git a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h index 3abab92..c3e5921 100644 --- a/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h +++ b/demos/TIVA/RT-TM4C1294-LAUNCHPAD/mcuconf.h @@ -31,7 +31,7 @@ * HAL driver system settings. */ #define TIVA_MOSC_SINGLE_ENDED FALSE -#define TIVA_RSCLKCFG_OSCSRC RSCLKCFG_OSCSRC_MOSC +#define TIVA_RSCLKCFG_OSCSRC SYSCTL_RSCLKCFG_OSCSRC_MOSC /* * GPT driver system settings. diff --git a/os/common/ext/TivaWare/inc/asmdefs.h b/os/common/ext/TivaWare/inc/asmdefs.h new file mode 100644 index 0000000..062cb09 --- /dev/null +++ b/os/common/ext/TivaWare/inc/asmdefs.h @@ -0,0 +1,227 @@ +//***************************************************************************** +// +// asmdefs.h - Macros to allow assembly code be portable among toolchains. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for code_red. +// +//***************************************************************************** +#ifdef codered + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // codered + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef ewarm + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler nmenonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // ewarm + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(gcc) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // gcc + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#ifdef rvmdk + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler nmenonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // rvmdk + +//***************************************************************************** +// +// The defines required for Sourcery G++. +// +//***************************************************************************** +#if defined(sourcerygxx) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // sourcerygxx + +#endif // __ASMDEF_H__ diff --git a/os/common/ext/TivaWare/inc/hw_adc.h b/os/common/ext/TivaWare/inc/hw_adc.h new file mode 100644 index 0000000..27a384f --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_adc.h @@ -0,0 +1,1306 @@ +//***************************************************************************** +// +// hw_adc.h - Macros used when accessing the ADC hardware. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following are defines for the ADC register offsets. +// +//***************************************************************************** +#define ADC_O_ACTSS 0x00000000 // ADC Active Sample Sequencer +#define ADC_O_RIS 0x00000004 // ADC Raw Interrupt Status +#define ADC_O_IM 0x00000008 // ADC Interrupt Mask +#define ADC_O_ISC 0x0000000C // ADC Interrupt Status and Clear +#define ADC_O_OSTAT 0x00000010 // ADC Overflow Status +#define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select +#define ADC_O_USTAT 0x00000018 // ADC Underflow Status +#define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select +#define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority +#define ADC_O_SPC 0x00000024 // ADC Sample Phase Control +#define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence + // Initiate +#define ADC_O_SAC 0x00000030 // ADC Sample Averaging Control +#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt + // Status and Clear +#define ADC_O_CTL 0x00000038 // ADC Control +#define ADC_O_SSMUX0 0x00000040 // ADC Sample Sequence Input + // Multiplexer Select 0 +#define ADC_O_SSCTL0 0x00000044 // ADC Sample Sequence Control 0 +#define ADC_O_SSFIFO0 0x00000048 // ADC Sample Sequence Result FIFO + // 0 +#define ADC_O_SSFSTAT0 0x0000004C // ADC Sample Sequence FIFO 0 + // Status +#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation +#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital + // Comparator Select +#define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended + // Input Multiplexer Select 0 +#define ADC_O_SSTSH0 0x0000005C // ADC Sample Sequence 0 Sample and + // Hold Time +#define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input + // Multiplexer Select 1 +#define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1 +#define ADC_O_SSFIFO1 0x00000068 // ADC Sample Sequence Result FIFO + // 1 +#define ADC_O_SSFSTAT1 0x0000006C // ADC Sample Sequence FIFO 1 + // Status +#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation +#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital + // Comparator Select +#define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended + // Input Multiplexer Select 1 +#define ADC_O_SSTSH1 0x0000007C // ADC Sample Sequence 1 Sample and + // Hold Time +#define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input + // Multiplexer Select 2 +#define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2 +#define ADC_O_SSFIFO2 0x00000088 // ADC Sample Sequence Result FIFO + // 2 +#define ADC_O_SSFSTAT2 0x0000008C // ADC Sample Sequence FIFO 2 + // Status +#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation +#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital + // Comparator Select +#define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended + // Input Multiplexer Select 2 +#define ADC_O_SSTSH2 0x0000009C // ADC Sample Sequence 2 Sample and + // Hold Time +#define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input + // Multiplexer Select 3 +#define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3 +#define ADC_O_SSFIFO3 0x000000A8 // ADC Sample Sequence Result FIFO + // 3 +#define ADC_O_SSFSTAT3 0x000000AC // ADC Sample Sequence FIFO 3 + // Status +#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation +#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital + // Comparator Select +#define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended + // Input Multiplexer Select 3 +#define ADC_O_SSTSH3 0x000000BC // ADC Sample Sequence 3 Sample and + // Hold Time +#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset + // Initial Conditions +#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0 +#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1 +#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2 +#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3 +#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4 +#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5 +#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6 +#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7 +#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0 +#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1 +#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2 +#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3 +#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4 +#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5 +#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6 +#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7 +#define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties +#define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration +#define ADC_O_CC 0x00000FC8 // ADC Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_BUSY 0x00010000 // ADC Busy +#define ADC_ACTSS_ADEN3 0x00000800 // ADC SS3 DMA Enable +#define ADC_ACTSS_ADEN2 0x00000400 // ADC SS2 DMA Enable +#define ADC_ACTSS_ADEN1 0x00000200 // ADC SS1 DMA Enable +#define ADC_ACTSS_ADEN0 0x00000100 // ADC SS1 DMA Enable +#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable +#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable +#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable +#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt + // Status +#define ADC_RIS_DMAINR3 0x00000800 // SS3 DMA Raw Interrupt Status +#define ADC_RIS_DMAINR2 0x00000400 // SS2 DMA Raw Interrupt Status +#define ADC_RIS_DMAINR1 0x00000200 // SS1 DMA Raw Interrupt Status +#define ADC_RIS_DMAINR0 0x00000100 // SS0 DMA Raw Interrupt Status +#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status +#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status +#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status +#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_IM register. +// +//***************************************************************************** +#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on + // SS3 +#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on + // SS2 +#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on + // SS1 +#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on + // SS0 +#define ADC_IM_DMAMASK3 0x00000800 // SS3 DMA Interrupt Mask +#define ADC_IM_DMAMASK2 0x00000400 // SS2 DMA Interrupt Mask +#define ADC_IM_DMAMASK1 0x00000200 // SS1 DMA Interrupt Mask +#define ADC_IM_DMAMASK0 0x00000100 // SS0 DMA Interrupt Mask +#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask +#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask +#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask +#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ISC register. +// +//***************************************************************************** +#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt + // Status on SS3 +#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt + // Status on SS2 +#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt + // Status on SS1 +#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt + // Status on SS0 +#define ADC_ISC_DMAIN3 0x00000800 // SS3 DMA Interrupt Status and + // Clear +#define ADC_ISC_DMAIN2 0x00000400 // SS2 DMA Interrupt Status and + // Clear +#define ADC_ISC_DMAIN1 0x00000200 // SS1 DMA Interrupt Status and + // Clear +#define ADC_ISC_DMAIN0 0x00000100 // SS0 DMA Interrupt Status and + // Clear +#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear +#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear +#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear +#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow +#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow +#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow +#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 +#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2 +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO Pins) +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM generator 0 +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM generator 1 +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM generator 2 +#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM generator 3 +#define ADC_EMUX_EM3_NEVER 0x0000E000 // Never Trigger +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) +#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 +#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2 +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO Pins) +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM generator 0 +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM generator 1 +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM generator 2 +#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM generator 3 +#define ADC_EMUX_EM2_NEVER 0x00000E00 // Never Trigger +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) +#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 +#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2 +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO Pins) +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM generator 0 +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM generator 1 +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM generator 2 +#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM generator 3 +#define ADC_EMUX_EM1_NEVER 0x000000E0 // Never Trigger +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) +#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 +#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2 +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO Pins) +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM generator 0 +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM generator 1 +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM generator 2 +#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM generator 3 +#define ADC_EMUX_EM0_NEVER 0x0000000E // Never Trigger +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow +#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow +#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow +#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_TSSEL register. +// +//***************************************************************************** +#define ADC_TSSEL_PS3_M 0x30000000 // Generator 3 PWM Module Trigger + // Select +#define ADC_TSSEL_PS3_0 0x00000000 // Use Generator 3 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS3_1 0x10000000 // Use Generator 3 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS2_M 0x00300000 // Generator 2 PWM Module Trigger + // Select +#define ADC_TSSEL_PS2_0 0x00000000 // Use Generator 2 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS2_1 0x00100000 // Use Generator 2 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS1_M 0x00003000 // Generator 1 PWM Module Trigger + // Select +#define ADC_TSSEL_PS1_0 0x00000000 // Use Generator 1 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS1_1 0x00001000 // Use Generator 1 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS0_M 0x00000030 // Generator 0 PWM Module Trigger + // Select +#define ADC_TSSEL_PS0_0 0x00000000 // Use Generator 0 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS0_1 0x00000010 // Use Generator 0 (and its + // trigger) in PWM module 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority +#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority +#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority +#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SPC register. +// +//***************************************************************************** +#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference +#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 +#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 +#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 +#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 +#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 +#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 +#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 +#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 +#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 +#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 +#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 +#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 +#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 +#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 +#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 +#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize +#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait +#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate +#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate +#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate +#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCISC register. +// +//***************************************************************************** +#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt + // Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CTL register. +// +//***************************************************************************** +#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select +#define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage + // references +#define ADC_CTL_VREF_EXT_3V 0x00000001 // The external VREFA+ and VREFA- + // inputs are the voltage + // references + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX0 register. +// +//***************************************************************************** +#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select +#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select +#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select +#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select +#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX0_MUX7_S 28 +#define ADC_SSMUX0_MUX6_S 24 +#define ADC_SSMUX0_MUX5_S 20 +#define ADC_SSMUX0_MUX4_S 16 +#define ADC_SSMUX0_MUX3_S 12 +#define ADC_SSMUX0_MUX2_S 8 +#define ADC_SSMUX0_MUX1_S 4 +#define ADC_SSMUX0_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL0 register. +// +//***************************************************************************** +#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select +#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable +#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence +#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Differential Input + // Select +#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select +#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable +#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence +#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Differential Input + // Select +#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select +#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable +#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence +#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Differential Input + // Select +#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select +#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable +#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence +#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Differential Input + // Select +#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. +// +//***************************************************************************** +#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. +// +//***************************************************************************** +#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT0_HPTR_S 4 +#define ADC_SSFSTAT0_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP0 register. +// +//***************************************************************************** +#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator + // Operation +#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator + // Operation +#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator + // Operation +#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator + // Operation +#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC0 register. +// +//***************************************************************************** +#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator + // Select +#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator + // Select +#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator + // Select +#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_S 24 +#define ADC_SSDC0_S5DCSEL_S 20 +#define ADC_SSDC0_S4DCSEL_S 16 +#define ADC_SSDC0_S3DCSEL_S 12 +#define ADC_SSDC0_S2DCSEL_S 8 +#define ADC_SSDC0_S1DCSEL_S 4 +#define ADC_SSDC0_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX0 register. +// +//***************************************************************************** +#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSTSH0 register. +// +//***************************************************************************** +#define ADC_SSTSH0_TSH7_M 0xF0000000 // 8th Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH6_M 0x0F000000 // 7th Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH5_M 0x00F00000 // 6th Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH4_M 0x000F0000 // 5th Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH3_M 0x0000F000 // 4th Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH2_M 0x00000F00 // 3rd Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH1_M 0x000000F0 // 2nd Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH0_M 0x0000000F // 1st Sample and Hold Period + // Select +#define ADC_SSTSH0_TSH7_S 28 +#define ADC_SSTSH0_TSH6_S 24 +#define ADC_SSTSH0_TSH5_S 20 +#define ADC_SSTSH0_TSH4_S 16 +#define ADC_SSTSH0_TSH3_S 12 +#define ADC_SSTSH0_TSH2_S 8 +#define ADC_SSTSH0_TSH1_S 4 +#define ADC_SSTSH0_TSH0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX1 register. +// +//***************************************************************************** +#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX1_MUX3_S 12 +#define ADC_SSMUX1_MUX2_S 8 +#define ADC_SSMUX1_MUX1_S 4 +#define ADC_SSMUX1_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL1 register. +// +//***************************************************************************** +#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. +// +//***************************************************************************** +#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. +// +//***************************************************************************** +#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT1_HPTR_S 4 +#define ADC_SSFSTAT1_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP1 register. +// +//***************************************************************************** +#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC1 register. +// +//***************************************************************************** +#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_S 8 +#define ADC_SSDC1_S1DCSEL_S 4 +#define ADC_SSDC1_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX1 register. +// +//***************************************************************************** +#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSTSH1 register. +// +//***************************************************************************** +#define ADC_SSTSH1_TSH3_M 0x0000F000 // 4th Sample and Hold Period + // Select +#define ADC_SSTSH1_TSH2_M 0x00000F00 // 3rd Sample and Hold Period + // Select +#define ADC_SSTSH1_TSH1_M 0x000000F0 // 2nd Sample and Hold Period + // Select +#define ADC_SSTSH1_TSH0_M 0x0000000F // 1st Sample and Hold Period + // Select +#define ADC_SSTSH1_TSH3_S 12 +#define ADC_SSTSH1_TSH2_S 8 +#define ADC_SSTSH1_TSH1_S 4 +#define ADC_SSTSH1_TSH0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX2 register. +// +//***************************************************************************** +#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX2_MUX3_S 12 +#define ADC_SSMUX2_MUX2_S 8 +#define ADC_SSMUX2_MUX1_S 4 +#define ADC_SSMUX2_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL2 register. +// +//***************************************************************************** +#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. +// +//***************************************************************************** +#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. +// +//***************************************************************************** +#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT2_HPTR_S 4 +#define ADC_SSFSTAT2_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP2 register. +// +//***************************************************************************** +#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC2 register. +// +//***************************************************************************** +#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_S 8 +#define ADC_SSDC2_S1DCSEL_S 4 +#define ADC_SSDC2_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX2 register. +// +//***************************************************************************** +#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper + // Bit) +#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSTSH2 register. +// +//***************************************************************************** +#define ADC_SSTSH2_TSH3_M 0x0000F000 // 4th Sample and Hold Period + // Select +#define ADC_SSTSH2_TSH2_M 0x00000F00 // 3rd Sample and Hold Period + // Select +#define ADC_SSTSH2_TSH1_M 0x000000F0 // 2nd Sample and Hold Period + // Select +#define ADC_SSTSH2_TSH0_M 0x0000000F // 1st Sample and Hold Period + // Select +#define ADC_SSTSH2_TSH3_S 12 +#define ADC_SSTSH2_TSH2_S 8 +#define ADC_SSTSH2_TSH1_S 4 +#define ADC_SSTSH2_TSH0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX3 register. +// +//***************************************************************************** +#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX3_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL3 register. +// +//***************************************************************************** +#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL3_IE0 0x00000004 // Sample Interrupt Enable +#define ADC_SSCTL3_END0 0x00000002 // End of Sequence +#define ADC_SSCTL3_D0 0x00000001 // Sample Differential Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. +// +//***************************************************************************** +#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. +// +//***************************************************************************** +#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT3_HPTR_S 4 +#define ADC_SSFSTAT3_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP3 register. +// +//***************************************************************************** +#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC3 register. +// +//***************************************************************************** +#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSEMUX3 register. +// +//***************************************************************************** +#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper + // Bit) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSTSH3 register. +// +//***************************************************************************** +#define ADC_SSTSH3_TSH0_M 0x0000000F // 1st Sample and Hold Period + // Select +#define ADC_SSTSH3_TSH0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCRIC register. +// +//***************************************************************************** +#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 +#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 +#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 +#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 +#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 +#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 +#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 +#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 +#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 +#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 +#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 +#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 +#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 +#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 +#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 +#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL0 register. +// +//***************************************************************************** +#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL1 register. +// +//***************************************************************************** +#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL2 register. +// +//***************************************************************************** +#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL3 register. +// +//***************************************************************************** +#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL4 register. +// +//***************************************************************************** +#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL5 register. +// +//***************************************************************************** +#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL6 register. +// +//***************************************************************************** +#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL7 register. +// +//***************************************************************************** +#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP0 register. +// +//***************************************************************************** +#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP0_COMP1_S 16 +#define ADC_DCCMP0_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP1 register. +// +//***************************************************************************** +#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP1_COMP1_S 16 +#define ADC_DCCMP1_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP2 register. +// +//***************************************************************************** +#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP2_COMP1_S 16 +#define ADC_DCCMP2_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP3 register. +// +//***************************************************************************** +#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP3_COMP1_S 16 +#define ADC_DCCMP3_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP4 register. +// +//***************************************************************************** +#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP4_COMP1_S 16 +#define ADC_DCCMP4_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP5 register. +// +//***************************************************************************** +#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP5_COMP1_S 16 +#define ADC_DCCMP5_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP6 register. +// +//***************************************************************************** +#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP6_COMP1_S 16 +#define ADC_DCCMP6_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP7 register. +// +//***************************************************************************** +#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP7_COMP1_S 16 +#define ADC_DCCMP7_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PP register. +// +//***************************************************************************** +#define ADC_PP_APSHT 0x01000000 // Application-Programmable + // Sample-and-Hold Time +#define ADC_PP_TS 0x00800000 // Temperature Sensor +#define ADC_PP_RSL_M 0x007C0000 // Resolution +#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture +#define ADC_PP_TYPE_SAR 0x00000000 // SAR +#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count +#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count +#define ADC_PP_MCR_M 0x0000000F // Maximum Conversion Rate +#define ADC_PP_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as + // defined by TADC and NSH +#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate +#define ADC_PP_MSR_125K 0x00000001 // 125 ksps +#define ADC_PP_MSR_250K 0x00000003 // 250 ksps +#define ADC_PP_MSR_500K 0x00000005 // 500 ksps +#define ADC_PP_MSR_1M 0x00000007 // 1 Msps +#define ADC_PP_RSL_S 18 +#define ADC_PP_DC_S 10 +#define ADC_PP_CH_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PC register. +// +//***************************************************************************** +#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate +#define ADC_PC_SR_125K 0x00000001 // 125 ksps +#define ADC_PC_SR_250K 0x00000003 // 250 ksps +#define ADC_PC_SR_500K 0x00000005 // 500 ksps +#define ADC_PC_SR_1M 0x00000007 // 1 Msps +#define ADC_PC_MCR_M 0x0000000F // Conversion Rate +#define ADC_PC_MCR_1_8 0x00000001 // Eighth conversion rate. After a + // conversion completes, the logic + // pauses for 112 TADC periods + // before starting the next + // conversion +#define ADC_PC_MCR_1_4 0x00000003 // Quarter conversion rate. After a + // conversion completes, the logic + // pauses for 48 TADC periods + // before starting the next + // conversion +#define ADC_PC_MCR_1_2 0x00000005 // Half conversion rate. After a + // conversion completes, the logic + // pauses for 16 TADC periods + // before starting the next + // conversion +#define ADC_PC_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as + // defined by TADC and NSH + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CC register. +// +//***************************************************************************** +#define ADC_CC_CLKDIV_M 0x000003F0 // PLL VCO Clock Divisor +#define ADC_CC_CS_M 0x0000000F // ADC Clock Source +#define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV +#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC +#define ADC_CC_CS_MOSC 0x00000002 // MOSC +#define ADC_CC_CLKDIV_S 4 + +#endif // __HW_ADC_H__ diff --git a/os/common/ext/TivaWare/inc/hw_aes.h b/os/common/ext/TivaWare/inc/hw_aes.h new file mode 100644 index 0000000..49dda1e --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_aes.h @@ -0,0 +1,545 @@ +//***************************************************************************** +// +// hw_aes.h - Macros used when accessing the AES hardware. +// +// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_AES_H__ +#define __HW_AES_H__ + +//***************************************************************************** +// +// The following are defines for the AES register offsets. +// +//***************************************************************************** +#define AES_O_KEY2_6 0x00000000 // AES Key 2_6 +#define AES_O_KEY2_7 0x00000004 // AES Key 2_7 +#define AES_O_KEY2_4 0x00000008 // AES Key 2_4 +#define AES_O_KEY2_5 0x0000000C // AES Key 2_5 +#define AES_O_KEY2_2 0x00000010 // AES Key 2_2 +#define AES_O_KEY2_3 0x00000014 // AES Key 2_3 +#define AES_O_KEY2_0 0x00000018 // AES Key 2_0 +#define AES_O_KEY2_1 0x0000001C // AES Key 2_1 +#define AES_O_KEY1_6 0x00000020 // AES Key 1_6 +#define AES_O_KEY1_7 0x00000024 // AES Key 1_7 +#define AES_O_KEY1_4 0x00000028 // AES Key 1_4 +#define AES_O_KEY1_5 0x0000002C // AES Key 1_5 +#define AES_O_KEY1_2 0x00000030 // AES Key 1_2 +#define AES_O_KEY1_3 0x00000034 // AES Key 1_3 +#define AES_O_KEY1_0 0x00000038 // AES Key 1_0 +#define AES_O_KEY1_1 0x0000003C // AES Key 1_1 +#define AES_O_IV_IN_0 0x00000040 // AES Initialization Vector Input + // 0 +#define AES_O_IV_IN_1 0x00000044 // AES Initialization Vector Input + // 1 +#define AES_O_IV_IN_2 0x00000048 // AES Initialization Vector Input + // 2 +#define AES_O_IV_IN_3 0x0000004C // AES Initialization Vector Input + // 3 +#define AES_O_CTRL 0x00000050 // AES Control +#define AES_O_C_LENGTH_0 0x00000054 // AES Crypto Data Length 0 +#define AES_O_C_LENGTH_1 0x00000058 // AES Crypto Data Length 1 +#define AES_O_AUTH_LENGTH 0x0000005C // AES Authentication Data Length +#define AES_O_DATA_IN_0 0x00000060 // AES Data RW Plaintext/Ciphertext + // 0 +#define AES_O_DATA_IN_1 0x00000064 // AES Data RW Plaintext/Ciphertext + // 1 +#define AES_O_DATA_IN_2 0x00000068 // AES Data RW Plaintext/Ciphertext + // 2 +#define AES_O_DATA_IN_3 0x0000006C // AES Data RW Plaintext/Ciphertext + // 3 +#define AES_O_TAG_OUT_0 0x00000070 // AES Hash Tag Out 0 +#define AES_O_TAG_OUT_1 0x00000074 // AES Hash Tag Out 1 +#define AES_O_TAG_OUT_2 0x00000078 // AES Hash Tag Out 2 +#define AES_O_TAG_OUT_3 0x0000007C // AES Hash Tag Out 3 +#define AES_O_REVISION 0x00000080 // AES IP Revision Identifier +#define AES_O_SYSCONFIG 0x00000084 // AES System Configuration +#define AES_O_SYSSTATUS 0x00000088 // AES System Status +#define AES_O_IRQSTATUS 0x0000008C // AES Interrupt Status +#define AES_O_IRQENABLE 0x00000090 // AES Interrupt Enable +#define AES_O_DIRTYBITS 0x00000094 // AES Dirty Bits +#define AES_O_DMAIM 0xFFFFA020 // AES DMA Interrupt Mask +#define AES_O_DMARIS 0xFFFFA024 // AES DMA Raw Interrupt Status +#define AES_O_DMAMIS 0xFFFFA028 // AES DMA Masked Interrupt Status +#define AES_O_DMAIC 0xFFFFA02C // AES DMA Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_6 register. +// +//***************************************************************************** +#define AES_KEY2_6_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_6_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_7 register. +// +//***************************************************************************** +#define AES_KEY2_7_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_7_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_4 register. +// +//***************************************************************************** +#define AES_KEY2_4_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_4_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_5 register. +// +//***************************************************************************** +#define AES_KEY2_5_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_5_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_2 register. +// +//***************************************************************************** +#define AES_KEY2_2_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_2_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_3 register. +// +//***************************************************************************** +#define AES_KEY2_3_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_3_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_0 register. +// +//***************************************************************************** +#define AES_KEY2_0_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_0_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_1 register. +// +//***************************************************************************** +#define AES_KEY2_1_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY2_1_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_6 register. +// +//***************************************************************************** +#define AES_KEY1_6_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_6_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_7 register. +// +//***************************************************************************** +#define AES_KEY1_7_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_7_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_4 register. +// +//***************************************************************************** +#define AES_KEY1_4_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_4_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_5 register. +// +//***************************************************************************** +#define AES_KEY1_5_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_5_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_2 register. +// +//***************************************************************************** +#define AES_KEY1_2_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_2_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_3 register. +// +//***************************************************************************** +#define AES_KEY1_3_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_3_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_0 register. +// +//***************************************************************************** +#define AES_KEY1_0_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_0_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_1 register. +// +//***************************************************************************** +#define AES_KEY1_1_KEY_M 0xFFFFFFFF // Key Data +#define AES_KEY1_1_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_0 register. +// +//***************************************************************************** +#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // Initialization Vector Input +#define AES_IV_IN_0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_1 register. +// +//***************************************************************************** +#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // Initialization Vector Input +#define AES_IV_IN_1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_2 register. +// +//***************************************************************************** +#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // Initialization Vector Input +#define AES_IV_IN_2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_3 register. +// +//***************************************************************************** +#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // Initialization Vector Input +#define AES_IV_IN_3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_CTRL register. +// +//***************************************************************************** +#define AES_CTRL_CTXTRDY 0x80000000 // Context Data Registers Ready +#define AES_CTRL_SVCTXTRDY 0x40000000 // AES TAG/IV Block(s) Ready +#define AES_CTRL_SAVE_CONTEXT 0x20000000 // TAG or Result IV Save +#define AES_CTRL_CCM_M_M 0x01C00000 // Counter with CBC-MAC (CCM) +#define AES_CTRL_CCM_L_M 0x00380000 // L Value +#define AES_CTRL_CCM_L_2 0x00080000 // width = 2 +#define AES_CTRL_CCM_L_4 0x00180000 // width = 4 +#define AES_CTRL_CCM_L_8 0x00380000 // width = 8 +#define AES_CTRL_CCM 0x00040000 // AES-CCM Mode Enable +#define AES_CTRL_GCM_M 0x00030000 // AES-GCM Mode Enable +#define AES_CTRL_GCM_NOP 0x00000000 // No operation +#define AES_CTRL_GCM_HLY0ZERO 0x00010000 // GHASH with H loaded and + // Y0-encrypted forced to zero +#define AES_CTRL_GCM_HLY0CALC 0x00020000 // GHASH with H loaded and + // Y0-encrypted calculated + // internally +#define AES_CTRL_GCM_HY0CALC 0x00030000 // Autonomous GHASH (both H and + // Y0-encrypted calculated + // internally) +#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC Enable +#define AES_CTRL_F9 0x00004000 // AES f9 Mode Enable +#define AES_CTRL_F8 0x00002000 // AES f8 Mode Enable +#define AES_CTRL_XTS_M 0x00001800 // AES-XTS Operation Enabled +#define AES_CTRL_XTS_NOP 0x00000000 // No operation +#define AES_CTRL_XTS_TWEAKJL 0x00000800 // Previous/intermediate tweak + // value and j loaded (value is + // loaded via IV, j is loaded via + // the AAD length register) +#define AES_CTRL_XTS_K2IJL 0x00001000 // Key2, n and j are loaded (n is + // loaded via IV, j is loaded via + // the AAD length register) +#define AES_CTRL_XTS_K2ILJ0 0x00001800 // Key2 and n are loaded; j=0 (n is + // loaded via IV) +#define AES_CTRL_CFB 0x00000400 // Full block AES cipher feedback + // mode (CFB128) Enable +#define AES_CTRL_ICM 0x00000200 // AES Integer Counter Mode (ICM) + // Enable +#define AES_CTRL_CTR_WIDTH_M 0x00000180 // AES-CTR Mode Counter Width +#define AES_CTRL_CTR_WIDTH_32 0x00000000 // Counter is 32 bits +#define AES_CTRL_CTR_WIDTH_64 0x00000080 // Counter is 64 bits +#define AES_CTRL_CTR_WIDTH_96 0x00000100 // Counter is 96 bits +#define AES_CTRL_CTR_WIDTH_128 0x00000180 // Counter is 128 bits +#define AES_CTRL_CTR 0x00000040 // Counter Mode +#define AES_CTRL_MODE 0x00000020 // ECB/CBC Mode +#define AES_CTRL_KEY_SIZE_M 0x00000018 // Key Size +#define AES_CTRL_KEY_SIZE_128 0x00000008 // Key is 128 bits +#define AES_CTRL_KEY_SIZE_192 0x00000010 // Key is 192 bits +#define AES_CTRL_KEY_SIZE_256 0x00000018 // Key is 256 bits +#define AES_CTRL_DIRECTION 0x00000004 // Encryption/Decryption Selection +#define AES_CTRL_INPUT_READY 0x00000002 // Input Ready Status +#define AES_CTRL_OUTPUT_READY 0x00000001 // Output Ready Status +#define AES_CTRL_CCM_M_S 22 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_C_LENGTH_0 +// register. +// +//***************************************************************************** +#define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF // Data Length +#define AES_C_LENGTH_0_LENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_C_LENGTH_1 +// register. +// +//***************************************************************************** +#define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF // Data Length +#define AES_C_LENGTH_1_LENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_AUTH_LENGTH +// register. +// +//***************************************************************************** +#define AES_AUTH_LENGTH_AUTH_M 0xFFFFFFFF // Authentication Data Length +#define AES_AUTH_LENGTH_AUTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_0 +// register. +// +//***************************************************************************** +#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Secure Data RW + // Plaintext/Ciphertext +#define AES_DATA_IN_0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_1 +// register. +// +//***************************************************************************** +#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Secure Data RW + // Plaintext/Ciphertext +#define AES_DATA_IN_1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_2 +// register. +// +//***************************************************************************** +#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Secure Data RW + // Plaintext/Ciphertext +#define AES_DATA_IN_2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_3 +// register. +// +//***************************************************************************** +#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Secure Data RW + // Plaintext/Ciphertext +#define AES_DATA_IN_3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_0 +// register. +// +//***************************************************************************** +#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash Result +#define AES_TAG_OUT_0_HASH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_1 +// register. +// +//***************************************************************************** +#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash Result +#define AES_TAG_OUT_1_HASH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_2 +// register. +// +//***************************************************************************** +#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash Result +#define AES_TAG_OUT_2_HASH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_3 +// register. +// +//***************************************************************************** +#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash Result +#define AES_TAG_OUT_3_HASH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_REVISION register. +// +//***************************************************************************** +#define AES_REVISION_M 0xFFFFFFFF // Revision number +#define AES_REVISION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSCONFIG +// register. +// +//***************************************************************************** +#define AES_SYSCONFIG_K3 0x00001000 // K3 Select +#define AES_SYSCONFIG_KEYENC 0x00000800 // Key Encoding +#define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT \ + 0x00000200 // Map Context Out on Data Out + // Enable +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ + 0x00000100 // DMA Request Context Out Enable +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // DMA Request Context In Enable +#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // DMA Request Data Out Enable +#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // DMA Request Data In Enable +#define AES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSSTATUS +// register. +// +//***************************************************************************** +#define AES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQSTATUS +// register. +// +//***************************************************************************** +#define AES_IRQSTATUS_CONTEXT_OUT \ + 0x00000008 // Context Output Interrupt Status +#define AES_IRQSTATUS_DATA_OUT 0x00000004 // Data Out Interrupt Status +#define AES_IRQSTATUS_DATA_IN 0x00000002 // Data In Interrupt Status +#define AES_IRQSTATUS_CONTEXT_IN \ + 0x00000001 // Context In Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQENABLE +// register. +// +//***************************************************************************** +#define AES_IRQENABLE_CONTEXT_OUT \ + 0x00000008 // Context Out Interrupt Enable +#define AES_IRQENABLE_DATA_OUT 0x00000004 // Data Out Interrupt Enable +#define AES_IRQENABLE_DATA_IN 0x00000002 // Data In Interrupt Enable +#define AES_IRQENABLE_CONTEXT_IN \ + 0x00000001 // Context In Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DIRTYBITS +// register. +// +//***************************************************************************** +#define AES_DIRTYBITS_S_DIRTY 0x00000002 // AES Dirty Bit +#define AES_DIRTYBITS_S_ACCESS 0x00000001 // AES Access Bit + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DMAIM register. +// +//***************************************************************************** +#define AES_DMAIM_DOUT 0x00000008 // Data Out DMA Done Interrupt Mask +#define AES_DMAIM_DIN 0x00000004 // Data In DMA Done Interrupt Mask +#define AES_DMAIM_COUT 0x00000002 // Context Out DMA Done Interrupt + // Mask +#define AES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DMARIS register. +// +//***************************************************************************** +#define AES_DMARIS_DOUT 0x00000008 // Data Out DMA Done Raw Interrupt + // Status +#define AES_DMARIS_DIN 0x00000004 // Data In DMA Done Raw Interrupt + // Status +#define AES_DMARIS_COUT 0x00000002 // Context Out DMA Done Raw + // Interrupt Status +#define AES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DMAMIS register. +// +//***************************************************************************** +#define AES_DMAMIS_DOUT 0x00000008 // Data Out DMA Done Masked + // Interrupt Status +#define AES_DMAMIS_DIN 0x00000004 // Data In DMA Done Masked + // Interrupt Status +#define AES_DMAMIS_COUT 0x00000002 // Context Out DMA Done Masked + // Interrupt Status +#define AES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DMAIC register. +// +//***************************************************************************** +#define AES_DMAIC_DOUT 0x00000008 // Data Out DMA Done Interrupt + // Clear +#define AES_DMAIC_DIN 0x00000004 // Data In DMA Done Interrupt Clear +#define AES_DMAIC_COUT 0x00000002 // Context Out DMA Done Masked + // Interrupt Status +#define AES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +#endif // __HW_AES_H__ diff --git a/os/common/ext/TivaWare/inc/hw_can.h b/os/common/ext/TivaWare/inc/hw_can.h new file mode 100644 index 0000000..a683e67 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_can.h @@ -0,0 +1,462 @@ +//***************************************************************************** +// +// hw_can.h - Defines and macros used when accessing the CAN controllers. +// +// Copyright (c) 2006-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_CAN_H__ +#define __HW_CAN_H__ + +//***************************************************************************** +// +// The following are defines for the CAN register offsets. +// +//***************************************************************************** +#define CAN_O_CTL 0x00000000 // CAN Control +#define CAN_O_STS 0x00000004 // CAN Status +#define CAN_O_ERR 0x00000008 // CAN Error Counter +#define CAN_O_BIT 0x0000000C // CAN Bit Timing +#define CAN_O_INT 0x00000010 // CAN Interrupt +#define CAN_O_TST 0x00000014 // CAN Test +#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler + // Extension +#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request +#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask +#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1 +#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2 +#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1 +#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2 +#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control +#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1 +#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2 +#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1 +#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2 +#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request +#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask +#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1 +#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2 +#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1 +#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2 +#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control +#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1 +#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2 +#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1 +#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2 +#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1 +#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2 +#define CAN_O_NWDA1 0x00000120 // CAN New Data 1 +#define CAN_O_NWDA2 0x00000124 // CAN New Data 2 +#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending +#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending +#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid +#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_CTL register. +// +//***************************************************************************** +#define CAN_CTL_TEST 0x00000080 // Test Mode Enable +#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable +#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission +#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable +#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable +#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable +#define CAN_CTL_INIT 0x00000001 // Initialization + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_STS register. +// +//***************************************************************************** +#define CAN_STS_BOFF 0x00000080 // Bus-Off Status +#define CAN_STS_EWARN 0x00000040 // Warning Status +#define CAN_STS_EPASS 0x00000020 // Error Passive +#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully +#define CAN_STS_TXOK 0x00000008 // Transmitted a Message + // Successfully +#define CAN_STS_LEC_M 0x00000007 // Last Error Code +#define CAN_STS_LEC_NONE 0x00000000 // No Error +#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error +#define CAN_STS_LEC_FORM 0x00000002 // Format Error +#define CAN_STS_LEC_ACK 0x00000003 // ACK Error +#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error +#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error +#define CAN_STS_LEC_CRC 0x00000006 // CRC Error +#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_ERR register. +// +//***************************************************************************** +#define CAN_ERR_RP 0x00008000 // Received Error Passive +#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter +#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter +#define CAN_ERR_REC_S 8 +#define CAN_ERR_TEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BIT register. +// +//***************************************************************************** +#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point +#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point +#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width +#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler +#define CAN_BIT_TSEG2_S 12 +#define CAN_BIT_TSEG1_S 8 +#define CAN_BIT_SJW_S 6 +#define CAN_BIT_BRP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_INT register. +// +//***************************************************************************** +#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier +#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending +#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TST register. +// +//***************************************************************************** +#define CAN_TST_RX 0x00000080 // Receive Observation +#define CAN_TST_TX_M 0x00000060 // Transmit Control +#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control +#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point +#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low +#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High +#define CAN_TST_LBACK 0x00000010 // Loopback Mode +#define CAN_TST_SILENT 0x00000008 // Silent Mode +#define CAN_TST_BASIC 0x00000004 // Basic Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BRPE register. +// +//***************************************************************************** +#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension +#define CAN_BRPE_BRPE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CRQ register. +// +//***************************************************************************** +#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF1CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CMSK register. +// +//***************************************************************************** +#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. +// +//***************************************************************************** +#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF1MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. +// +//***************************************************************************** +#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF1MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. +// +//***************************************************************************** +#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF1ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. +// +//***************************************************************************** +#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF1ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MCTL register. +// +//***************************************************************************** +#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF1MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA1 register. +// +//***************************************************************************** +#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA2 register. +// +//***************************************************************************** +#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB1 register. +// +//***************************************************************************** +#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB2 register. +// +//***************************************************************************** +#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CRQ register. +// +//***************************************************************************** +#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF2CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CMSK register. +// +//***************************************************************************** +#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. +// +//***************************************************************************** +#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF2MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. +// +//***************************************************************************** +#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF2MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. +// +//***************************************************************************** +#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF2ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. +// +//***************************************************************************** +#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF2ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MCTL register. +// +//***************************************************************************** +#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF2MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA1 register. +// +//***************************************************************************** +#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA2 register. +// +//***************************************************************************** +#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB1 register. +// +//***************************************************************************** +#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB2 register. +// +//***************************************************************************** +#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ1 register. +// +//***************************************************************************** +#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ1_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ2 register. +// +//***************************************************************************** +#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ2_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA1 register. +// +//***************************************************************************** +#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA1_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA2 register. +// +//***************************************************************************** +#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA2_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1INT register. +// +//***************************************************************************** +#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG1INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2INT register. +// +//***************************************************************************** +#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG2INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1VAL register. +// +//***************************************************************************** +#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG1VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2VAL register. +// +//***************************************************************************** +#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG2VAL_MSGVAL_S 0 + +#endif // __HW_CAN_H__ diff --git a/os/common/ext/TivaWare/inc/hw_ccm.h b/os/common/ext/TivaWare/inc/hw_ccm.h new file mode 100644 index 0000000..19041b6 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_ccm.h @@ -0,0 +1,115 @@ +//***************************************************************************** +// +// hw_ccm.h - Macros used when accessing the CCM hardware. +// +// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_CCM_H__ +#define __HW_CCM_H__ + +//***************************************************************************** +// +// The following are defines for the EC register offsets. +// +//***************************************************************************** +#define CCM_O_CRCCTRL 0x00000400 // CRC Control +#define CCM_O_CRCSEED 0x00000410 // CRC SEED/Context +#define CCM_O_CRCDIN 0x00000414 // CRC Data Input +#define CCM_O_CRCRSLTPP 0x00000418 // CRC Post Processing Result + +//***************************************************************************** +// +// The following are defines for the bit fields in the CCM_O_CRCCTRL register. +// +//***************************************************************************** +#define CCM_CRCCTRL_INIT_M 0x00006000 // CRC Initialization +#define CCM_CRCCTRL_INIT_SEED 0x00000000 // Use the CRCSEED register context + // as the starting value +#define CCM_CRCCTRL_INIT_0 0x00004000 // Initialize to all '0s' +#define CCM_CRCCTRL_INIT_1 0x00006000 // Initialize to all '1s' +#define CCM_CRCCTRL_SIZE 0x00001000 // Input Data Size +#define CCM_CRCCTRL_RESINV 0x00000200 // Result Inverse Enable +#define CCM_CRCCTRL_OBR 0x00000100 // Output Reverse Enable +#define CCM_CRCCTRL_BR 0x00000080 // Bit reverse enable +#define CCM_CRCCTRL_ENDIAN_M 0x00000030 // Endian Control +#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000 // Configuration unchanged. (B3, + // B2, B1, B0) +#define CCM_CRCCTRL_ENDIAN_SHW 0x00000010 // Bytes are swapped in half-words + // but half-words are not swapped + // (B2, B3, B0, B1) +#define CCM_CRCCTRL_ENDIAN_SHWNB \ + 0x00000020 // Half-words are swapped but bytes + // are not swapped in half-word. + // (B1, B0, B3, B2) +#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030 // Bytes are swapped in half-words + // and half-words are swapped. (B0, + // B1, B2, B3) +#define CCM_CRCCTRL_TYPE_M 0x0000000F // Operation Type +#define CCM_CRCCTRL_TYPE_P8055 0x00000000 // Polynomial 0x8005 +#define CCM_CRCCTRL_TYPE_P1021 0x00000001 // Polynomial 0x1021 +#define CCM_CRCCTRL_TYPE_P4C11DB7 \ + 0x00000002 // Polynomial 0x4C11DB7 +#define CCM_CRCCTRL_TYPE_P1EDC6F41 \ + 0x00000003 // Polynomial 0x1EDC6F41 +#define CCM_CRCCTRL_TYPE_TCPCHKSUM \ + 0x00000008 // TCP checksum + +//***************************************************************************** +// +// The following are defines for the bit fields in the CCM_O_CRCSEED register. +// +//***************************************************************************** +#define CCM_CRCSEED_SEED_M 0xFFFFFFFF // SEED/Context Value +#define CCM_CRCSEED_SEED_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CCM_O_CRCDIN register. +// +//***************************************************************************** +#define CCM_CRCDIN_DATAIN_M 0xFFFFFFFF // Data Input +#define CCM_CRCDIN_DATAIN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CCM_O_CRCRSLTPP +// register. +// +//***************************************************************************** +#define CCM_CRCRSLTPP_RSLTPP_M 0xFFFFFFFF // Post Processing Result +#define CCM_CRCRSLTPP_RSLTPP_S 0 + +#endif // __HW_CCM_H__ diff --git a/os/common/ext/TivaWare/inc/hw_comp.h b/os/common/ext/TivaWare/inc/hw_comp.h new file mode 100644 index 0000000..aea2f84 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_comp.h @@ -0,0 +1,211 @@ +//***************************************************************************** +// +// hw_comp.h - Macros used when accessing the comparator hardware. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_COMP_H__ +#define __HW_COMP_H__ + +//***************************************************************************** +// +// The following are defines for the Comparator register offsets. +// +//***************************************************************************** +#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked + // Interrupt Status +#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt + // Status +#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt + // Enable +#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference + // Voltage Control +#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0 +#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0 +#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1 +#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1 +#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2 +#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2 +#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral + // Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACMIS register. +// +//***************************************************************************** +#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt + // Status +#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt + // Status +#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACRIS register. +// +//***************************************************************************** +#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status +#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status +#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACINTEN register. +// +//***************************************************************************** +#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable +#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable +#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACREFCTL +// register. +// +//***************************************************************************** +#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable +#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range +#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref +#define COMP_ACREFCTL_VREF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. +// +//***************************************************************************** +#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL0 register. +// +//***************************************************************************** +#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. +// +//***************************************************************************** +#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL1 register. +// +//***************************************************************************** +#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT2 register. +// +//***************************************************************************** +#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL2 register. +// +//***************************************************************************** +#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_PP register. +// +//***************************************************************************** +#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present +#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present +#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present +#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present +#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present +#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present + +#endif // __HW_COMP_H__ diff --git a/os/common/ext/TivaWare/inc/hw_des.h b/os/common/ext/TivaWare/inc/hw_des.h new file mode 100644 index 0000000..da46c52 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_des.h @@ -0,0 +1,310 @@ +//***************************************************************************** +// +// hw_des.h - Macros used when accessing the DES hardware. +// +// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_DES_H__ +#define __HW_DES_H__ + +//***************************************************************************** +// +// The following are defines for the DES register offsets. +// +//***************************************************************************** +#define DES_O_KEY3_L 0x00000000 // DES Key 3 LSW for 192-Bit Key +#define DES_O_KEY3_H 0x00000004 // DES Key 3 MSW for 192-Bit Key +#define DES_O_KEY2_L 0x00000008 // DES Key 2 LSW for 128-Bit Key +#define DES_O_KEY2_H 0x0000000C // DES Key 2 MSW for 128-Bit Key +#define DES_O_KEY1_L 0x00000010 // DES Key 1 LSW for 64-Bit Key +#define DES_O_KEY1_H 0x00000014 // DES Key 1 MSW for 64-Bit Key +#define DES_O_IV_L 0x00000018 // DES Initialization Vector +#define DES_O_IV_H 0x0000001C // DES Initialization Vector +#define DES_O_CTRL 0x00000020 // DES Control +#define DES_O_LENGTH 0x00000024 // DES Cryptographic Data Length +#define DES_O_DATA_L 0x00000028 // DES LSW Data RW +#define DES_O_DATA_H 0x0000002C // DES MSW Data RW +#define DES_O_REVISION 0x00000030 // DES Revision Number +#define DES_O_SYSCONFIG 0x00000034 // DES System Configuration +#define DES_O_SYSSTATUS 0x00000038 // DES System Status +#define DES_O_IRQSTATUS 0x0000003C // DES Interrupt Status +#define DES_O_IRQENABLE 0x00000040 // DES Interrupt Enable +#define DES_O_DIRTYBITS 0x00000044 // DES Dirty Bits +#define DES_O_DMAIM 0xFFFF8030 // DES DMA Interrupt Mask +#define DES_O_DMARIS 0xFFFF8034 // DES DMA Raw Interrupt Status +#define DES_O_DMAMIS 0xFFFF8038 // DES DMA Masked Interrupt Status +#define DES_O_DMAIC 0xFFFF803C // DES DMA Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_L register. +// +//***************************************************************************** +#define DES_KEY3_L_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY3_L_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_H register. +// +//***************************************************************************** +#define DES_KEY3_H_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY3_H_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_L register. +// +//***************************************************************************** +#define DES_KEY2_L_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY2_L_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_H register. +// +//***************************************************************************** +#define DES_KEY2_H_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY2_H_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_L register. +// +//***************************************************************************** +#define DES_KEY1_L_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY1_L_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_H register. +// +//***************************************************************************** +#define DES_KEY1_H_KEY_M 0xFFFFFFFF // Key Data +#define DES_KEY1_H_KEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_L register. +// +//***************************************************************************** +#define DES_IV_L_M 0xFFFFFFFF // Initialization vector for CBC, + // CFB modes (LSW) +#define DES_IV_L_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_H register. +// +//***************************************************************************** +#define DES_IV_H_M 0xFFFFFFFF // Initialization vector for CBC, + // CFB modes (MSW) +#define DES_IV_H_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_CTRL register. +// +//***************************************************************************** +#define DES_CTRL_CONTEXT 0x80000000 // If 1, this read-only status bit + // indicates that the context data + // registers can be overwritten and + // the host is permitted to write + // the next context +#define DES_CTRL_MODE_M 0x00000030 // Select CBC, ECB or CFB mode0x0: + // ECB mode0x1: CBC mode0x2: CFB + // mode0x3: reserved +#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES + // encryption/decryption +#define DES_CTRL_DIRECTION 0x00000004 // Select encryption/decryption + // 0x0: decryption is selected0x1: + // Encryption is selected +#define DES_CTRL_INPUT_READY 0x00000002 // When 1, ready to encrypt/decrypt + // data +#define DES_CTRL_OUTPUT_READY 0x00000001 // When 1, Data decrypted/encrypted + // ready +#define DES_CTRL_MODE_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_LENGTH register. +// +//***************************************************************************** +#define DES_LENGTH_M 0xFFFFFFFF // Cryptographic data length in + // bytes for all modes +#define DES_LENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_L register. +// +//***************************************************************************** +#define DES_DATA_L_M 0xFFFFFFFF // Data for encryption/decryption, + // LSW +#define DES_DATA_L_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_H register. +// +//***************************************************************************** +#define DES_DATA_H_M 0xFFFFFFFF // Data for encryption/decryption, + // MSW +#define DES_DATA_H_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_REVISION register. +// +//***************************************************************************** +#define DES_REVISION_M 0xFFFFFFFF // Revision number +#define DES_REVISION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSCONFIG +// register. +// +//***************************************************************************** +#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // DMA Request Context In Enable +#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // DMA Request Data Out Enable +#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // DMA Request Data In Enable +#define DES_SYSCONFIG_SIDLE_M 0x0000000C // Sidle mode +#define DES_SYSCONFIG_SIDLE_FORCE \ + 0x00000000 // Force-idle mode +#define DES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSSTATUS +// register. +// +//***************************************************************************** +#define DES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQSTATUS +// register. +// +//***************************************************************************** +#define DES_IRQSTATUS_DATA_OUT 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output +#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output +#define DES_IRQSTATUS_CONTEX_IN 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQENABLE +// register. +// +//***************************************************************************** +#define DES_IRQENABLE_M_DATA_OUT \ + 0x00000004 // If this bit is set to 1 the data + // output interrupt is enabled +#define DES_IRQENABLE_M_DATA_IN 0x00000002 // If this bit is set to 1 the data + // input interrupt is enabled +#define DES_IRQENABLE_M_CONTEX_IN \ + 0x00000001 // If this bit is set to 1 the + // context interrupt is enabled + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DIRTYBITS +// register. +// +//***************************************************************************** +#define DES_DIRTYBITS_S_DIRTY 0x00000002 // This bit is set to 1 by the + // module if any of the DES_* + // registers is written +#define DES_DIRTYBITS_S_ACCESS 0x00000001 // This bit is set to 1 by the + // module if any of the DES_* + // registers is read + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DMAIM register. +// +//***************************************************************************** +#define DES_DMAIM_DOUT 0x00000004 // Data Out DMA Done Interrupt Mask +#define DES_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask +#define DES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DMARIS register. +// +//***************************************************************************** +#define DES_DMARIS_DOUT 0x00000004 // Data Out DMA Done Raw Interrupt + // Status +#define DES_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt + // Status +#define DES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DMAMIS register. +// +//***************************************************************************** +#define DES_DMAMIS_DOUT 0x00000004 // Data Out DMA Done Masked + // Interrupt Status +#define DES_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked + // Interrupt Status +#define DES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DMAIC register. +// +//***************************************************************************** +#define DES_DMAIC_DOUT 0x00000004 // Data Out DMA Done Interrupt + // Clear +#define DES_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear +#define DES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +#endif // __HW_DES_H__ diff --git a/os/common/ext/TivaWare/inc/hw_eeprom.h b/os/common/ext/TivaWare/inc/hw_eeprom.h new file mode 100644 index 0000000..7ba282d --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_eeprom.h @@ -0,0 +1,251 @@ +//***************************************************************************** +// +// hw_eeprom.h - Macros used when accessing the EEPROM controller. +// +// Copyright (c) 2011-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_EEPROM_H__ +#define __HW_EEPROM_H__ + +//***************************************************************************** +// +// The following are defines for the EEPROM register offsets. +// +//***************************************************************************** +#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information +#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block +#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset +#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write +#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment +#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status +#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and + // Status +#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock +#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection +#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password +#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password +#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password +#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt +#define EEPROM_EEHIDE0 0x400AF050 // EEPROM Block Hide 0 +#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide +#define EEPROM_EEHIDE1 0x400AF054 // EEPROM Block Hide 1 +#define EEPROM_EEHIDE2 0x400AF058 // EEPROM Block Hide 2 +#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase +#define EEPROM_PP 0x400AFFC0 // EEPROM Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESIZE register. +// +//***************************************************************************** +#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words +#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks +#define EEPROM_EESIZE_WORDCNT_S 0 +#define EEPROM_EESIZE_BLKCNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEBLOCK register. +// +//***************************************************************************** +#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block +#define EEPROM_EEBLOCK_BLOCK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEOFFSET +// register. +// +//***************************************************************************** +#define EEPROM_EEOFFSET_OFFSET_M \ + 0x0000000F // Current Address Offset +#define EEPROM_EEOFFSET_OFFSET_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWR register. +// +//***************************************************************************** +#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data +#define EEPROM_EERDWR_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWRINC +// register. +// +//***************************************************************************** +#define EEPROM_EERDWRINC_VALUE_M \ + 0xFFFFFFFF // EEPROM Read or Write Data with + // Increment +#define EEPROM_EERDWRINC_VALUE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDONE register. +// +//***************************************************************************** +#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working +#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase +#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy +#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission +#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESUPP register. +// +//***************************************************************************** +#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried +#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEUNLOCK +// register. +// +//***************************************************************************** +#define EEPROM_EEUNLOCK_UNLOCK_M \ + 0xFFFFFFFF // EEPROM Unlock + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPROT register. +// +//***************************************************************************** +#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control +#define EEPROM_EEPROT_PROT_RWNPW \ + 0x00000000 // This setting is the default. If + // there is no password, the block + // is not protected and is readable + // and writable +#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the + // block is readable or writable + // only when unlocked +#define EEPROM_EEPROT_PROT_RONPW \ + 0x00000002 // If there is no password, the + // block is readable, not writable +#define EEPROM_EEPROT_ACC 0x00000008 // Access Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS0 register. +// +//***************************************************************************** +#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS0_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS1 register. +// +//***************************************************************************** +#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS1_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS2 register. +// +//***************************************************************************** +#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS2_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEINT register. +// +//***************************************************************************** +#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE0 register. +// +//***************************************************************************** +#define EEPROM_EEHIDE0_HN_M 0xFFFFFFFE // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE register. +// +//***************************************************************************** +#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE1 register. +// +//***************************************************************************** +#define EEPROM_EEHIDE1_HN_M 0xFFFFFFFF // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE2 register. +// +//***************************************************************************** +#define EEPROM_EEHIDE2_HN_M 0xFFFFFFFF // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDBGME register. +// +//***************************************************************************** +#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase +#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key +#define EEPROM_EEDBGME_KEY_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_PP register. +// +//***************************************************************************** +#define EEPROM_PP_SIZE_M 0x0000FFFF // EEPROM Size +#define EEPROM_PP_SIZE_64 0x00000000 // 64 bytes of EEPROM +#define EEPROM_PP_SIZE_128 0x00000001 // 128 bytes of EEPROM +#define EEPROM_PP_SIZE_256 0x00000003 // 256 bytes of EEPROM +#define EEPROM_PP_SIZE_512 0x00000007 // 512 bytes of EEPROM +#define EEPROM_PP_SIZE_1K 0x0000000F // 1 KB of EEPROM +#define EEPROM_PP_SIZE_2K 0x0000001F // 2 KB of EEPROM +#define EEPROM_PP_SIZE_3K 0x0000003F // 3 KB of EEPROM +#define EEPROM_PP_SIZE_4K 0x0000007F // 4 KB of EEPROM +#define EEPROM_PP_SIZE_5K 0x000000FF // 5 KB of EEPROM +#define EEPROM_PP_SIZE_6K 0x000001FF // 6 KB of EEPROM +#define EEPROM_PP_SIZE_S 0 + +#endif // __HW_EEPROM_H__ diff --git a/os/common/ext/TivaWare/inc/hw_emac.h b/os/common/ext/TivaWare/inc/hw_emac.h new file mode 100644 index 0000000..67cb03e --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_emac.h @@ -0,0 +1,1839 @@ +//***************************************************************************** +// +// hw_emac.h - Macros used when accessing the EMAC hardware. +// +// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_EMAC_H__ +#define __HW_EMAC_H__ + +//***************************************************************************** +// +// The following are defines for the EMAC register offsets. +// +//***************************************************************************** +#define EMAC_O_CFG 0x00000000 // Ethernet MAC Configuration +#define EMAC_O_FRAMEFLTR 0x00000004 // Ethernet MAC Frame Filter +#define EMAC_O_HASHTBLH 0x00000008 // Ethernet MAC Hash Table High +#define EMAC_O_HASHTBLL 0x0000000C // Ethernet MAC Hash Table Low +#define EMAC_O_MIIADDR 0x00000010 // Ethernet MAC MII Address +#define EMAC_O_MIIDATA 0x00000014 // Ethernet MAC MII Data Register +#define EMAC_O_FLOWCTL 0x00000018 // Ethernet MAC Flow Control +#define EMAC_O_VLANTG 0x0000001C // Ethernet MAC VLAN Tag +#define EMAC_O_STATUS 0x00000024 // Ethernet MAC Status +#define EMAC_O_RWUFF 0x00000028 // Ethernet MAC Remote Wake-Up + // Frame Filter +#define EMAC_O_PMTCTLSTAT 0x0000002C // Ethernet MAC PMT Control and + // Status Register +#define EMAC_O_RIS 0x00000038 // Ethernet MAC Raw Interrupt + // Status +#define EMAC_O_IM 0x0000003C // Ethernet MAC Interrupt Mask +#define EMAC_O_ADDR0H 0x00000040 // Ethernet MAC Address 0 High +#define EMAC_O_ADDR0L 0x00000044 // Ethernet MAC Address 0 Low + // Register +#define EMAC_O_ADDR1H 0x00000048 // Ethernet MAC Address 1 High +#define EMAC_O_ADDR1L 0x0000004C // Ethernet MAC Address 1 Low +#define EMAC_O_ADDR2H 0x00000050 // Ethernet MAC Address 2 High +#define EMAC_O_ADDR2L 0x00000054 // Ethernet MAC Address 2 Low +#define EMAC_O_ADDR3H 0x00000058 // Ethernet MAC Address 3 High +#define EMAC_O_ADDR3L 0x0000005C // Ethernet MAC Address 3 Low +#define EMAC_O_WDOGTO 0x000000DC // Ethernet MAC Watchdog Timeout +#define EMAC_O_MMCCTRL 0x00000100 // Ethernet MAC MMC Control +#define EMAC_O_MMCRXRIS 0x00000104 // Ethernet MAC MMC Receive Raw + // Interrupt Status +#define EMAC_O_MMCTXRIS 0x00000108 // Ethernet MAC MMC Transmit Raw + // Interrupt Status +#define EMAC_O_MMCRXIM 0x0000010C // Ethernet MAC MMC Receive + // Interrupt Mask +#define EMAC_O_MMCTXIM 0x00000110 // Ethernet MAC MMC Transmit + // Interrupt Mask +#define EMAC_O_TXCNTGB 0x00000118 // Ethernet MAC Transmit Frame + // Count for Good and Bad Frames +#define EMAC_O_TXCNTSCOL 0x0000014C // Ethernet MAC Transmit Frame + // Count for Frames Transmitted + // after Single Collision +#define EMAC_O_TXCNTMCOL 0x00000150 // Ethernet MAC Transmit Frame + // Count for Frames Transmitted + // after Multiple Collisions +#define EMAC_O_TXOCTCNTG 0x00000164 // Ethernet MAC Transmit Octet + // Count Good +#define EMAC_O_RXCNTGB 0x00000180 // Ethernet MAC Receive Frame Count + // for Good and Bad Frames +#define EMAC_O_RXCNTCRCERR 0x00000194 // Ethernet MAC Receive Frame Count + // for CRC Error Frames +#define EMAC_O_RXCNTALGNERR 0x00000198 // Ethernet MAC Receive Frame Count + // for Alignment Error Frames +#define EMAC_O_RXCNTGUNI 0x000001C4 // Ethernet MAC Receive Frame Count + // for Good Unicast Frames +#define EMAC_O_VLNINCREP 0x00000584 // Ethernet MAC VLAN Tag Inclusion + // or Replacement +#define EMAC_O_VLANHASH 0x00000588 // Ethernet MAC VLAN Hash Table +#define EMAC_O_TIMSTCTRL 0x00000700 // Ethernet MAC Timestamp Control +#define EMAC_O_SUBSECINC 0x00000704 // Ethernet MAC Sub-Second + // Increment +#define EMAC_O_TIMSEC 0x00000708 // Ethernet MAC System Time - + // Seconds +#define EMAC_O_TIMNANO 0x0000070C // Ethernet MAC System Time - + // Nanoseconds +#define EMAC_O_TIMSECU 0x00000710 // Ethernet MAC System Time - + // Seconds Update +#define EMAC_O_TIMNANOU 0x00000714 // Ethernet MAC System Time - + // Nanoseconds Update +#define EMAC_O_TIMADD 0x00000718 // Ethernet MAC Timestamp Addend +#define EMAC_O_TARGSEC 0x0000071C // Ethernet MAC Target Time Seconds +#define EMAC_O_TARGNANO 0x00000720 // Ethernet MAC Target Time + // Nanoseconds +#define EMAC_O_HWORDSEC 0x00000724 // Ethernet MAC System Time-Higher + // Word Seconds +#define EMAC_O_TIMSTAT 0x00000728 // Ethernet MAC Timestamp Status +#define EMAC_O_PPSCTRL 0x0000072C // Ethernet MAC PPS Control +#define EMAC_O_PPS0INTVL 0x00000760 // Ethernet MAC PPS0 Interval +#define EMAC_O_PPS0WIDTH 0x00000764 // Ethernet MAC PPS0 Width +#define EMAC_O_DMABUSMOD 0x00000C00 // Ethernet MAC DMA Bus Mode +#define EMAC_O_TXPOLLD 0x00000C04 // Ethernet MAC Transmit Poll + // Demand +#define EMAC_O_RXPOLLD 0x00000C08 // Ethernet MAC Receive Poll Demand +#define EMAC_O_RXDLADDR 0x00000C0C // Ethernet MAC Receive Descriptor + // List Address +#define EMAC_O_TXDLADDR 0x00000C10 // Ethernet MAC Transmit Descriptor + // List Address +#define EMAC_O_DMARIS 0x00000C14 // Ethernet MAC DMA Interrupt + // Status +#define EMAC_O_DMAOPMODE 0x00000C18 // Ethernet MAC DMA Operation Mode +#define EMAC_O_DMAIM 0x00000C1C // Ethernet MAC DMA Interrupt Mask + // Register +#define EMAC_O_MFBOC 0x00000C20 // Ethernet MAC Missed Frame and + // Buffer Overflow Counter +#define EMAC_O_RXINTWDT 0x00000C24 // Ethernet MAC Receive Interrupt + // Watchdog Timer +#define EMAC_O_HOSTXDESC 0x00000C48 // Ethernet MAC Current Host + // Transmit Descriptor +#define EMAC_O_HOSRXDESC 0x00000C4C // Ethernet MAC Current Host + // Receive Descriptor +#define EMAC_O_HOSTXBA 0x00000C50 // Ethernet MAC Current Host + // Transmit Buffer Address +#define EMAC_O_HOSRXBA 0x00000C54 // Ethernet MAC Current Host + // Receive Buffer Address +#define EMAC_O_PP 0x00000FC0 // Ethernet MAC Peripheral Property + // Register +#define EMAC_O_PC 0x00000FC4 // Ethernet MAC Peripheral + // Configuration Register +#define EMAC_O_CC 0x00000FC8 // Ethernet MAC Clock Configuration + // Register +#define EMAC_O_EPHYRIS 0x00000FD0 // Ethernet PHY Raw Interrupt + // Status +#define EMAC_O_EPHYIM 0x00000FD4 // Ethernet PHY Interrupt Mask +#define EMAC_O_EPHYMISC 0x00000FD8 // Ethernet PHY Masked Interrupt + // Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_CFG register. +// +//***************************************************************************** +#define EMAC_CFG_TWOKPEN 0x08000000 // IEEE 802 +#define EMAC_CFG_CST 0x02000000 // CRC Stripping for Type Frames +#define EMAC_CFG_WDDIS 0x00800000 // Watchdog Disable +#define EMAC_CFG_JD 0x00400000 // Jabber Disable +#define EMAC_CFG_JFEN 0x00100000 // Jumbo Frame Enable +#define EMAC_CFG_IFG_M 0x000E0000 // Inter-Frame Gap (IFG) +#define EMAC_CFG_IFG_96 0x00000000 // 96 bit times +#define EMAC_CFG_IFG_88 0x00020000 // 88 bit times +#define EMAC_CFG_IFG_80 0x00040000 // 80 bit times +#define EMAC_CFG_IFG_72 0x00060000 // 72 bit times +#define EMAC_CFG_IFG_64 0x00080000 // 64 bit times +#define EMAC_CFG_IFG_56 0x000A0000 // 56 bit times +#define EMAC_CFG_IFG_48 0x000C0000 // 48 bit times +#define EMAC_CFG_IFG_40 0x000E0000 // 40 bit times +#define EMAC_CFG_DISCRS 0x00010000 // Disable Carrier Sense During + // Transmission +#define EMAC_CFG_PS 0x00008000 // Port Select +#define EMAC_CFG_FES 0x00004000 // Speed +#define EMAC_CFG_DRO 0x00002000 // Disable Receive Own +#define EMAC_CFG_LOOPBM 0x00001000 // Loopback Mode +#define EMAC_CFG_DUPM 0x00000800 // Duplex Mode +#define EMAC_CFG_IPC 0x00000400 // Checksum Offload +#define EMAC_CFG_DR 0x00000200 // Disable Retry +#define EMAC_CFG_ACS 0x00000080 // Automatic Pad or CRC Stripping +#define EMAC_CFG_BL_M 0x00000060 // Back-Off Limit +#define EMAC_CFG_BL_1024 0x00000000 // k = min (n,10) +#define EMAC_CFG_BL_256 0x00000020 // k = min (n,8) +#define EMAC_CFG_BL_8 0x00000040 // k = min (n,4) +#define EMAC_CFG_BL_2 0x00000060 // k = min (n,1) +#define EMAC_CFG_DC 0x00000010 // Deferral Check +#define EMAC_CFG_TE 0x00000008 // Transmitter Enable +#define EMAC_CFG_RE 0x00000004 // Receiver Enable +#define EMAC_CFG_PRELEN_M 0x00000003 // Preamble Length for Transmit + // Frames +#define EMAC_CFG_PRELEN_7 0x00000000 // 7 bytes of preamble +#define EMAC_CFG_PRELEN_5 0x00000001 // 5 bytes of preamble +#define EMAC_CFG_PRELEN_3 0x00000002 // 3 bytes of preamble + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_FRAMEFLTR +// register. +// +//***************************************************************************** +#define EMAC_FRAMEFLTR_RA 0x80000000 // Receive All +#define EMAC_FRAMEFLTR_VTFE 0x00010000 // VLAN Tag Filter Enable +#define EMAC_FRAMEFLTR_HPF 0x00000400 // Hash or Perfect Filter +#define EMAC_FRAMEFLTR_SAF 0x00000200 // Source Address Filter Enable +#define EMAC_FRAMEFLTR_SAIF 0x00000100 // Source Address (SA) Inverse + // Filtering +#define EMAC_FRAMEFLTR_PCF_M 0x000000C0 // Pass Control Frames +#define EMAC_FRAMEFLTR_PCF_ALL 0x00000000 // The MAC filters all control + // frames from reaching application +#define EMAC_FRAMEFLTR_PCF_PAUSE \ + 0x00000040 // MAC forwards all control frames + // except PAUSE control frames to + // application even if they fail + // the address filter +#define EMAC_FRAMEFLTR_PCF_NONE 0x00000080 // MAC forwards all control frames + // to application even if they fail + // the address Filter +#define EMAC_FRAMEFLTR_PCF_ADDR 0x000000C0 // MAC forwards control frames that + // pass the address Filter +#define EMAC_FRAMEFLTR_DBF 0x00000020 // Disable Broadcast Frames +#define EMAC_FRAMEFLTR_PM 0x00000010 // Pass All Multicast +#define EMAC_FRAMEFLTR_DAIF 0x00000008 // Destination Address (DA) Inverse + // Filtering +#define EMAC_FRAMEFLTR_HMC 0x00000004 // Hash Multicast +#define EMAC_FRAMEFLTR_HUC 0x00000002 // Hash Unicast +#define EMAC_FRAMEFLTR_PR 0x00000001 // Promiscuous Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HASHTBLH +// register. +// +//***************************************************************************** +#define EMAC_HASHTBLH_HTH_M 0xFFFFFFFF // Hash Table High +#define EMAC_HASHTBLH_HTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HASHTBLL +// register. +// +//***************************************************************************** +#define EMAC_HASHTBLL_HTL_M 0xFFFFFFFF // Hash Table Low +#define EMAC_HASHTBLL_HTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MIIADDR register. +// +//***************************************************************************** +#define EMAC_MIIADDR_PLA_M 0x0000F800 // Physical Layer Address +#define EMAC_MIIADDR_MII_M 0x000007C0 // MII Register +#define EMAC_MIIADDR_CR_M 0x0000003C // Clock Reference Frequency + // Selection +#define EMAC_MIIADDR_CR_60_100 0x00000000 // The frequency of the System + // Clock is 60 to 100 MHz providing + // a MDIO clock of SYSCLK/42 +#define EMAC_MIIADDR_CR_100_150 0x00000004 // The frequency of the System + // Clock is 100 to 150 MHz + // providing a MDIO clock of + // SYSCLK/62 +#define EMAC_MIIADDR_CR_20_35 0x00000008 // The frequency of the System + // Clock is 20-35 MHz providing a + // MDIO clock of System Clock/16 +#define EMAC_MIIADDR_CR_35_60 0x0000000C // The frequency of the System + // Clock is 35 to 60 MHz providing + // a MDIO clock of System Clock/26 +#define EMAC_MIIADDR_MIIW 0x00000002 // MII Write +#define EMAC_MIIADDR_MIIB 0x00000001 // MII Busy +#define EMAC_MIIADDR_PLA_S 11 +#define EMAC_MIIADDR_MII_S 6 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MIIDATA register. +// +//***************************************************************************** +#define EMAC_MIIDATA_DATA_M 0x0000FFFF // MII Data +#define EMAC_MIIDATA_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_FLOWCTL register. +// +//***************************************************************************** +#define EMAC_FLOWCTL_PT_M 0xFFFF0000 // Pause Time +#define EMAC_FLOWCTL_DZQP 0x00000080 // Disable Zero-Quanta Pause +#define EMAC_FLOWCTL_UP 0x00000008 // Unicast Pause Frame Detect +#define EMAC_FLOWCTL_RFE 0x00000004 // Receive Flow Control Enable +#define EMAC_FLOWCTL_TFE 0x00000002 // Transmit Flow Control Enable +#define EMAC_FLOWCTL_FCBBPA 0x00000001 // Flow Control Busy or + // Back-pressure Activate +#define EMAC_FLOWCTL_PT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_VLANTG register. +// +//***************************************************************************** +#define EMAC_VLANTG_VTHM 0x00080000 // VLAN Tag Hash Table Match Enable +#define EMAC_VLANTG_ESVL 0x00040000 // Enable S-VLAN +#define EMAC_VLANTG_VTIM 0x00020000 // VLAN Tag Inverse Match Enable +#define EMAC_VLANTG_ETV 0x00010000 // Enable 12-Bit VLAN Tag + // Comparison +#define EMAC_VLANTG_VL_M 0x0000FFFF // VLAN Tag Identifier for Receive + // Frames +#define EMAC_VLANTG_VL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_STATUS register. +// +//***************************************************************************** +#define EMAC_STATUS_TXFF 0x02000000 // TX/RX Controller TX FIFO Full + // Status +#define EMAC_STATUS_TXFE 0x01000000 // TX/RX Controller TX FIFO Not + // Empty Status +#define EMAC_STATUS_TWC 0x00400000 // TX/RX Controller TX FIFO Write + // Controller Active Status +#define EMAC_STATUS_TRC_M 0x00300000 // TX/RX Controller's TX FIFO Read + // Controller Status +#define EMAC_STATUS_TRC_IDLE 0x00000000 // IDLE state +#define EMAC_STATUS_TRC_READ 0x00100000 // READ state (transferring data to + // MAC transmitter) +#define EMAC_STATUS_TRC_WAIT 0x00200000 // Waiting for TX Status from MAC + // transmitter +#define EMAC_STATUS_TRC_WRFLUSH 0x00300000 // Writing the received TX Status + // or flushing the TX FIFO +#define EMAC_STATUS_TXPAUSED 0x00080000 // MAC Transmitter PAUSE +#define EMAC_STATUS_TFC_M 0x00060000 // MAC Transmit Frame Controller + // Status +#define EMAC_STATUS_TFC_IDLE 0x00000000 // IDLE state +#define EMAC_STATUS_TFC_STATUS 0x00020000 // Waiting for status of previous + // frame or IFG or backoff period + // to be over +#define EMAC_STATUS_TFC_PAUSE 0x00040000 // Generating and transmitting a + // PAUSE control frame (in the + // full-duplex mode) +#define EMAC_STATUS_TFC_INPUT 0x00060000 // Transferring input frame for + // transmission +#define EMAC_STATUS_TPE 0x00010000 // MAC MII Transmit Protocol Engine + // Status +#define EMAC_STATUS_RXF_M 0x00000300 // TX/RX Controller RX FIFO + // Fill-level Status +#define EMAC_STATUS_RXF_EMPTY 0x00000000 // RX FIFO Empty +#define EMAC_STATUS_RXF_BELOW 0x00000100 // RX FIFO fill level is below the + // flow-control deactivate + // threshold +#define EMAC_STATUS_RXF_ABOVE 0x00000200 // RX FIFO fill level is above the + // flow-control activate threshold +#define EMAC_STATUS_RXF_FULL 0x00000300 // RX FIFO Full +#define EMAC_STATUS_RRC_M 0x00000060 // TX/RX Controller Read Controller + // State +#define EMAC_STATUS_RRC_IDLE 0x00000000 // IDLE state +#define EMAC_STATUS_RRC_STATUS 0x00000020 // Reading frame data +#define EMAC_STATUS_RRC_DATA 0x00000040 // Reading frame status (or + // timestamp) +#define EMAC_STATUS_RRC_FLUSH 0x00000060 // Flushing the frame data and + // status +#define EMAC_STATUS_RWC 0x00000010 // TX/RX Controller RX FIFO Write + // Controller Active Status +#define EMAC_STATUS_RFCFC_M 0x00000006 // MAC Receive Frame Controller + // FIFO Status +#define EMAC_STATUS_RPE 0x00000001 // MAC MII Receive Protocol Engine + // Status +#define EMAC_STATUS_RFCFC_S 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RWUFF register. +// +//***************************************************************************** +#define EMAC_RWUFF_WAKEUPFIL_M 0xFFFFFFFF // Remote Wake-Up Frame Filter +#define EMAC_RWUFF_WAKEUPFIL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PMTCTLSTAT +// register. +// +//***************************************************************************** +#define EMAC_PMTCTLSTAT_WUPFRRST \ + 0x80000000 // Wake-Up Frame Filter Register + // Pointer Reset +#define EMAC_PMTCTLSTAT_RWKPTR_M \ + 0x07000000 // Remote Wake-Up FIFO Pointer +#define EMAC_PMTCTLSTAT_GLBLUCAST \ + 0x00000200 // Global Unicast +#define EMAC_PMTCTLSTAT_WUPRX 0x00000040 // Wake-Up Frame Received +#define EMAC_PMTCTLSTAT_MGKPRX 0x00000020 // Magic Packet Received +#define EMAC_PMTCTLSTAT_WUPFREN 0x00000004 // Wake-Up Frame Enable +#define EMAC_PMTCTLSTAT_MGKPKTEN \ + 0x00000002 // Magic Packet Enable +#define EMAC_PMTCTLSTAT_PWRDWN 0x00000001 // Power Down +#define EMAC_PMTCTLSTAT_RWKPTR_S \ + 24 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RIS register. +// +//***************************************************************************** +#define EMAC_RIS_TS 0x00000200 // Timestamp Interrupt Status +#define EMAC_RIS_MMCTX 0x00000040 // MMC Transmit Interrupt Status +#define EMAC_RIS_MMCRX 0x00000020 // MMC Receive Interrupt Status +#define EMAC_RIS_MMC 0x00000010 // MMC Interrupt Status +#define EMAC_RIS_PMT 0x00000008 // PMT Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_IM register. +// +//***************************************************************************** +#define EMAC_IM_TSI 0x00000200 // Timestamp Interrupt Mask +#define EMAC_IM_PMT 0x00000008 // PMT Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR0H register. +// +//***************************************************************************** +#define EMAC_ADDR0H_AE 0x80000000 // Address Enable +#define EMAC_ADDR0H_ADDRHI_M 0x0000FFFF // MAC Address0 [47:32] +#define EMAC_ADDR0H_ADDRHI_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR0L register. +// +//***************************************************************************** +#define EMAC_ADDR0L_ADDRLO_M 0xFFFFFFFF // MAC Address0 [31:0] +#define EMAC_ADDR0L_ADDRLO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR1H register. +// +//***************************************************************************** +#define EMAC_ADDR1H_AE 0x80000000 // Address Enable +#define EMAC_ADDR1H_SA 0x40000000 // Source Address +#define EMAC_ADDR1H_MBC_M 0x3F000000 // Mask Byte Control +#define EMAC_ADDR1H_ADDRHI_M 0x0000FFFF // MAC Address1 [47:32] +#define EMAC_ADDR1H_MBC_S 24 +#define EMAC_ADDR1H_ADDRHI_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR1L register. +// +//***************************************************************************** +#define EMAC_ADDR1L_ADDRLO_M 0xFFFFFFFF // MAC Address1 [31:0] +#define EMAC_ADDR1L_ADDRLO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR2H register. +// +//***************************************************************************** +#define EMAC_ADDR2H_AE 0x80000000 // Address Enable +#define EMAC_ADDR2H_SA 0x40000000 // Source Address +#define EMAC_ADDR2H_MBC_M 0x3F000000 // Mask Byte Control +#define EMAC_ADDR2H_ADDRHI_M 0x0000FFFF // MAC Address2 [47:32] +#define EMAC_ADDR2H_MBC_S 24 +#define EMAC_ADDR2H_ADDRHI_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR2L register. +// +//***************************************************************************** +#define EMAC_ADDR2L_ADDRLO_M 0xFFFFFFFF // MAC Address2 [31:0] +#define EMAC_ADDR2L_ADDRLO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR3H register. +// +//***************************************************************************** +#define EMAC_ADDR3H_AE 0x80000000 // Address Enable +#define EMAC_ADDR3H_SA 0x40000000 // Source Address +#define EMAC_ADDR3H_MBC_M 0x3F000000 // Mask Byte Control +#define EMAC_ADDR3H_ADDRHI_M 0x0000FFFF // MAC Address3 [47:32] +#define EMAC_ADDR3H_MBC_S 24 +#define EMAC_ADDR3H_ADDRHI_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_ADDR3L register. +// +//***************************************************************************** +#define EMAC_ADDR3L_ADDRLO_M 0xFFFFFFFF // MAC Address3 [31:0] +#define EMAC_ADDR3L_ADDRLO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_WDOGTO register. +// +//***************************************************************************** +#define EMAC_WDOGTO_PWE 0x00010000 // Programmable Watchdog Enable +#define EMAC_WDOGTO_WTO_M 0x00003FFF // Watchdog Timeout +#define EMAC_WDOGTO_WTO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MMCCTRL register. +// +//***************************************************************************** +#define EMAC_MMCCTRL_UCDBC 0x00000100 // Update MMC Counters for Dropped + // Broadcast Frames +#define EMAC_MMCCTRL_CNTPRSTLVL 0x00000020 // Full/Half Preset Level Value +#define EMAC_MMCCTRL_CNTPRST 0x00000010 // Counters Preset +#define EMAC_MMCCTRL_CNTFREEZ 0x00000008 // MMC Counter Freeze +#define EMAC_MMCCTRL_RSTONRD 0x00000004 // Reset on Read +#define EMAC_MMCCTRL_CNTSTPRO 0x00000002 // Counters Stop Rollover +#define EMAC_MMCCTRL_CNTRST 0x00000001 // Counters Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MMCRXRIS +// register. +// +//***************************************************************************** +#define EMAC_MMCRXRIS_UCGF 0x00020000 // MMC Receive Unicast Good Frame + // Counter Interrupt Status +#define EMAC_MMCRXRIS_ALGNERR 0x00000040 // MMC Receive Alignment Error + // Frame Counter Interrupt Status +#define EMAC_MMCRXRIS_CRCERR 0x00000020 // MMC Receive CRC Error Frame + // Counter Interrupt Status +#define EMAC_MMCRXRIS_GBF 0x00000001 // MMC Receive Good Bad Frame + // Counter Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MMCTXRIS +// register. +// +//***************************************************************************** +#define EMAC_MMCTXRIS_OCTCNT 0x00100000 // Octet Counter Interrupt Status +#define EMAC_MMCTXRIS_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision + // Good Frame Counter Interrupt + // Status +#define EMAC_MMCTXRIS_SCOLLGF 0x00004000 // MMC Transmit Single Collision + // Good Frame Counter Interrupt + // Status +#define EMAC_MMCTXRIS_GBF 0x00000002 // MMC Transmit Good Bad Frame + // Counter Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MMCRXIM register. +// +//***************************************************************************** +#define EMAC_MMCRXIM_UCGF 0x00020000 // MMC Receive Unicast Good Frame + // Counter Interrupt Mask +#define EMAC_MMCRXIM_ALGNERR 0x00000040 // MMC Receive Alignment Error + // Frame Counter Interrupt Mask +#define EMAC_MMCRXIM_CRCERR 0x00000020 // MMC Receive CRC Error Frame + // Counter Interrupt Mask +#define EMAC_MMCRXIM_GBF 0x00000001 // MMC Receive Good Bad Frame + // Counter Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MMCTXIM register. +// +//***************************************************************************** +#define EMAC_MMCTXIM_OCTCNT 0x00100000 // MMC Transmit Good Octet Counter + // Interrupt Mask +#define EMAC_MMCTXIM_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision + // Good Frame Counter Interrupt + // Mask +#define EMAC_MMCTXIM_SCOLLGF 0x00004000 // MMC Transmit Single Collision + // Good Frame Counter Interrupt + // Mask +#define EMAC_MMCTXIM_GBF 0x00000002 // MMC Transmit Good Bad Frame + // Counter Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXCNTGB register. +// +//***************************************************************************** +#define EMAC_TXCNTGB_TXFRMGB_M 0xFFFFFFFF // This field indicates the number + // of good and bad frames + // transmitted, exclusive of + // retried frames +#define EMAC_TXCNTGB_TXFRMGB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXCNTSCOL +// register. +// +//***************************************************************************** +#define EMAC_TXCNTSCOL_TXSNGLCOLG_M \ + 0xFFFFFFFF // This field indicates the number + // of successfully transmitted + // frames after a single collision + // in the half-duplex mode +#define EMAC_TXCNTSCOL_TXSNGLCOLG_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXCNTMCOL +// register. +// +//***************************************************************************** +#define EMAC_TXCNTMCOL_TXMULTCOLG_M \ + 0xFFFFFFFF // This field indicates the number + // of successfully transmitted + // frames after multiple collisions + // in the half-duplex mode +#define EMAC_TXCNTMCOL_TXMULTCOLG_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXOCTCNTG +// register. +// +//***************************************************************************** +#define EMAC_TXOCTCNTG_TXOCTG_M 0xFFFFFFFF // This field indicates the number + // of bytes transmitted, exclusive + // of preamble, in good frames +#define EMAC_TXOCTCNTG_TXOCTG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXCNTGB register. +// +//***************************************************************************** +#define EMAC_RXCNTGB_RXFRMGB_M 0xFFFFFFFF // This field indicates the number + // of received good and bad frames +#define EMAC_RXCNTGB_RXFRMGB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXCNTCRCERR +// register. +// +//***************************************************************************** +#define EMAC_RXCNTCRCERR_RXCRCERR_M \ + 0xFFFFFFFF // This field indicates the number + // of frames received with CRC + // error +#define EMAC_RXCNTCRCERR_RXCRCERR_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXCNTALGNERR +// register. +// +//***************************************************************************** +#define EMAC_RXCNTALGNERR_RXALGNERR_M \ + 0xFFFFFFFF // This field indicates the number + // of frames received with + // alignment (dribble) error +#define EMAC_RXCNTALGNERR_RXALGNERR_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXCNTGUNI +// register. +// +//***************************************************************************** +#define EMAC_RXCNTGUNI_RXUCASTG_M \ + 0xFFFFFFFF // This field indicates the number + // of received good unicast frames +#define EMAC_RXCNTGUNI_RXUCASTG_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_VLNINCREP +// register. +// +//***************************************************************************** +#define EMAC_VLNINCREP_CSVL 0x00080000 // C-VLAN or S-VLAN +#define EMAC_VLNINCREP_VLP 0x00040000 // VLAN Priority Control +#define EMAC_VLNINCREP_VLC_M 0x00030000 // VLAN Tag Control in Transmit + // Frames +#define EMAC_VLNINCREP_VLC_NONE 0x00000000 // No VLAN tag deletion, insertion, + // or replacement +#define EMAC_VLNINCREP_VLC_TAGDEL \ + 0x00010000 // VLAN tag deletion +#define EMAC_VLNINCREP_VLC_TAGINS \ + 0x00020000 // VLAN tag insertion +#define EMAC_VLNINCREP_VLC_TAGREP \ + 0x00030000 // VLAN tag replacement +#define EMAC_VLNINCREP_VLT_M 0x0000FFFF // VLAN Tag for Transmit Frames +#define EMAC_VLNINCREP_VLT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_VLANHASH +// register. +// +//***************************************************************************** +#define EMAC_VLANHASH_VLHT_M 0x0000FFFF // VLAN Hash Table +#define EMAC_VLANHASH_VLHT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMSTCTRL +// register. +// +//***************************************************************************** +#define EMAC_TIMSTCTRL_PTPFLTR 0x00040000 // Enable MAC address for PTP Frame + // Filtering +#define EMAC_TIMSTCTRL_SELPTP_M 0x00030000 // Select PTP packets for Taking + // Snapshots +#define EMAC_TIMSTCTRL_TSMAST 0x00008000 // Enable Snapshot for Messages + // Relevant to Master +#define EMAC_TIMSTCTRL_TSEVNT 0x00004000 // Enable Timestamp Snapshot for + // Event Messages +#define EMAC_TIMSTCTRL_PTPIPV4 0x00002000 // Enable Processing of PTP Frames + // Sent over IPv4-UDP +#define EMAC_TIMSTCTRL_PTPIPV6 0x00001000 // Enable Processing of PTP Frames + // Sent Over IPv6-UDP +#define EMAC_TIMSTCTRL_PTPETH 0x00000800 // Enable Processing of PTP Over + // Ethernet Frames +#define EMAC_TIMSTCTRL_PTPVER2 0x00000400 // Enable PTP Packet Processing For + // Version 2 Format +#define EMAC_TIMSTCTRL_DGTLBIN 0x00000200 // Timestamp Digital or Binary + // Rollover Control +#define EMAC_TIMSTCTRL_ALLF 0x00000100 // Enable Timestamp For All Frames +#define EMAC_TIMSTCTRL_ADDREGUP 0x00000020 // Addend Register Update +#define EMAC_TIMSTCTRL_INTTRIG 0x00000010 // Timestamp Interrupt Trigger + // Enable +#define EMAC_TIMSTCTRL_TSUPDT 0x00000008 // Timestamp Update +#define EMAC_TIMSTCTRL_TSINIT 0x00000004 // Timestamp Initialize +#define EMAC_TIMSTCTRL_TSFCUPDT 0x00000002 // Timestamp Fine or Coarse Update +#define EMAC_TIMSTCTRL_TSEN 0x00000001 // Timestamp Enable +#define EMAC_TIMSTCTRL_SELPTP_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_SUBSECINC +// register. +// +//***************************************************************************** +#define EMAC_SUBSECINC_SSINC_M 0x000000FF // Sub-second Increment Value +#define EMAC_SUBSECINC_SSINC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMSEC register. +// +//***************************************************************************** +#define EMAC_TIMSEC_TSS_M 0xFFFFFFFF // Timestamp Second +#define EMAC_TIMSEC_TSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMNANO register. +// +//***************************************************************************** +#define EMAC_TIMNANO_TSSS_M 0x7FFFFFFF // Timestamp Sub-Seconds +#define EMAC_TIMNANO_TSSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMSECU register. +// +//***************************************************************************** +#define EMAC_TIMSECU_TSS_M 0xFFFFFFFF // Timestamp Second +#define EMAC_TIMSECU_TSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMNANOU +// register. +// +//***************************************************************************** +#define EMAC_TIMNANOU_ADDSUB 0x80000000 // Add or subtract time +#define EMAC_TIMNANOU_TSSS_M 0x7FFFFFFF // Timestamp Sub-Second +#define EMAC_TIMNANOU_TSSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMADD register. +// +//***************************************************************************** +#define EMAC_TIMADD_TSAR_M 0xFFFFFFFF // Timestamp Addend Register +#define EMAC_TIMADD_TSAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TARGSEC register. +// +//***************************************************************************** +#define EMAC_TARGSEC_TSTR_M 0xFFFFFFFF // Target Time Seconds Register +#define EMAC_TARGSEC_TSTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TARGNANO +// register. +// +//***************************************************************************** +#define EMAC_TARGNANO_TRGTBUSY 0x80000000 // Target Time Register Busy +#define EMAC_TARGNANO_TTSLO_M 0x7FFFFFFF // Target Timestamp Low Register +#define EMAC_TARGNANO_TTSLO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HWORDSEC +// register. +// +//***************************************************************************** +#define EMAC_HWORDSEC_TSHWR_M 0x0000FFFF // Target Timestamp Higher Word + // Register +#define EMAC_HWORDSEC_TSHWR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TIMSTAT register. +// +//***************************************************************************** +#define EMAC_TIMSTAT_TSTARGT 0x00000002 // Timestamp Target Time Reached +#define EMAC_TIMSTAT_TSSOVF 0x00000001 // Timestamp Seconds Overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PPSCTRL register. +// +//***************************************************************************** +#define EMAC_PPSCTRL_TRGMODS0_M 0x00000060 // Target Time Register Mode for + // PPS0 Output +#define EMAC_PPSCTRL_TRGMODS0_INTONLY \ + 0x00000000 // Indicates that the Target Time + // registers are programmed only + // for generating the interrupt + // event +#define EMAC_PPSCTRL_TRGMODS0_INTPPS0 \ + 0x00000040 // Indicates that the Target Time + // registers are programmed for + // generating the interrupt event + // and starting or stopping the + // generation of the EN0PPS output + // signal +#define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY \ + 0x00000060 // Indicates that the Target Time + // registers are programmed only + // for starting or stopping the + // generation of the EN0PPS output + // signal. No interrupt is asserted +#define EMAC_PPSCTRL_PPSEN0 0x00000010 // Flexible PPS Output Mode Enable +#define EMAC_PPSCTRL_PPSCTRL_M 0x0000000F // EN0PPS Output Frequency Control + // (PPSCTRL) or Command Control + // (PPSCMD) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PPS0INTVL +// register. +// +//***************************************************************************** +#define EMAC_PPS0INTVL_PPS0INT_M \ + 0xFFFFFFFF // PPS0 Output Signal Interval +#define EMAC_PPS0INTVL_PPS0INT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PPS0WIDTH +// register. +// +//***************************************************************************** +#define EMAC_PPS0WIDTH_M 0xFFFFFFFF // EN0PPS Output Signal Width +#define EMAC_PPS0WIDTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_DMABUSMOD +// register. +// +//***************************************************************************** +#define EMAC_DMABUSMOD_RIB 0x80000000 // Rebuild Burst +#define EMAC_DMABUSMOD_TXPR 0x08000000 // Transmit Priority +#define EMAC_DMABUSMOD_MB 0x04000000 // Mixed Burst +#define EMAC_DMABUSMOD_AAL 0x02000000 // Address Aligned Beats +#define EMAC_DMABUSMOD_8XPBL 0x01000000 // 8 x Programmable Burst Length + // (PBL) Mode +#define EMAC_DMABUSMOD_USP 0x00800000 // Use Separate Programmable Burst + // Length (PBL) +#define EMAC_DMABUSMOD_RPBL_M 0x007E0000 // RX DMA Programmable Burst Length + // (PBL) +#define EMAC_DMABUSMOD_FB 0x00010000 // Fixed Burst +#define EMAC_DMABUSMOD_PR_M 0x0000C000 // Priority Ratio +#define EMAC_DMABUSMOD_PBL_M 0x00003F00 // Programmable Burst Length +#define EMAC_DMABUSMOD_ATDS 0x00000080 // Alternate Descriptor Size +#define EMAC_DMABUSMOD_DSL_M 0x0000007C // Descriptor Skip Length +#define EMAC_DMABUSMOD_DA 0x00000002 // DMA Arbitration Scheme +#define EMAC_DMABUSMOD_SWR 0x00000001 // DMA Software Reset +#define EMAC_DMABUSMOD_RPBL_S 17 +#define EMAC_DMABUSMOD_PR_S 14 +#define EMAC_DMABUSMOD_PBL_S 8 +#define EMAC_DMABUSMOD_DSL_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXPOLLD register. +// +//***************************************************************************** +#define EMAC_TXPOLLD_TPD_M 0xFFFFFFFF // Transmit Poll Demand +#define EMAC_TXPOLLD_TPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXPOLLD register. +// +//***************************************************************************** +#define EMAC_RXPOLLD_RPD_M 0xFFFFFFFF // Receive Poll Demand +#define EMAC_RXPOLLD_RPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXDLADDR +// register. +// +//***************************************************************************** +#define EMAC_RXDLADDR_STRXLIST_M \ + 0xFFFFFFFC // Start of Receive List +#define EMAC_RXDLADDR_STRXLIST_S \ + 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_TXDLADDR +// register. +// +//***************************************************************************** +#define EMAC_TXDLADDR_TXDLADDR_M \ + 0xFFFFFFFC // Start of Transmit List Base + // Address +#define EMAC_TXDLADDR_TXDLADDR_S \ + 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_DMARIS register. +// +//***************************************************************************** +#define EMAC_DMARIS_TT 0x20000000 // Timestamp Trigger Interrupt + // Status +#define EMAC_DMARIS_PMT 0x10000000 // MAC PMT Interrupt Status +#define EMAC_DMARIS_MMC 0x08000000 // MAC MMC Interrupt +#define EMAC_DMARIS_AE_M 0x03800000 // Access Error +#define EMAC_DMARIS_AE_RXDMAWD 0x00000000 // Error during RX DMA Write Data + // Transfer +#define EMAC_DMARIS_AE_TXDMARD 0x01800000 // Error during TX DMA Read Data + // Transfer +#define EMAC_DMARIS_AE_RXDMADW 0x02000000 // Error during RX DMA Descriptor + // Write Access +#define EMAC_DMARIS_AE_TXDMADW 0x02800000 // Error during TX DMA Descriptor + // Write Access +#define EMAC_DMARIS_AE_RXDMADR 0x03000000 // Error during RX DMA Descriptor + // Read Access +#define EMAC_DMARIS_AE_TXDMADR 0x03800000 // Error during TX DMA Descriptor + // Read Access +#define EMAC_DMARIS_TS_M 0x00700000 // Transmit Process State +#define EMAC_DMARIS_TS_STOP 0x00000000 // Stopped; Reset or Stop transmit + // command processed +#define EMAC_DMARIS_TS_RUNTXTD 0x00100000 // Running; Fetching transmit + // transfer descriptor +#define EMAC_DMARIS_TS_STATUS 0x00200000 // Running; Waiting for status +#define EMAC_DMARIS_TS_RUNTX 0x00300000 // Running; Reading data from host + // memory buffer and queuing it to + // transmit buffer (TX FIFO) +#define EMAC_DMARIS_TS_TSTAMP 0x00400000 // Writing Timestamp +#define EMAC_DMARIS_TS_SUSPEND 0x00600000 // Suspended; Transmit descriptor + // unavailable or transmit buffer + // underflow +#define EMAC_DMARIS_TS_RUNCTD 0x00700000 // Running; Closing transmit + // descriptor +#define EMAC_DMARIS_RS_M 0x000E0000 // Received Process State +#define EMAC_DMARIS_RS_STOP 0x00000000 // Stopped: Reset or stop receive + // command issued +#define EMAC_DMARIS_RS_RUNRXTD 0x00020000 // Running: Fetching receive + // transfer descriptor +#define EMAC_DMARIS_RS_RUNRXD 0x00060000 // Running: Waiting for receive + // packet +#define EMAC_DMARIS_RS_SUSPEND 0x00080000 // Suspended: Receive descriptor + // unavailable +#define EMAC_DMARIS_RS_RUNCRD 0x000A0000 // Running: Closing receive + // descriptor +#define EMAC_DMARIS_RS_TSWS 0x000C0000 // Writing Timestamp +#define EMAC_DMARIS_RS_RUNTXD 0x000E0000 // Running: Transferring the + // receive packet data from receive + // buffer to host memory +#define EMAC_DMARIS_NIS 0x00010000 // Normal Interrupt Summary +#define EMAC_DMARIS_AIS 0x00008000 // Abnormal Interrupt Summary +#define EMAC_DMARIS_ERI 0x00004000 // Early Receive Interrupt +#define EMAC_DMARIS_FBI 0x00002000 // Fatal Bus Error Interrupt +#define EMAC_DMARIS_ETI 0x00000400 // Early Transmit Interrupt +#define EMAC_DMARIS_RWT 0x00000200 // Receive Watchdog Timeout +#define EMAC_DMARIS_RPS 0x00000100 // Receive Process Stopped +#define EMAC_DMARIS_RU 0x00000080 // Receive Buffer Unavailable +#define EMAC_DMARIS_RI 0x00000040 // Receive Interrupt +#define EMAC_DMARIS_UNF 0x00000020 // Transmit Underflow +#define EMAC_DMARIS_OVF 0x00000010 // Receive Overflow +#define EMAC_DMARIS_TJT 0x00000008 // Transmit Jabber Timeout +#define EMAC_DMARIS_TU 0x00000004 // Transmit Buffer Unavailable +#define EMAC_DMARIS_TPS 0x00000002 // Transmit Process Stopped +#define EMAC_DMARIS_TI 0x00000001 // Transmit Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_DMAOPMODE +// register. +// +//***************************************************************************** +#define EMAC_DMAOPMODE_DT 0x04000000 // Disable Dropping of TCP/IP + // Checksum Error Frames +#define EMAC_DMAOPMODE_RSF 0x02000000 // Receive Store and Forward +#define EMAC_DMAOPMODE_DFF 0x01000000 // Disable Flushing of Received + // Frames +#define EMAC_DMAOPMODE_TSF 0x00200000 // Transmit Store and Forward +#define EMAC_DMAOPMODE_FTF 0x00100000 // Flush Transmit FIFO +#define EMAC_DMAOPMODE_TTC_M 0x0001C000 // Transmit Threshold Control +#define EMAC_DMAOPMODE_TTC_64 0x00000000 // 64 bytes +#define EMAC_DMAOPMODE_TTC_128 0x00004000 // 128 bytes +#define EMAC_DMAOPMODE_TTC_192 0x00008000 // 192 bytes +#define EMAC_DMAOPMODE_TTC_256 0x0000C000 // 256 bytes +#define EMAC_DMAOPMODE_TTC_40 0x00010000 // 40 bytes +#define EMAC_DMAOPMODE_TTC_32 0x00014000 // 32 bytes +#define EMAC_DMAOPMODE_TTC_24 0x00018000 // 24 bytes +#define EMAC_DMAOPMODE_TTC_16 0x0001C000 // 16 bytes +#define EMAC_DMAOPMODE_ST 0x00002000 // Start or Stop Transmission + // Command +#define EMAC_DMAOPMODE_FEF 0x00000080 // Forward Error Frames +#define EMAC_DMAOPMODE_FUF 0x00000040 // Forward Undersized Good Frames +#define EMAC_DMAOPMODE_DGF 0x00000020 // Drop Giant Frame Enable +#define EMAC_DMAOPMODE_RTC_M 0x00000018 // Receive Threshold Control +#define EMAC_DMAOPMODE_RTC_64 0x00000000 // 64 bytes +#define EMAC_DMAOPMODE_RTC_32 0x00000008 // 32 bytes +#define EMAC_DMAOPMODE_RTC_96 0x00000010 // 96 bytes +#define EMAC_DMAOPMODE_RTC_128 0x00000018 // 128 bytes +#define EMAC_DMAOPMODE_OSF 0x00000004 // Operate on Second Frame +#define EMAC_DMAOPMODE_SR 0x00000002 // Start or Stop Receive + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_DMAIM register. +// +//***************************************************************************** +#define EMAC_DMAIM_NIE 0x00010000 // Normal Interrupt Summary Enable +#define EMAC_DMAIM_AIE 0x00008000 // Abnormal Interrupt Summary + // Enable +#define EMAC_DMAIM_ERE 0x00004000 // Early Receive Interrupt Enable +#define EMAC_DMAIM_FBE 0x00002000 // Fatal Bus Error Enable +#define EMAC_DMAIM_ETE 0x00000400 // Early Transmit Interrupt Enable +#define EMAC_DMAIM_RWE 0x00000200 // Receive Watchdog Timeout Enable +#define EMAC_DMAIM_RSE 0x00000100 // Receive Stopped Enable +#define EMAC_DMAIM_RUE 0x00000080 // Receive Buffer Unavailable + // Enable +#define EMAC_DMAIM_RIE 0x00000040 // Receive Interrupt Enable +#define EMAC_DMAIM_UNE 0x00000020 // Underflow Interrupt Enable +#define EMAC_DMAIM_OVE 0x00000010 // Overflow Interrupt Enable +#define EMAC_DMAIM_TJE 0x00000008 // Transmit Jabber Timeout Enable +#define EMAC_DMAIM_TUE 0x00000004 // Transmit Buffer Unvailable + // Enable +#define EMAC_DMAIM_TSE 0x00000002 // Transmit Stopped Enable +#define EMAC_DMAIM_TIE 0x00000001 // Transmit Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_MFBOC register. +// +//***************************************************************************** +#define EMAC_MFBOC_OVFCNTOVF 0x10000000 // Overflow Bit for FIFO Overflow + // Counter +#define EMAC_MFBOC_OVFFRMCNT_M 0x0FFE0000 // Overflow Frame Counter +#define EMAC_MFBOC_MISCNTOVF 0x00010000 // Overflow bit for Missed Frame + // Counter +#define EMAC_MFBOC_MISFRMCNT_M 0x0000FFFF // Missed Frame Counter +#define EMAC_MFBOC_OVFFRMCNT_S 17 +#define EMAC_MFBOC_MISFRMCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_RXINTWDT +// register. +// +//***************************************************************************** +#define EMAC_RXINTWDT_RIWT_M 0x000000FF // Receive Interrupt Watchdog Timer + // Count +#define EMAC_RXINTWDT_RIWT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HOSTXDESC +// register. +// +//***************************************************************************** +#define EMAC_HOSTXDESC_CURTXDESC_M \ + 0xFFFFFFFF // Host Transmit Descriptor Address + // Pointer +#define EMAC_HOSTXDESC_CURTXDESC_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HOSRXDESC +// register. +// +//***************************************************************************** +#define EMAC_HOSRXDESC_CURRXDESC_M \ + 0xFFFFFFFF // Host Receive Descriptor Address + // Pointer +#define EMAC_HOSRXDESC_CURRXDESC_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HOSTXBA register. +// +//***************************************************************************** +#define EMAC_HOSTXBA_CURTXBUFA_M \ + 0xFFFFFFFF // Host Transmit Buffer Address + // Pointer +#define EMAC_HOSTXBA_CURTXBUFA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_HOSRXBA register. +// +//***************************************************************************** +#define EMAC_HOSRXBA_CURRXBUFA_M \ + 0xFFFFFFFF // Host Receive Buffer Address + // Pointer +#define EMAC_HOSRXBA_CURRXBUFA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PP register. +// +//***************************************************************************** +#define EMAC_PP_MACTYPE_M 0x00000700 // Ethernet MAC Type +#define EMAC_PP_MACTYPE_1 0x00000100 // Tiva TM4E129x-class MAC +#define EMAC_PP_PHYTYPE_M 0x00000007 // Ethernet PHY Type +#define EMAC_PP_PHYTYPE_NONE 0x00000000 // No PHY +#define EMAC_PP_PHYTYPE_1 0x00000003 // Snowflake class PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_PC register. +// +//***************************************************************************** +#define EMAC_PC_PHYEXT 0x80000000 // PHY Select +#define EMAC_PC_PINTFS_M 0x70000000 // Ethernet Interface Select +#define EMAC_PC_PINTFS_IMII 0x00000000 // MII (default) Used for internal + // PHY or external PHY connected + // via MII +#define EMAC_PC_PINTFS_RMII 0x40000000 // RMII: Used for external PHY + // connected via RMII +#define EMAC_PC_DIGRESTART 0x02000000 // PHY Soft Restart +#define EMAC_PC_NIBDETDIS 0x01000000 // Odd Nibble TXER Detection + // Disable +#define EMAC_PC_RXERIDLE 0x00800000 // RXER Detection During Idle +#define EMAC_PC_ISOMIILL 0x00400000 // Isolate MII in Link Loss +#define EMAC_PC_LRR 0x00200000 // Link Loss Recovery +#define EMAC_PC_TDRRUN 0x00100000 // TDR Auto Run +#define EMAC_PC_FASTLDMODE_M 0x000F8000 // Fast Link Down Mode +#define EMAC_PC_POLSWAP 0x00004000 // Polarity Swap +#define EMAC_PC_MDISWAP 0x00002000 // MDI Swap +#define EMAC_PC_RBSTMDIX 0x00001000 // Robust Auto MDI-X +#define EMAC_PC_FASTMDIX 0x00000800 // Fast Auto MDI-X +#define EMAC_PC_MDIXEN 0x00000400 // MDIX Enable +#define EMAC_PC_FASTRXDV 0x00000200 // Fast RXDV Detection +#define EMAC_PC_FASTLUPD 0x00000100 // FAST Link-Up in Parallel Detect +#define EMAC_PC_EXTFD 0x00000080 // Extended Full Duplex Ability +#define EMAC_PC_FASTANEN 0x00000040 // Fast Auto Negotiation Enable +#define EMAC_PC_FASTANSEL_M 0x00000030 // Fast Auto Negotiation Select +#define EMAC_PC_ANEN 0x00000008 // Auto Negotiation Enable +#define EMAC_PC_ANMODE_M 0x00000006 // Auto Negotiation Mode +#define EMAC_PC_ANMODE_10HD 0x00000000 // When ANEN = 0x0, the mode is + // 10Base-T, Half-Duplex +#define EMAC_PC_ANMODE_10FD 0x00000002 // When ANEN = 0x0, the mode is + // 10Base-T, Full-Duplex +#define EMAC_PC_ANMODE_100HD 0x00000004 // When ANEN = 0x0, the mode is + // 100Base-TX, Half-Duplex +#define EMAC_PC_ANMODE_100FD 0x00000006 // When ANEN = 0x0, the mode is + // 100Base-TX, Full-Duplex +#define EMAC_PC_PHYHOLD 0x00000001 // Ethernet PHY Hold +#define EMAC_PC_FASTLDMODE_S 15 +#define EMAC_PC_FASTANSEL_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_CC register. +// +//***************************************************************************** +#define EMAC_CC_PTPCEN 0x00040000 // PTP Clock Reference Enable +#define EMAC_CC_POL 0x00020000 // LED Polarity Control +#define EMAC_CC_CLKEN 0x00010000 // EN0RREF_CLK Signal Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_EPHYRIS register. +// +//***************************************************************************** +#define EMAC_EPHYRIS_INT 0x00000001 // Ethernet PHY Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_EPHYIM register. +// +//***************************************************************************** +#define EMAC_EPHYIM_INT 0x00000001 // Ethernet PHY Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_EPHYMISC +// register. +// +//***************************************************************************** +#define EMAC_EPHYMISC_INT 0x00000001 // Ethernet PHY Status and Clear + // register + +//***************************************************************************** +// +// The following are defines for the EPHY register offsets. +// +//***************************************************************************** +#define EPHY_BMCR 0x00000000 // Ethernet PHY Basic Mode Control +#define EPHY_BMSR 0x00000001 // Ethernet PHY Basic Mode Status +#define EPHY_ID1 0x00000002 // Ethernet PHY Identifier Register + // 1 +#define EPHY_ID2 0x00000003 // Ethernet PHY Identifier Register + // 2 +#define EPHY_ANA 0x00000004 // Ethernet PHY Auto-Negotiation + // Advertisement +#define EPHY_ANLPA 0x00000005 // Ethernet PHY Auto-Negotiation + // Link Partner Ability +#define EPHY_ANER 0x00000006 // Ethernet PHY Auto-Negotiation + // Expansion +#define EPHY_ANNPTR 0x00000007 // Ethernet PHY Auto-Negotiation + // Next Page TX +#define EPHY_ANLNPTR 0x00000008 // Ethernet PHY Auto-Negotiation + // Link Partner Ability Next Page +#define EPHY_CFG1 0x00000009 // Ethernet PHY Configuration 1 +#define EPHY_CFG2 0x0000000A // Ethernet PHY Configuration 2 +#define EPHY_CFG3 0x0000000B // Ethernet PHY Configuration 3 +#define EPHY_REGCTL 0x0000000D // Ethernet PHY Register Control +#define EPHY_ADDAR 0x0000000E // Ethernet PHY Address or Data +#define EPHY_STS 0x00000010 // Ethernet PHY Status +#define EPHY_SCR 0x00000011 // Ethernet PHY Specific Control +#define EPHY_MISR1 0x00000012 // Ethernet PHY MII Interrupt + // Status 1 +#define EPHY_MISR2 0x00000013 // Ethernet PHY MII Interrupt + // Status 2 +#define EPHY_FCSCR 0x00000014 // Ethernet PHY False Carrier Sense + // Counter +#define EPHY_RXERCNT 0x00000015 // Ethernet PHY Receive Error Count +#define EPHY_BISTCR 0x00000016 // Ethernet PHY BIST Control +#define EPHY_LEDCR 0x00000018 // Ethernet PHY LED Control +#define EPHY_CTL 0x00000019 // Ethernet PHY Control +#define EPHY_10BTSC 0x0000001A // Ethernet PHY 10Base-T + // Status/Control - MR26 +#define EPHY_BICSR1 0x0000001B // Ethernet PHY BIST Control and + // Status 1 +#define EPHY_BICSR2 0x0000001C // Ethernet PHY BIST Control and + // Status 2 +#define EPHY_CDCR 0x0000001E // Ethernet PHY Cable Diagnostic + // Control +#define EPHY_RCR 0x0000001F // Ethernet PHY Reset Control +#define EPHY_LEDCFG 0x00000025 // Ethernet PHY LED Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_BMCR register. +// +//***************************************************************************** +#define EPHY_BMCR_MIIRESET 0x00008000 // MII Register reset +#define EPHY_BMCR_MIILOOPBK 0x00004000 // MII Loopback +#define EPHY_BMCR_SPEED 0x00002000 // Speed Select +#define EPHY_BMCR_ANEN 0x00001000 // Auto-Negotiate Enable +#define EPHY_BMCR_PWRDWN 0x00000800 // Power Down +#define EPHY_BMCR_ISOLATE 0x00000400 // Port Isolate +#define EPHY_BMCR_RESTARTAN 0x00000200 // Restart Auto-Negotiation +#define EPHY_BMCR_DUPLEXM 0x00000100 // Duplex Mode +#define EPHY_BMCR_COLLTST 0x00000080 // Collision Test + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_BMSR register. +// +//***************************************************************************** +#define EPHY_BMSR_100BTXFD 0x00004000 // 100Base-TX Full Duplex Capable +#define EPHY_BMSR_100BTXHD 0x00002000 // 100Base-TX Half Duplex Capable +#define EPHY_BMSR_10BTFD 0x00001000 // 10 Base-T Full Duplex Capable +#define EPHY_BMSR_10BTHD 0x00000800 // 10 Base-T Half Duplex Capable +#define EPHY_BMSR_MFPRESUP 0x00000040 // Preamble Suppression Capable +#define EPHY_BMSR_ANC 0x00000020 // Auto-Negotiation Complete +#define EPHY_BMSR_RFAULT 0x00000010 // Remote Fault +#define EPHY_BMSR_ANEN 0x00000008 // Auto Negotiation Enabled +#define EPHY_BMSR_LINKSTAT 0x00000004 // Link Status +#define EPHY_BMSR_JABBER 0x00000002 // Jabber Detect +#define EPHY_BMSR_EXTEN 0x00000001 // Extended Capability Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ID1 register. +// +//***************************************************************************** +#define EPHY_ID1_OUIMSB_M 0x0000FFFF // OUI Most Significant Bits +#define EPHY_ID1_OUIMSB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ID2 register. +// +//***************************************************************************** +#define EPHY_ID2_OUILSB_M 0x0000FC00 // OUI Least Significant Bits +#define EPHY_ID2_VNDRMDL_M 0x000003F0 // Vendor Model Number +#define EPHY_ID2_MDLREV_M 0x0000000F // Model Revision Number +#define EPHY_ID2_OUILSB_S 10 +#define EPHY_ID2_VNDRMDL_S 4 +#define EPHY_ID2_MDLREV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ANA register. +// +//***************************************************************************** +#define EPHY_ANA_NP 0x00008000 // Next Page Indication +#define EPHY_ANA_RF 0x00002000 // Remote Fault +#define EPHY_ANA_ASMDUP 0x00000800 // Asymmetric PAUSE support for + // Full Duplex Links +#define EPHY_ANA_PAUSE 0x00000400 // PAUSE Support for Full Duplex + // Links +#define EPHY_ANA_100BT4 0x00000200 // 100Base-T4 Support +#define EPHY_ANA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support +#define EPHY_ANA_100BTX 0x00000080 // 100Base-TX Support +#define EPHY_ANA_10BTFD 0x00000040 // 10Base-T Full Duplex Support +#define EPHY_ANA_10BT 0x00000020 // 10Base-T Support +#define EPHY_ANA_SELECT_M 0x0000001F // Protocol Selection +#define EPHY_ANA_SELECT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ANLPA register. +// +//***************************************************************************** +#define EPHY_ANLPA_NP 0x00008000 // Next Page Indication +#define EPHY_ANLPA_ACK 0x00004000 // Acknowledge +#define EPHY_ANLPA_RF 0x00002000 // Remote Fault +#define EPHY_ANLPA_ASMDUP 0x00000800 // Asymmetric PAUSE +#define EPHY_ANLPA_PAUSE 0x00000400 // PAUSE +#define EPHY_ANLPA_100BT4 0x00000200 // 100Base-T4 Support +#define EPHY_ANLPA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support +#define EPHY_ANLPA_100BTX 0x00000080 // 100Base-TX Support +#define EPHY_ANLPA_10BTFD 0x00000040 // 10Base-T Full Duplex Support +#define EPHY_ANLPA_10BT 0x00000020 // 10Base-T Support +#define EPHY_ANLPA_SELECT_M 0x0000001F // Protocol Selection +#define EPHY_ANLPA_SELECT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ANER register. +// +//***************************************************************************** +#define EPHY_ANER_PDF 0x00000010 // Parallel Detection Fault +#define EPHY_ANER_LPNPABLE 0x00000008 // Link Partner Next Page Able +#define EPHY_ANER_NPABLE 0x00000004 // Next Page Able +#define EPHY_ANER_PAGERX 0x00000002 // Link Code Word Page Received +#define EPHY_ANER_LPANABLE 0x00000001 // Link Partner Auto-Negotiation + // Able + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ANNPTR register. +// +//***************************************************************************** +#define EPHY_ANNPTR_NP 0x00008000 // Next Page Indication +#define EPHY_ANNPTR_MP 0x00002000 // Message Page +#define EPHY_ANNPTR_ACK2 0x00001000 // Acknowledge 2 +#define EPHY_ANNPTR_TOGTX 0x00000800 // Toggle +#define EPHY_ANNPTR_CODE_M 0x000007FF // Code +#define EPHY_ANNPTR_CODE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ANLNPTR register. +// +//***************************************************************************** +#define EPHY_ANLNPTR_NP 0x00008000 // Next Page Indication +#define EPHY_ANLNPTR_ACK 0x00004000 // Acknowledge +#define EPHY_ANLNPTR_MP 0x00002000 // Message Page +#define EPHY_ANLNPTR_ACK2 0x00001000 // Acknowledge 2 +#define EPHY_ANLNPTR_TOG 0x00000800 // Toggle +#define EPHY_ANLNPTR_CODE_M 0x000007FF // Code +#define EPHY_ANLNPTR_CODE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_CFG1 register. +// +//***************************************************************************** +#define EPHY_CFG1_DONE 0x00008000 // Configuration Done +#define EPHY_CFG1_TDRAR 0x00000100 // TDR Auto-Run at Link Down +#define EPHY_CFG1_LLR 0x00000080 // Link Loss Recovery +#define EPHY_CFG1_FAMDIX 0x00000040 // Fast Auto MDI/MDIX +#define EPHY_CFG1_RAMDIX 0x00000020 // Robust Auto MDI/MDIX +#define EPHY_CFG1_FASTANEN 0x00000010 // Fast Auto Negotiation Enable +#define EPHY_CFG1_FANSEL_M 0x0000000C // Fast Auto-Negotiation Select + // Configuration +#define EPHY_CFG1_FANSEL_BLT80 0x00000000 // Break Link Timer: 80 ms +#define EPHY_CFG1_FANSEL_BLT120 0x00000004 // Break Link Timer: 120 ms +#define EPHY_CFG1_FANSEL_BLT240 0x00000008 // Break Link Timer: 240 ms +#define EPHY_CFG1_FRXDVDET 0x00000002 // FAST RXDV Detection + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_CFG2 register. +// +//***************************************************************************** +#define EPHY_CFG2_FLUPPD 0x00000040 // Fast Link-Up in Parallel Detect + // Mode +#define EPHY_CFG2_EXTFD 0x00000020 // Extended Full-Duplex Ability +#define EPHY_CFG2_ENLEDLINK 0x00000010 // Enhanced LED Functionality +#define EPHY_CFG2_ISOMIILL 0x00000008 // Isolate MII outputs when + // Enhanced Link is not Achievable +#define EPHY_CFG2_RXERRIDLE 0x00000004 // Detection of Receive Symbol + // Error During IDLE State +#define EPHY_CFG2_ODDNDETDIS 0x00000002 // Detection of Transmit Error + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_CFG3 register. +// +//***************************************************************************** +#define EPHY_CFG3_POLSWAP 0x00000080 // Polarity Swap +#define EPHY_CFG3_MDIMDIXS 0x00000040 // MDI/MDIX Swap +#define EPHY_CFG3_FLDWNM_M 0x0000001F // Fast Link Down Modes +#define EPHY_CFG3_FLDWNM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_REGCTL register. +// +//***************************************************************************** +#define EPHY_REGCTL_FUNC_M 0x0000C000 // Function +#define EPHY_REGCTL_FUNC_ADDR 0x00000000 // Address +#define EPHY_REGCTL_FUNC_DATANI 0x00004000 // Data, no post increment +#define EPHY_REGCTL_FUNC_DATAPIRW \ + 0x00008000 // Data, post increment on read and + // write +#define EPHY_REGCTL_FUNC_DATAPIWO \ + 0x0000C000 // Data, post increment on write + // only +#define EPHY_REGCTL_DEVAD_M 0x0000001F // Device Address +#define EPHY_REGCTL_DEVAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_ADDAR register. +// +//***************************************************************************** +#define EPHY_ADDAR_ADDRDATA_M 0x0000FFFF // Address or Data +#define EPHY_ADDAR_ADDRDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_STS register. +// +//***************************************************************************** +#define EPHY_STS_MDIXM 0x00004000 // MDI-X Mode +#define EPHY_STS_RXLERR 0x00002000 // Receive Error Latch +#define EPHY_STS_POLSTAT 0x00001000 // Polarity Status +#define EPHY_STS_FCSL 0x00000800 // False Carrier Sense Latch +#define EPHY_STS_SD 0x00000400 // Signal Detect +#define EPHY_STS_DL 0x00000200 // Descrambler Lock +#define EPHY_STS_PAGERX 0x00000100 // Link Code Page Received +#define EPHY_STS_MIIREQ 0x00000080 // MII Interrupt Pending +#define EPHY_STS_RF 0x00000040 // Remote Fault +#define EPHY_STS_JD 0x00000020 // Jabber Detect +#define EPHY_STS_ANS 0x00000010 // Auto-Negotiation Status +#define EPHY_STS_MIILB 0x00000008 // MII Loopback Status +#define EPHY_STS_DUPLEX 0x00000004 // Duplex Status +#define EPHY_STS_SPEED 0x00000002 // Speed Status +#define EPHY_STS_LINK 0x00000001 // Link Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_SCR register. +// +//***************************************************************************** +#define EPHY_SCR_DISCLK 0x00008000 // Disable CLK +#define EPHY_SCR_PSEN 0x00004000 // Power Saving Modes Enable +#define EPHY_SCR_PSMODE_M 0x00003000 // Power Saving Modes +#define EPHY_SCR_PSMODE_NORMAL 0x00000000 // Normal: Normal operation mode. + // PHY is fully functional +#define EPHY_SCR_PSMODE_LOWPWR 0x00001000 // IEEE Power Down +#define EPHY_SCR_PSMODE_ACTWOL 0x00002000 // Active Sleep +#define EPHY_SCR_PSMODE_PASWOL 0x00003000 // Passive Sleep +#define EPHY_SCR_SBPYASS 0x00000800 // Scrambler Bypass +#define EPHY_SCR_LBFIFO_M 0x00000300 // Loopback FIFO Depth +#define EPHY_SCR_LBFIFO_4 0x00000000 // Four nibble FIFO +#define EPHY_SCR_LBFIFO_5 0x00000100 // Five nibble FIFO +#define EPHY_SCR_LBFIFO_6 0x00000200 // Six nibble FIFO +#define EPHY_SCR_LBFIFO_8 0x00000300 // Eight nibble FIFO +#define EPHY_SCR_COLFDM 0x00000010 // Collision in Full-Duplex Mode +#define EPHY_SCR_TINT 0x00000004 // Test Interrupt +#define EPHY_SCR_INTEN 0x00000002 // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_MISR1 register. +// +//***************************************************************************** +#define EPHY_MISR1_LINKSTAT 0x00002000 // Change of Link Status Interrupt +#define EPHY_MISR1_SPEED 0x00001000 // Change of Speed Status Interrupt +#define EPHY_MISR1_DUPLEXM 0x00000800 // Change of Duplex Status + // Interrupt +#define EPHY_MISR1_ANC 0x00000400 // Auto-Negotiation Complete + // Interrupt +#define EPHY_MISR1_FCHF 0x00000200 // False Carrier Counter Half-Full + // Interrupt +#define EPHY_MISR1_RXHF 0x00000100 // Receive Error Counter Half-Full + // Interrupt +#define EPHY_MISR1_LINKSTATEN 0x00000020 // Link Status Interrupt Enable +#define EPHY_MISR1_SPEEDEN 0x00000010 // Speed Change Interrupt Enable +#define EPHY_MISR1_DUPLEXMEN 0x00000008 // Duplex Status Interrupt Enable +#define EPHY_MISR1_ANCEN 0x00000004 // Auto-Negotiation Complete + // Interrupt Enable +#define EPHY_MISR1_FCHFEN 0x00000002 // False Carrier Counter Register + // half-full Interrupt Enable +#define EPHY_MISR1_RXHFEN 0x00000001 // Receive Error Counter Register + // Half-Full Event Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_MISR2 register. +// +//***************************************************************************** +#define EPHY_MISR2_ANERR 0x00004000 // Auto-Negotiation Error Interrupt +#define EPHY_MISR2_PAGERX 0x00002000 // Page Receive Interrupt +#define EPHY_MISR2_LBFIFO 0x00001000 // Loopback FIFO Overflow/Underflow + // Event Interrupt +#define EPHY_MISR2_MDICO 0x00000800 // MDI/MDIX Crossover Status + // Changed Interrupt +#define EPHY_MISR2_SLEEP 0x00000400 // Sleep Mode Event Interrupt +#define EPHY_MISR2_POLINT 0x00000200 // Polarity Changed Interrupt +#define EPHY_MISR2_JABBER 0x00000100 // Jabber Detect Event Interrupt +#define EPHY_MISR2_ANERREN 0x00000040 // Auto-Negotiation Error Interrupt + // Enable +#define EPHY_MISR2_PAGERXEN 0x00000020 // Page Receive Interrupt Enable +#define EPHY_MISR2_LBFIFOEN 0x00000010 // Loopback FIFO Overflow/Underflow + // Interrupt Enable +#define EPHY_MISR2_MDICOEN 0x00000008 // MDI/MDIX Crossover Status + // Changed Interrupt Enable +#define EPHY_MISR2_SLEEPEN 0x00000004 // Sleep Mode Event Interrupt + // Enable +#define EPHY_MISR2_POLINTEN 0x00000002 // Polarity Changed Interrupt + // Enable +#define EPHY_MISR2_JABBEREN 0x00000001 // Jabber Detect Event Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_FCSCR register. +// +//***************************************************************************** +#define EPHY_FCSCR_FCSCNT_M 0x000000FF // False Carrier Event Counter +#define EPHY_FCSCR_FCSCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_RXERCNT register. +// +//***************************************************************************** +#define EPHY_RXERCNT_RXERRCNT_M 0x0000FFFF // Receive Error Count +#define EPHY_RXERCNT_RXERRCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_BISTCR register. +// +//***************************************************************************** +#define EPHY_BISTCR_PRBSM 0x00004000 // PRBS Single/Continuous Mode +#define EPHY_BISTCR_PRBSPKT 0x00002000 // Generated PRBS Packets +#define EPHY_BISTCR_PKTEN 0x00001000 // Packet Generation Enable +#define EPHY_BISTCR_PRBSCHKLK 0x00000800 // PRBS Checker Lock Indication +#define EPHY_BISTCR_PRBSCHKSYNC 0x00000400 // PRBS Checker Lock Sync Loss + // Indication +#define EPHY_BISTCR_PKTGENSTAT 0x00000200 // Packet Generator Status + // Indication +#define EPHY_BISTCR_PWRMODE 0x00000100 // Power Mode Indication +#define EPHY_BISTCR_TXMIILB 0x00000040 // Transmit Data in MII Loopback + // Mode +#define EPHY_BISTCR_LBMODE_M 0x0000001F // Loopback Mode Select +#define EPHY_BISTCR_LBMODE_NPCSIN \ + 0x00000001 // Near-end loopback: PCS Input + // Loopback +#define EPHY_BISTCR_LBMODE_NPCSOUT \ + 0x00000002 // Near-end loopback: PCS Output + // Loopback (In 100Base-TX only) +#define EPHY_BISTCR_LBMODE_NDIG 0x00000004 // Near-end loopback: Digital + // Loopback +#define EPHY_BISTCR_LBMODE_NANA 0x00000008 // Near-end loopback: Analog + // Loopback (requires 100 Ohm + // termination) +#define EPHY_BISTCR_LBMODE_FREV 0x00000010 // Far-end Loopback: Reverse + // Loopback + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_LEDCR register. +// +//***************************************************************************** +#define EPHY_LEDCR_BLINKRATE_M 0x00000600 // LED Blinking Rate (ON/OFF + // duration): +#define EPHY_LEDCR_BLINKRATE_20HZ \ + 0x00000000 // 20 Hz (50 ms) +#define EPHY_LEDCR_BLINKRATE_10HZ \ + 0x00000200 // 10 Hz (100 ms) +#define EPHY_LEDCR_BLINKRATE_5HZ \ + 0x00000400 // 5 Hz (200 ms) +#define EPHY_LEDCR_BLINKRATE_2HZ \ + 0x00000600 // 2 Hz (500 ms) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_CTL register. +// +//***************************************************************************** +#define EPHY_CTL_AUTOMDI 0x00008000 // Auto-MDIX Enable +#define EPHY_CTL_FORCEMDI 0x00004000 // Force MDIX +#define EPHY_CTL_PAUSERX 0x00002000 // Pause Receive Negotiated Status +#define EPHY_CTL_PAUSETX 0x00001000 // Pause Transmit Negotiated Status +#define EPHY_CTL_MIILNKSTAT 0x00000800 // MII Link Status +#define EPHY_CTL_BYPLEDSTRCH 0x00000080 // Bypass LED Stretching + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_10BTSC register. +// +//***************************************************************************** +#define EPHY_10BTSC_RXTHEN 0x00002000 // Lower Receiver Threshold Enable +#define EPHY_10BTSC_SQUELCH_M 0x00001E00 // Squelch Configuration +#define EPHY_10BTSC_NLPDIS 0x00000080 // Normal Link Pulse (NLP) + // Transmission Control +#define EPHY_10BTSC_POLSTAT 0x00000010 // 10 Mb Polarity Status +#define EPHY_10BTSC_JABBERD 0x00000001 // Jabber Disable +#define EPHY_10BTSC_SQUELCH_S 9 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_BICSR1 register. +// +//***************************************************************************** +#define EPHY_BICSR1_ERRCNT_M 0x0000FF00 // BIST Error Count +#define EPHY_BICSR1_IPGLENGTH_M 0x000000FF // BIST IPG Length +#define EPHY_BICSR1_ERRCNT_S 8 +#define EPHY_BICSR1_IPGLENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_BICSR2 register. +// +//***************************************************************************** +#define EPHY_BICSR2_PKTLENGTH_M 0x000007FF // BIST Packet Length +#define EPHY_BICSR2_PKTLENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_CDCR register. +// +//***************************************************************************** +#define EPHY_CDCR_START 0x00008000 // Cable Diagnostic Process Start +#define EPHY_CDCR_LINKQUAL_M 0x00000300 // Link Quality Indication +#define EPHY_CDCR_LINKQUAL_GOOD 0x00000100 // Good Quality Link Indication +#define EPHY_CDCR_LINKQUAL_MILD 0x00000200 // Mid- Quality Link Indication +#define EPHY_CDCR_LINKQUAL_POOR 0x00000300 // Poor Quality Link Indication +#define EPHY_CDCR_DONE 0x00000002 // Cable Diagnostic Process Done +#define EPHY_CDCR_FAIL 0x00000001 // Cable Diagnostic Process Fail + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_RCR register. +// +//***************************************************************************** +#define EPHY_RCR_SWRST 0x00008000 // Software Reset +#define EPHY_RCR_SWRESTART 0x00004000 // Software Restart + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPHY_LEDCFG register. +// +//***************************************************************************** +#define EPHY_LEDCFG_LED2_M 0x00000F00 // LED2 Configuration +#define EPHY_LEDCFG_LED2_LINK 0x00000000 // Link OK +#define EPHY_LEDCFG_LED2_RXTX 0x00000100 // RX/TX Activity +#define EPHY_LEDCFG_LED2_TX 0x00000200 // TX Activity +#define EPHY_LEDCFG_LED2_RX 0x00000300 // RX Activity +#define EPHY_LEDCFG_LED2_COL 0x00000400 // Collision +#define EPHY_LEDCFG_LED2_100BT 0x00000500 // 100-Base TX +#define EPHY_LEDCFG_LED2_10BT 0x00000600 // 10-Base TX +#define EPHY_LEDCFG_LED2_FD 0x00000700 // Full Duplex +#define EPHY_LEDCFG_LED2_LINKTXRX \ + 0x00000800 // Link OK/Blink on TX/RX Activity +#define EPHY_LEDCFG_LED1_M 0x000000F0 // LED1 Configuration +#define EPHY_LEDCFG_LED1_LINK 0x00000000 // Link OK +#define EPHY_LEDCFG_LED1_RXTX 0x00000010 // RX/TX Activity +#define EPHY_LEDCFG_LED1_TX 0x00000020 // TX Activity +#define EPHY_LEDCFG_LED1_RX 0x00000030 // RX Activity +#define EPHY_LEDCFG_LED1_COL 0x00000040 // Collision +#define EPHY_LEDCFG_LED1_100BT 0x00000050 // 100-Base TX +#define EPHY_LEDCFG_LED1_10BT 0x00000060 // 10-Base TX +#define EPHY_LEDCFG_LED1_FD 0x00000070 // Full Duplex +#define EPHY_LEDCFG_LED1_LINKTXRX \ + 0x00000080 // Link OK/Blink on TX/RX Activity +#define EPHY_LEDCFG_LED0_M 0x0000000F // LED0 Configuration +#define EPHY_LEDCFG_LED0_LINK 0x00000000 // Link OK +#define EPHY_LEDCFG_LED0_RXTX 0x00000001 // RX/TX Activity +#define EPHY_LEDCFG_LED0_TX 0x00000002 // TX Activity +#define EPHY_LEDCFG_LED0_RX 0x00000003 // RX Activity +#define EPHY_LEDCFG_LED0_COL 0x00000004 // Collision +#define EPHY_LEDCFG_LED0_100BT 0x00000005 // 100-Base TX +#define EPHY_LEDCFG_LED0_10BT 0x00000006 // 10-Base TX +#define EPHY_LEDCFG_LED0_FD 0x00000007 // Full Duplex +#define EPHY_LEDCFG_LED0_LINKTXRX \ + 0x00000008 // Link OK/Blink on TX/RX Activity + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// EMAC_O_PPSCTRL register. +// +//***************************************************************************** +#define EMAC_PPSCTRL_PPSCTRL_1HZ \ + 0x00000000 // When the PPSEN0 bit = 0x0, the + // EN0PPS signal is 1 pulse of the + // PTP reference clock.(of width + // clk_ptp_i) every second +#define EMAC_PPSCTRL_PPSCTRL_2HZ \ + 0x00000001 // When the PPSEN0 bit = 0x0, the + // binary rollover is 2 Hz, and the + // digital rollover is 1 Hz +#define EMAC_PPSCTRL_PPSCTRL_4HZ \ + 0x00000002 // When the PPSEN0 bit = 0x0, the + // binary rollover is 4 Hz, and the + // digital rollover is 2 Hz +#define EMAC_PPSCTRL_PPSCTRL_8HZ \ + 0x00000003 // When thePPSEN0 bit = 0x0, the + // binary rollover is 8 Hz, and the + // digital rollover is 4 Hz, +#define EMAC_PPSCTRL_PPSCTRL_16HZ \ + 0x00000004 // When thePPSEN0 bit = 0x0, the + // binary rollover is 16 Hz, and + // the digital rollover is 8 Hz +#define EMAC_PPSCTRL_PPSCTRL_32HZ \ + 0x00000005 // When thePPSEN0 bit = 0x0, the + // binary rollover is 32 Hz, and + // the digital rollover is 16 Hz +#define EMAC_PPSCTRL_PPSCTRL_64HZ \ + 0x00000006 // When thePPSEN0 bit = 0x0, the + // binary rollover is 64 Hz, and + // the digital rollover is 32 Hz +#define EMAC_PPSCTRL_PPSCTRL_128HZ \ + 0x00000007 // When thePPSEN0 bit = 0x0, the + // binary rollover is 128 Hz, and + // the digital rollover is 64 Hz +#define EMAC_PPSCTRL_PPSCTRL_256HZ \ + 0x00000008 // When thePPSEN0 bit = 0x0, the + // binary rollover is 256 Hz, and + // the digital rollover is 128 Hz +#define EMAC_PPSCTRL_PPSCTRL_512HZ \ + 0x00000009 // When thePPSEN0 bit = 0x0, the + // binary rollover is 512 Hz, and + // the digital rollover is 256 Hz +#define EMAC_PPSCTRL_PPSCTRL_1024HZ \ + 0x0000000A // When the PPSEN0 bit = 0x0, the + // binary rollover is 1.024 kHz, + // and the digital rollover is 512 + // Hz +#define EMAC_PPSCTRL_PPSCTRL_2048HZ \ + 0x0000000B // When thePPSEN0 bit = 0x0, the + // binary rollover is 2.048 kHz, + // and the digital rollover is + // 1.024 kHz +#define EMAC_PPSCTRL_PPSCTRL_4096HZ \ + 0x0000000C // When thePPSEN0 bit = 0x0, the + // binary rollover is 4.096 kHz, + // and the digital rollover is + // 2.048 kHz +#define EMAC_PPSCTRL_PPSCTRL_8192HZ \ + 0x0000000D // When thePPSEN0 bit = 0x0, the + // binary rollover is 8.192 kHz, + // and the digital rollover is + // 4.096 kHz +#define EMAC_PPSCTRL_PPSCTRL_16384HZ \ + 0x0000000E // When thePPSEN0 bit = 0x0, the + // binary rollover is 16.384 kHz, + // and the digital rollover is + // 8.092 kHz +#define EMAC_PPSCTRL_PPSCTRL_32768HZ \ + 0x0000000F // When thePPSEN0 bit = 0x0, the + // binary rollover is 32.768 KHz, + // and the digital rollover is + // 16.384 KHz + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the EMAC_O_CC +// register. +// +//***************************************************************************** +#define EMAC_CC_CS_PA7 0x00000001 // GPIO + +#endif + +#endif // __HW_EMAC_H__ diff --git a/os/common/ext/TivaWare/inc/hw_epi.h b/os/common/ext/TivaWare/inc/hw_epi.h new file mode 100644 index 0000000..54b59c3 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_epi.h @@ -0,0 +1,933 @@ +//***************************************************************************** +// +// hw_epi.h - Macros for use in accessing the EPI registers. +// +// Copyright (c) 2008-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_EPI_H__ +#define __HW_EPI_H__ + +//***************************************************************************** +// +// The following are defines for the External Peripheral Interface register +// offsets. +// +//***************************************************************************** +#define EPI_O_CFG 0x00000000 // EPI Configuration +#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate +#define EPI_O_BAUD2 0x00000008 // EPI Main Baud Rate +#define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration +#define EPI_O_GPCFG 0x00000010 // EPI General-Purpose + // Configuration +#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration +#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration +#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2 +#define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2 +#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map +#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0 +#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0 +#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0 +#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1 +#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1 +#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1 +#define EPI_O_STAT 0x00000060 // EPI Status +#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count +#define EPI_O_READFIFO0 0x00000070 // EPI Read FIFO +#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1 +#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2 +#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3 +#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4 +#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5 +#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6 +#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7 +#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects +#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count +#define EPI_O_DMATXCNT 0x00000208 // EPI DMA Transmit Count +#define EPI_O_IM 0x00000210 // EPI Interrupt Mask +#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status +#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status +#define EPI_O_EISC 0x0000021C // EPI Error and Interrupt Status + // and Clear +#define EPI_O_HB8CFG3 0x00000308 // EPI Host-Bus 8 Configuration 3 +#define EPI_O_HB16CFG3 0x00000308 // EPI Host-Bus 16 Configuration 3 +#define EPI_O_HB16CFG4 0x0000030C // EPI Host-Bus 16 Configuration 4 +#define EPI_O_HB8CFG4 0x0000030C // EPI Host-Bus 8 Configuration 4 +#define EPI_O_HB8TIME 0x00000310 // EPI Host-Bus 8 Timing Extension +#define EPI_O_HB16TIME 0x00000310 // EPI Host-Bus 16 Timing Extension +#define EPI_O_HB8TIME2 0x00000314 // EPI Host-Bus 8 Timing Extension +#define EPI_O_HB16TIME2 0x00000314 // EPI Host-Bus 16 Timing Extension +#define EPI_O_HB16TIME3 0x00000318 // EPI Host-Bus 16 Timing Extension +#define EPI_O_HB8TIME3 0x00000318 // EPI Host-Bus 8 Timing Extension +#define EPI_O_HB8TIME4 0x0000031C // EPI Host-Bus 8 Timing Extension +#define EPI_O_HB16TIME4 0x0000031C // EPI Host-Bus 16 Timing Extension +#define EPI_O_HBPSRAM 0x00000360 // EPI Host-Bus PSRAM + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_CFG register. +// +//***************************************************************************** +#define EPI_CFG_INTDIV 0x00000100 // Integer Clock Divider Enable +#define EPI_CFG_BLKEN 0x00000010 // Block Enable +#define EPI_CFG_MODE_M 0x0000000F // Mode Select +#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose +#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM +#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8) +#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_BAUD register. +// +//***************************************************************************** +#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1 +#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0 +#define EPI_BAUD_COUNT1_S 16 +#define EPI_BAUD_COUNT0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_BAUD2 register. +// +//***************************************************************************** +#define EPI_BAUD2_COUNT1_M 0xFFFF0000 // CS3n Baud Rate Counter 1 +#define EPI_BAUD2_COUNT0_M 0x0000FFFF // CS2n Baud Rate Counter 0 +#define EPI_BAUD2_COUNT1_S 16 +#define EPI_BAUD2_COUNT0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16CFG register. +// +//***************************************************************************** +#define EPI_HB16CFG_CLKGATE 0x80000000 // Clock Gated +#define EPI_HB16CFG_CLKGATEI 0x40000000 // Clock Gated Idle +#define EPI_HB16CFG_CLKINV 0x20000000 // Invert Output Clock Enable +#define EPI_HB16CFG_RDYEN 0x10000000 // Input Ready Enable +#define EPI_HB16CFG_IRDYINV 0x08000000 // Input Ready Invert +#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable +#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable +#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity +#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity +#define EPI_HB16CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity +#define EPI_HB16CFG_WRCRE 0x00040000 // PSRAM Configuration Register + // Write +#define EPI_HB16CFG_RDCRE 0x00020000 // PSRAM Configuration Register + // Read +#define EPI_HB16CFG_BURST 0x00010000 // Burst Mode +#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait +#define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States +#define EPI_HB16CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB16CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB16CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB16CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States +#define EPI_HB16CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB16CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB16CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB16CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration +#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode +#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] +#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0] +#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0] +#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0] +#define EPI_HB16CFG_MAXWAIT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_GPCFG register. +// +//***************************************************************************** +#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin +#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated +#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame +#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count +#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes +#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size +#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address +#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide +#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size + // cannot be used with 24-bit data +#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size + // cannot be used with data sizes + // other than 8 +#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus +#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7) +#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15) +#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23) +#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31) +#define EPI_GPCFG_FRMCNT_S 22 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_SDRAMCFG register. +// +//***************************************************************************** +#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range +#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz +#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz +#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz +#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter +#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode +#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM +#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB) +#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB) +#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB) +#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB) +#define EPI_SDRAMCFG_RFSH_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8CFG register. +// +//***************************************************************************** +#define EPI_HB8CFG_CLKGATE 0x80000000 // Clock Gated +#define EPI_HB8CFG_CLKGATEI 0x40000000 // Clock Gated when Idle +#define EPI_HB8CFG_CLKINV 0x20000000 // Invert Output Clock Enable +#define EPI_HB8CFG_RDYEN 0x10000000 // Input Ready Enable +#define EPI_HB8CFG_IRDYINV 0x08000000 // Input Ready Invert +#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable +#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable +#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity +#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity +#define EPI_HB8CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity +#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait +#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States +#define EPI_HB8CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB8CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB8CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB8CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States +#define EPI_HB8CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB8CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB8CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB8CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode +#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0] +#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0] +#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0] +#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0] +#define EPI_HB8CFG_MAXWAIT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8CFG2 register. +// +//***************************************************************************** +#define EPI_HB8CFG2_CSCFGEXT 0x08000000 // Chip Select Extended + // Configuration +#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and + // Multiple Sub-Mode Configuration + // enable +#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration +#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration +#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration +#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration +#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration +#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity +#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity +#define EPI_HB8CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity +#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States +#define EPI_HB8CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB8CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB8CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB8CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States +#define EPI_HB8CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB8CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB8CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB8CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB8CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode +#define EPI_HB8CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] +#define EPI_HB8CFG2_MODE_AD 0x00000001 // ADNONMUX - D[7:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16CFG2 register. +// +//***************************************************************************** +#define EPI_HB16CFG2_CSCFGEXT 0x08000000 // Chip Select Extended + // Configuration +#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and + // Multiple Sub-Mode Configuration + // enable +#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration +#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration +#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration +#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration +#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration +#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity +#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity +#define EPI_HB16CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity +#define EPI_HB16CFG2_WRCRE 0x00040000 // CS1n PSRAM Configuration + // Register Write +#define EPI_HB16CFG2_RDCRE 0x00020000 // CS1n PSRAM Configuration + // Register Read +#define EPI_HB16CFG2_BURST 0x00010000 // CS1n Burst Mode +#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States +#define EPI_HB16CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB16CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB16CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB16CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States +#define EPI_HB16CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB16CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB16CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB16CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB16CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode +#define EPI_HB16CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] +#define EPI_HB16CFG2_MODE_AD 0x00000001 // ADNONMUX - D[15:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_ADDRMAP register. +// +//***************************************************************************** +#define EPI_ADDRMAP_ECSZ_M 0x00000C00 // External Code Size +#define EPI_ADDRMAP_ECSZ_256B 0x00000000 // 256 bytes; lower address range: + // 0x00 to 0xFF +#define EPI_ADDRMAP_ECSZ_64KB 0x00000400 // 64 KB; lower address range: + // 0x0000 to 0xFFFF +#define EPI_ADDRMAP_ECSZ_16MB 0x00000800 // 16 MB; lower address range: + // 0x00.0000 to 0xFF.FFFF +#define EPI_ADDRMAP_ECSZ_256MB 0x00000C00 // 256MB; lower address range: + // 0x000.0000 to 0x0FFF.FFFF +#define EPI_ADDRMAP_ECADR_M 0x00000300 // External Code Address +#define EPI_ADDRMAP_ECADR_NONE 0x00000000 // Not mapped +#define EPI_ADDRMAP_ECADR_1000 0x00000100 // At 0x1000.0000 +#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size +#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range: + // 0x00 to 0xFF +#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range: + // 0x0000 to 0xFFFF +#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range: + // 0x00.0000 to 0xFF.FFFF +#define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range: + // 0x000.0000 to 0xFFF.FFFF +#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address +#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped +#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000 +#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000 +#define EPI_ADDRMAP_EPADR_HBQS 0x00000030 // Only to be used with Host Bus + // quad chip select. In quad chip + // select mode, CS2n maps to + // 0xA000.0000 and CS3n maps to + // 0xC000.0000 +#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size +#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range: + // 0x00 to 0xFF +#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range: + // 0x0000 to 0xFFFF +#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range: + // 0x00.0000 to 0xFF.FFFF +#define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range: + // 0x000.0000 to 0xFFF.FFFF +#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address +#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped +#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000 +#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000 +#define EPI_ADDRMAP_ERADR_HBQS 0x00000003 // Only to be used with Host Bus + // quad chip select. In quad chip + // select mode, CS0n maps to + // 0x6000.0000 and CS1n maps to + // 0x8000.0000 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RSIZE0 register. +// +//***************************************************************************** +#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size +#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits) +#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits) +#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RADDR0 register. +// +//***************************************************************************** +#define EPI_RADDR0_ADDR_M 0xFFFFFFFF // Current Address +#define EPI_RADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RPSTD0 register. +// +//***************************************************************************** +#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count +#define EPI_RPSTD0_POSTCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RSIZE1 register. +// +//***************************************************************************** +#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size +#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits) +#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits) +#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits) + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RADDR1 register. +// +//***************************************************************************** +#define EPI_RADDR1_ADDR_M 0xFFFFFFFF // Current Address +#define EPI_RADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RPSTD1 register. +// +//***************************************************************************** +#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count +#define EPI_RPSTD1_POSTCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_STAT register. +// +//***************************************************************************** +#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full +#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty +#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence +#define EPI_STAT_WBUSY 0x00000020 // Write Busy +#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy +#define EPI_STAT_ACTIVE 0x00000001 // Register Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RFIFOCNT register. +// +//***************************************************************************** +#define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count +#define EPI_RFIFOCNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO0 +// register. +// +//***************************************************************************** +#define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO1 +// register. +// +//***************************************************************************** +#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO2 +// register. +// +//***************************************************************************** +#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO3 +// register. +// +//***************************************************************************** +#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO4 +// register. +// +//***************************************************************************** +#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO4_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO5 +// register. +// +//***************************************************************************** +#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO5_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO6 +// register. +// +//***************************************************************************** +#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO6_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_READFIFO7 +// register. +// +//***************************************************************************** +#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data +#define EPI_READFIFO7_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_FIFOLVL register. +// +//***************************************************************************** +#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error +#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error +#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO +#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Interrupt is triggered while + // WRFIFO is empty. +#define EPI_FIFOLVL_WRFIFO_2 0x00000020 // Interrupt is triggered until + // there are only two slots + // available. Thus, trigger is + // deasserted when there are two + // WRFIFO entries present. This + // configuration is optimized for + // bursts of 2 +#define EPI_FIFOLVL_WRFIFO_1 0x00000030 // Interrupt is triggered until + // there is one WRFIFO entry + // available. This configuration + // expects only single writes +#define EPI_FIFOLVL_WRFIFO_NFULL \ + 0x00000040 // Trigger interrupt when WRFIFO is + // not full, meaning trigger will + // continue to assert until there + // are four entries in the WRFIFO +#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO +#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty +#define EPI_FIFOLVL_RDFIFO_1 0x00000001 // Trigger when there are 1 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_2 0x00000002 // Trigger when there are 2 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_4 0x00000003 // Trigger when there are 4 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_6 0x00000004 // Trigger when there are 6 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_7 0x00000005 // Trigger when there are 7 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_8 0x00000006 // Trigger when there are 8 entries + // in the NBRFIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_WFIFOCNT register. +// +//***************************************************************************** +#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions +#define EPI_WFIFOCNT_WTAV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_DMATXCNT register. +// +//***************************************************************************** +#define EPI_DMATXCNT_TXCNT_M 0x0000FFFF // DMA Count +#define EPI_DMATXCNT_TXCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_IM register. +// +//***************************************************************************** +#define EPI_IM_DMAWRIM 0x00000010 // Write uDMA Interrupt Mask +#define EPI_IM_DMARDIM 0x00000008 // Read uDMA Interrupt Mask +#define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask +#define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask +#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_RIS register. +// +//***************************************************************************** +#define EPI_RIS_DMAWRRIS 0x00000010 // Write uDMA Raw Interrupt Status +#define EPI_RIS_DMARDRIS 0x00000008 // Read uDMA Raw Interrupt Status +#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status +#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status +#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_MIS register. +// +//***************************************************************************** +#define EPI_MIS_DMAWRMIS 0x00000010 // Write uDMA Masked Interrupt + // Status +#define EPI_MIS_DMARDMIS 0x00000008 // Read uDMA Masked Interrupt + // Status +#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status +#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status +#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_EISC register. +// +//***************************************************************************** +#define EPI_EISC_DMAWRIC 0x00000010 // Write uDMA Interrupt Clear +#define EPI_EISC_DMARDIC 0x00000008 // Read uDMA Interrupt Clear +#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error +#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error +#define EPI_EISC_TOUT 0x00000001 // Timeout Error + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8CFG3 register. +// +//***************************************************************************** +#define EPI_HB8CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity +#define EPI_HB8CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity +#define EPI_HB8CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity +#define EPI_HB8CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States +#define EPI_HB8CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB8CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB8CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB8CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB8CFG3_RDWS_M 0x00000030 // CS2n Read Wait States +#define EPI_HB8CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB8CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB8CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB8CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB8CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode +#define EPI_HB8CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] +#define EPI_HB8CFG3_MODE_AD 0x00000001 // ADNONMUX - D[7:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16CFG3 register. +// +//***************************************************************************** +#define EPI_HB16CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity +#define EPI_HB16CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity +#define EPI_HB16CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity +#define EPI_HB16CFG3_WRCRE 0x00040000 // CS2n PSRAM Configuration + // Register Write +#define EPI_HB16CFG3_RDCRE 0x00020000 // CS2n PSRAM Configuration + // Register Read +#define EPI_HB16CFG3_BURST 0x00010000 // CS2n Burst Mode +#define EPI_HB16CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States +#define EPI_HB16CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB16CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB16CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB16CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB16CFG3_RDWS_M 0x00000030 // CS2n Read Wait States +#define EPI_HB16CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB16CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB16CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB16CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB16CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode +#define EPI_HB16CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] +#define EPI_HB16CFG3_MODE_AD 0x00000001 // ADNONMUX - D[15:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16CFG4 register. +// +//***************************************************************************** +#define EPI_HB16CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity +#define EPI_HB16CFG4_RDHIGH 0x00100000 // CS3n READ Strobe Polarity +#define EPI_HB16CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity +#define EPI_HB16CFG4_WRCRE 0x00040000 // CS3n PSRAM Configuration + // Register Write +#define EPI_HB16CFG4_RDCRE 0x00020000 // CS3n PSRAM Configuration + // Register Read +#define EPI_HB16CFG4_BURST 0x00010000 // CS3n Burst Mode +#define EPI_HB16CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States +#define EPI_HB16CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB16CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB16CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB16CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB16CFG4_RDWS_M 0x00000030 // CS3n Read Wait States +#define EPI_HB16CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB16CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB16CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB16CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB16CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode +#define EPI_HB16CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] +#define EPI_HB16CFG4_MODE_AD 0x00000001 // ADNONMUX - D[15:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8CFG4 register. +// +//***************************************************************************** +#define EPI_HB8CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity +#define EPI_HB8CFG4_RDHIGH 0x00100000 // CS2n READ Strobe Polarity +#define EPI_HB8CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity +#define EPI_HB8CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States +#define EPI_HB8CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks +#define EPI_HB8CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks +#define EPI_HB8CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks +#define EPI_HB8CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks +#define EPI_HB8CFG4_RDWS_M 0x00000030 // CS3n Read Wait States +#define EPI_HB8CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks +#define EPI_HB8CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks +#define EPI_HB8CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks +#define EPI_HB8CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks +#define EPI_HB8CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode +#define EPI_HB8CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0] +#define EPI_HB8CFG4_MODE_AD 0x00000001 // ADNONMUX - D[7:0] + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8TIME register. +// +//***************************************************************************** +#define EPI_HB8TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay +#define EPI_HB8TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture + // Width +#define EPI_HB8TIME_WRWSM 0x00000010 // Write Wait State Minus One +#define EPI_HB8TIME_RDWSM 0x00000001 // Read Wait State Minus One +#define EPI_HB8TIME_IRDYDLY_S 24 +#define EPI_HB8TIME_CAPWIDTH_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16TIME register. +// +//***************************************************************************** +#define EPI_HB16TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay +#define EPI_HB16TIME_PSRAMSZ_M 0x00070000 // PSRAM Row Size +#define EPI_HB16TIME_PSRAMSZ_0 0x00000000 // No row size limitation +#define EPI_HB16TIME_PSRAMSZ_128B \ + 0x00010000 // 128 B +#define EPI_HB16TIME_PSRAMSZ_256B \ + 0x00020000 // 256 B +#define EPI_HB16TIME_PSRAMSZ_512B \ + 0x00030000 // 512 B +#define EPI_HB16TIME_PSRAMSZ_1KB \ + 0x00040000 // 1024 B +#define EPI_HB16TIME_PSRAMSZ_2KB \ + 0x00050000 // 2048 B +#define EPI_HB16TIME_PSRAMSZ_4KB \ + 0x00060000 // 4096 B +#define EPI_HB16TIME_PSRAMSZ_8KB \ + 0x00070000 // 8192 B +#define EPI_HB16TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture + // Width +#define EPI_HB16TIME_WRWSM 0x00000010 // Write Wait State Minus One +#define EPI_HB16TIME_RDWSM 0x00000001 // Read Wait State Minus One +#define EPI_HB16TIME_IRDYDLY_S 24 +#define EPI_HB16TIME_CAPWIDTH_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8TIME2 register. +// +//***************************************************************************** +#define EPI_HB8TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay +#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000 // CS1n Inter-transfer Capture + // Width +#define EPI_HB8TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One +#define EPI_HB8TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One +#define EPI_HB8TIME2_IRDYDLY_S 24 +#define EPI_HB8TIME2_CAPWIDTH_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16TIME2 +// register. +// +//***************************************************************************** +#define EPI_HB16TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay +#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000 // PSRAM Row Size +#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000 // No row size limitation +#define EPI_HB16TIME2_PSRAMSZ_128B \ + 0x00010000 // 128 B +#define EPI_HB16TIME2_PSRAMSZ_256B \ + 0x00020000 // 256 B +#define EPI_HB16TIME2_PSRAMSZ_512B \ + 0x00030000 // 512 B +#define EPI_HB16TIME2_PSRAMSZ_1KB \ + 0x00040000 // 1024 B +#define EPI_HB16TIME2_PSRAMSZ_2KB \ + 0x00050000 // 2048 B +#define EPI_HB16TIME2_PSRAMSZ_4KB \ + 0x00060000 // 4096 B +#define EPI_HB16TIME2_PSRAMSZ_8KB \ + 0x00070000 // 8192 B +#define EPI_HB16TIME2_CAPWIDTH_M \ + 0x00003000 // CS1n Inter-transfer Capture + // Width +#define EPI_HB16TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One +#define EPI_HB16TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One +#define EPI_HB16TIME2_IRDYDLY_S 24 +#define EPI_HB16TIME2_CAPWIDTH_S \ + 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16TIME3 +// register. +// +//***************************************************************************** +#define EPI_HB16TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay +#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000 // PSRAM Row Size +#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000 // No row size limitation +#define EPI_HB16TIME3_PSRAMSZ_128B \ + 0x00010000 // 128 B +#define EPI_HB16TIME3_PSRAMSZ_256B \ + 0x00020000 // 256 B +#define EPI_HB16TIME3_PSRAMSZ_512B \ + 0x00030000 // 512 B +#define EPI_HB16TIME3_PSRAMSZ_1KB \ + 0x00040000 // 1024 B +#define EPI_HB16TIME3_PSRAMSZ_2KB \ + 0x00050000 // 2048 B +#define EPI_HB16TIME3_PSRAMSZ_4KB \ + 0x00060000 // 4096 B +#define EPI_HB16TIME3_PSRAMSZ_8KB \ + 0x00070000 // 8192 B +#define EPI_HB16TIME3_CAPWIDTH_M \ + 0x00003000 // CS2n Inter-transfer Capture + // Width +#define EPI_HB16TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One +#define EPI_HB16TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One +#define EPI_HB16TIME3_IRDYDLY_S 24 +#define EPI_HB16TIME3_CAPWIDTH_S \ + 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8TIME3 register. +// +//***************************************************************************** +#define EPI_HB8TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay +#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000 // CS2n Inter-transfer Capture + // Width +#define EPI_HB8TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One +#define EPI_HB8TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One +#define EPI_HB8TIME3_IRDYDLY_S 24 +#define EPI_HB8TIME3_CAPWIDTH_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB8TIME4 register. +// +//***************************************************************************** +#define EPI_HB8TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay +#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000 // CS3n Inter-transfer Capture + // Width +#define EPI_HB8TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One +#define EPI_HB8TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One +#define EPI_HB8TIME4_IRDYDLY_S 24 +#define EPI_HB8TIME4_CAPWIDTH_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HB16TIME4 +// register. +// +//***************************************************************************** +#define EPI_HB16TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay +#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000 // PSRAM Row Size +#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000 // No row size limitation +#define EPI_HB16TIME4_PSRAMSZ_128B \ + 0x00010000 // 128 B +#define EPI_HB16TIME4_PSRAMSZ_256B \ + 0x00020000 // 256 B +#define EPI_HB16TIME4_PSRAMSZ_512B \ + 0x00030000 // 512 B +#define EPI_HB16TIME4_PSRAMSZ_1KB \ + 0x00040000 // 1024 B +#define EPI_HB16TIME4_PSRAMSZ_2KB \ + 0x00050000 // 2048 B +#define EPI_HB16TIME4_PSRAMSZ_4KB \ + 0x00060000 // 4096 B +#define EPI_HB16TIME4_PSRAMSZ_8KB \ + 0x00070000 // 8192 B +#define EPI_HB16TIME4_CAPWIDTH_M \ + 0x00003000 // CS3n Inter-transfer Capture + // Width +#define EPI_HB16TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One +#define EPI_HB16TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One +#define EPI_HB16TIME4_IRDYDLY_S 24 +#define EPI_HB16TIME4_CAPWIDTH_S \ + 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EPI_O_HBPSRAM register. +// +//***************************************************************************** +#define EPI_HBPSRAM_CR_M 0x001FFFFF // PSRAM Config Register +#define EPI_HBPSRAM_CR_S 0 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the EPI_O_FIFOLVL +// register. +// +//***************************************************************************** +#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are up to 3 + // spaces available in the WFIFO +#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are up to 2 + // spaces available in the WFIFO +#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space + // available in the WFIFO +#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more + // entries in the NBRFIFO +#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries + // in the NBRFIFO + +#endif + +#endif // __HW_EPI_H__ diff --git a/os/common/ext/TivaWare/inc/hw_fan.h b/os/common/ext/TivaWare/inc/hw_fan.h new file mode 100644 index 0000000..089a8ea --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_fan.h @@ -0,0 +1,49 @@ +//***************************************************************************** +// +// hw_fan.h - Macros used when accessing the fan control hardware. +// +// Copyright (c) 2010-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_FAN_H__ +#define __HW_FAN_H__ + +//***************************************************************************** +// +// The following are defines for the Fan Control register offsets. +// +//***************************************************************************** + +#endif // __HW_FAN_H__ diff --git a/os/common/ext/TivaWare/inc/hw_flash.h b/os/common/ext/TivaWare/inc/hw_flash.h new file mode 100644 index 0000000..0133b35 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_flash.h @@ -0,0 +1,625 @@ +//***************************************************************************** +// +// hw_flash.h - Macros used when accessing the flash controller. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// The following are defines for the FLASH register offsets. +// +//***************************************************************************** +#define FLASH_FMA 0x400FD000 // Flash Memory Address +#define FLASH_FMD 0x400FD004 // Flash Memory Data +#define FLASH_FMC 0x400FD008 // Flash Memory Control +#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt + // Status +#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask +#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked + // Interrupt Status and Clear +#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2 +#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid +#define FLASH_FLPEKEY 0x400FD03C // Flash Program/Erase Key +#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n +#define FLASH_PP 0x400FDFC0 // Flash Peripheral Properties +#define FLASH_FSIZE 0x400FDFC0 // Flash Size +#define FLASH_SSIZE 0x400FDFC4 // SRAM Size +#define FLASH_CONF 0x400FDFC8 // Flash Configuration Register +#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map +#define FLASH_DMASZ 0x400FDFD0 // Flash DMA Address Size +#define FLASH_DMAST 0x400FDFD4 // Flash DMA Starting Address +#define FLASH_RVP 0x400FE0D4 // Reset Vector Pointer +#define FLASH_RMCTL 0x400FE0F0 // ROM Control +#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration +#define FLASH_USERREG0 0x400FE1E0 // User Register 0 +#define FLASH_USERREG1 0x400FE1E4 // User Register 1 +#define FLASH_USERREG2 0x400FE1E8 // User Register 2 +#define FLASH_USERREG3 0x400FE1EC // User Register 3 +#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read + // Enable 0 +#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read + // Enable 1 +#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read + // Enable 2 +#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read + // Enable 3 +#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read + // Enable 4 +#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read + // Enable 5 +#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read + // Enable 6 +#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read + // Enable 7 +#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read + // Enable 8 +#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read + // Enable 9 +#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read + // Enable 10 +#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read + // Enable 11 +#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read + // Enable 12 +#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read + // Enable 13 +#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read + // Enable 14 +#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read + // Enable 15 +#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program + // Enable 0 +#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program + // Enable 1 +#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program + // Enable 2 +#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program + // Enable 3 +#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program + // Enable 4 +#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program + // Enable 5 +#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program + // Enable 6 +#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program + // Enable 7 +#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program + // Enable 8 +#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program + // Enable 9 +#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program + // Enable 10 +#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program + // Enable 11 +#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program + // Enable 12 +#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program + // Enable 13 +#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program + // Enable 14 +#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program + // Enable 15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMA register. +// +//***************************************************************************** +#define FLASH_FMA_OFFSET_M 0x000FFFFF // Address Offset +#define FLASH_FMA_OFFSET_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMD register. +// +//***************************************************************************** +#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value +#define FLASH_FMD_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit Register Value +#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory +#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory +#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw + // Interrupt Status +#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt + // Status +#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt + // Status +#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt + // Status +#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status +#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status +#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask +#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask +#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask +#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask +#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask +#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCMISC register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and + // Clear +#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC2 register. +// +//***************************************************************************** +#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBVAL register. +// +//***************************************************************************** +#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FLPEKEY register. +// +//***************************************************************************** +#define FLASH_FLPEKEY_PEKEY_M 0x0000FFFF // Key Value +#define FLASH_FLPEKEY_PEKEY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBN register. +// +//***************************************************************************** +#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_PP register. +// +//***************************************************************************** +#define FLASH_PP_PFC 0x40000000 // Prefetch Buffer Mode +#define FLASH_PP_FMM 0x20000000 // Flash Mirror Mode +#define FLASH_PP_DFA 0x10000000 // DMA Flash Access +#define FLASH_PP_EESS_M 0x00780000 // EEPROM Sector Size of the + // physical bank +#define FLASH_PP_EESS_1KB 0x00000000 // 1 KB +#define FLASH_PP_EESS_2KB 0x00080000 // 2 KB +#define FLASH_PP_EESS_4KB 0x00100000 // 4 KB +#define FLASH_PP_EESS_8KB 0x00180000 // 8 KB +#define FLASH_PP_MAINSS_M 0x00070000 // Flash Sector Size of the + // physical bank +#define FLASH_PP_MAINSS_1KB 0x00000000 // 1 KB +#define FLASH_PP_MAINSS_2KB 0x00010000 // 2 KB +#define FLASH_PP_MAINSS_4KB 0x00020000 // 4 KB +#define FLASH_PP_MAINSS_8KB 0x00030000 // 8 KB +#define FLASH_PP_MAINSS_16KB 0x00040000 // 16 KB +#define FLASH_PP_SIZE_M 0x0000FFFF // Flash Size +#define FLASH_PP_SIZE_512KB 0x000000FF // 512 KB of Flash +#define FLASH_PP_SIZE_1MB 0x000001FF // 1024 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FSIZE register. +// +//***************************************************************************** +#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size +#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash +#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash +#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash +#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_SSIZE register. +// +//***************************************************************************** +#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size +#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM +#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM +#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM +#define FLASH_SSIZE_SIZE_256KB 0x000003FF // 256 KB of SRAM + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CONF register. +// +//***************************************************************************** +#define FLASH_CONF_FMME 0x40000000 // Flash Mirror Mode Enable +#define FLASH_CONF_SPFE 0x20000000 // Single Prefetch Mode Enable +#define FLASH_CONF_CLRTV 0x00100000 // Clear Valid Tags +#define FLASH_CONF_FPFON 0x00020000 // Force Prefetch On +#define FLASH_CONF_FPFOFF 0x00010000 // Force Prefetch Off + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_ROMSWMAP register. +// +//***************************************************************************** +#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present +#define FLASH_ROMSWMAP_SW0EN_M 0x00000003 // ROM SW Region 0 Availability +#define FLASH_ROMSWMAP_SW0EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW0EN_CORE \ + 0x00000001 // Region available to core +#define FLASH_ROMSWMAP_SW1EN_M 0x0000000C // ROM SW Region 1 Availability +#define FLASH_ROMSWMAP_SW1EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW1EN_CORE \ + 0x00000004 // Region available to core +#define FLASH_ROMSWMAP_SW2EN_M 0x00000030 // ROM SW Region 2 Availability +#define FLASH_ROMSWMAP_SW2EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW2EN_CORE \ + 0x00000010 // Region available to core +#define FLASH_ROMSWMAP_SW3EN_M 0x000000C0 // ROM SW Region 3 Availability +#define FLASH_ROMSWMAP_SW3EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW3EN_CORE \ + 0x00000040 // Region available to core +#define FLASH_ROMSWMAP_SW4EN_M 0x00000300 // ROM SW Region 4 Availability +#define FLASH_ROMSWMAP_SW4EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW4EN_CORE \ + 0x00000100 // Region available to core +#define FLASH_ROMSWMAP_SW5EN_M 0x00000C00 // ROM SW Region 5 Availability +#define FLASH_ROMSWMAP_SW5EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW5EN_CORE \ + 0x00000400 // Region available to core +#define FLASH_ROMSWMAP_SW6EN_M 0x00003000 // ROM SW Region 6 Availability +#define FLASH_ROMSWMAP_SW6EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW6EN_CORE \ + 0x00001000 // Region available to core +#define FLASH_ROMSWMAP_SW7EN_M 0x0000C000 // ROM SW Region 7 Availability +#define FLASH_ROMSWMAP_SW7EN_NOTVIS \ + 0x00000000 // Software region not available to + // the core +#define FLASH_ROMSWMAP_SW7EN_CORE \ + 0x00004000 // Region available to core + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_DMASZ register. +// +//***************************************************************************** +#define FLASH_DMASZ_SIZE_M 0x0003FFFF // uDMA-accessible Memory Size +#define FLASH_DMASZ_SIZE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_DMAST register. +// +//***************************************************************************** +#define FLASH_DMAST_ADDR_M 0x1FFFF800 // Contains the starting address of + // the flash region accessible by + // uDMA if the FLASHPP register DFA + // bit is set +#define FLASH_DMAST_ADDR_S 11 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RVP register. +// +//***************************************************************************** +#define FLASH_RVP_RV_M 0xFFFFFFFF // Reset Vector Pointer Address +#define FLASH_RVP_RV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RMCTL register. +// +//***************************************************************************** +#define FLASH_RMCTL_BA 0x00000001 // Boot Alias + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_BOOTCFG register. +// +//***************************************************************************** +#define FLASH_BOOTCFG_NW 0x80000000 // Not Written +#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port +#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A +#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B +#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C +#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D +#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E +#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F +#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G +#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H +#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin +#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0 +#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1 +#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2 +#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3 +#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4 +#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5 +#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6 +#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7 +#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity +#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable +#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select +#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1 +#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG0 register. +// +//***************************************************************************** +#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG1 register. +// +//***************************************************************************** +#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG2 register. +// +//***************************************************************************** +#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG3 register. +// +//***************************************************************************** +#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE8 register. +// +//***************************************************************************** +#define FLASH_FMPRE8_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE8_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE9 register. +// +//***************************************************************************** +#define FLASH_FMPRE9_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE9_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE10 register. +// +//***************************************************************************** +#define FLASH_FMPRE10_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE10_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE11 register. +// +//***************************************************************************** +#define FLASH_FMPRE11_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE11_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE12 register. +// +//***************************************************************************** +#define FLASH_FMPRE12_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE12_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE13 register. +// +//***************************************************************************** +#define FLASH_FMPRE13_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE13_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE14 register. +// +//***************************************************************************** +#define FLASH_FMPRE14_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE14_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPRE15 register. +// +//***************************************************************************** +#define FLASH_FMPRE15_READ_ENABLE_M \ + 0xFFFFFFFF // Flash Read Enable +#define FLASH_FMPRE15_READ_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE8 register. +// +//***************************************************************************** +#define FLASH_FMPPE8_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE8_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE9 register. +// +//***************************************************************************** +#define FLASH_FMPPE9_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE9_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE10 register. +// +//***************************************************************************** +#define FLASH_FMPPE10_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE10_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE11 register. +// +//***************************************************************************** +#define FLASH_FMPPE11_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE11_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE12 register. +// +//***************************************************************************** +#define FLASH_FMPPE12_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE12_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE13 register. +// +//***************************************************************************** +#define FLASH_FMPPE13_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE13_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE14 register. +// +//***************************************************************************** +#define FLASH_FMPPE14_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE14_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMPPE15 register. +// +//***************************************************************************** +#define FLASH_FMPPE15_PROG_ENABLE_M \ + 0xFFFFFFFF // Flash Programming Enable +#define FLASH_FMPPE15_PROG_ENABLE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the erase size of the FLASH block that is +// erased by an erase operation, and the protect size is the size of the FLASH +// block that is protected by each protection register. +// +//***************************************************************************** +#define FLASH_PROTECT_SIZE 0x00000800 +#define FLASH_ERASE_SIZE 0x00000400 + +#endif // __HW_FLASH_H__ diff --git a/os/common/ext/TivaWare/inc/hw_gpio.h b/os/common/ext/TivaWare/inc/hw_gpio.h new file mode 100644 index 0000000..a2ef2e7 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_gpio.h @@ -0,0 +1,213 @@ +//***************************************************************************** +// +// hw_gpio.h - Defines and Macros for GPIO hardware. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// The following are defines for the GPIO register offsets. +// +//***************************************************************************** +#define GPIO_O_DATA 0x00000000 // GPIO Data +#define GPIO_O_DIR 0x00000400 // GPIO Direction +#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense +#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges +#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event +#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask +#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status +#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status +#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear +#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select +#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select +#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select +#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select +#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select +#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select +#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select +#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select +#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable +#define GPIO_O_LOCK 0x00000520 // GPIO Lock +#define GPIO_O_CR 0x00000524 // GPIO Commit +#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select +#define GPIO_O_PCTL 0x0000052C // GPIO Port Control +#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control +#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control +#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt +#define GPIO_O_DR12R 0x0000053C // GPIO 12-mA Drive Select +#define GPIO_O_WAKEPEN 0x00000540 // GPIO Wake Pin Enable +#define GPIO_O_WAKELVL 0x00000544 // GPIO Wake Level +#define GPIO_O_WAKESTAT 0x00000548 // GPIO Wake Status +#define GPIO_O_PP 0x00000FC0 // GPIO Peripheral Property +#define GPIO_O_PC 0x00000FC4 // GPIO Peripheral Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_IM register. +// +//***************************************************************************** +#define GPIO_IM_DMAIME 0x00000100 // GPIO uDMA Done Interrupt Mask + // Enable +#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable +#define GPIO_IM_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_RIS register. +// +//***************************************************************************** +#define GPIO_RIS_DMARIS 0x00000100 // GPIO uDMA Done Interrupt Raw + // Status +#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status +#define GPIO_RIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_MIS register. +// +//***************************************************************************** +#define GPIO_MIS_DMAMIS 0x00000100 // GPIO uDMA Done Masked Interrupt + // Status +#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status +#define GPIO_MIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_ICR register. +// +//***************************************************************************** +#define GPIO_ICR_DMAIC 0x00000100 // GPIO uDMA Interrupt Clear +#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear +#define GPIO_ICR_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_LOCK register. +// +//***************************************************************************** +#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock +#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked + // and may be modified +#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked + // and may not be modified +#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_SI register. +// +//***************************************************************************** +#define GPIO_SI_SUM 0x00000001 // Summary Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_DR12R register. +// +//***************************************************************************** +#define GPIO_DR12R_DRV12_M 0x000000FF // Output Pad 12-mA Drive Enable +#define GPIO_DR12R_DRV12_12MA 0x00000001 // The corresponding GPIO pin has + // 12-mA drive. This encoding is + // only valid if the GPIOPP EDE bit + // is set and the appropriate + // GPIOPC EDM bit field is + // programmed to 0x3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_WAKEPEN register. +// +//***************************************************************************** +#define GPIO_WAKEPEN_WAKEP4 0x00000010 // P[4] Wake Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_WAKELVL register. +// +//***************************************************************************** +#define GPIO_WAKELVL_WAKELVL4 0x00000010 // P[4] Wake Level + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_WAKESTAT +// register. +// +//***************************************************************************** +#define GPIO_WAKESTAT_STAT4 0x00000010 // P[4] Wake Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_PP register. +// +//***************************************************************************** +#define GPIO_PP_EDE 0x00000001 // Extended Drive Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_PC register. +// +//***************************************************************************** +#define GPIO_PC_EDM7_M 0x0000C000 // Extended Drive Mode Bit 7 +#define GPIO_PC_EDM6_M 0x00003000 // Extended Drive Mode Bit 6 +#define GPIO_PC_EDM5_M 0x00000C00 // Extended Drive Mode Bit 5 +#define GPIO_PC_EDM4_M 0x00000300 // Extended Drive Mode Bit 4 +#define GPIO_PC_EDM3_M 0x000000C0 // Extended Drive Mode Bit 3 +#define GPIO_PC_EDM2_M 0x00000030 // Extended Drive Mode Bit 2 +#define GPIO_PC_EDM1_M 0x0000000C // Extended Drive Mode Bit 1 +#define GPIO_PC_EDM0_M 0x00000003 // Extended Drive Mode Bit 0 +#define GPIO_PC_EDM0_DISABLE 0x00000000 // Drive values of 2, 4 and 8 mA + // are maintained. GPIO n Drive + // Select (GPIODRnR) registers + // function as normal +#define GPIO_PC_EDM0_6MA 0x00000001 // An additional 6 mA option is + // provided +#define GPIO_PC_EDM0_PLUS2MA 0x00000003 // A 2 mA driver is always enabled; + // setting the corresponding + // GPIODR4R register bit adds 2 mA + // and setting the corresponding + // GPIODR8R of GPIODR12R register + // bit adds an additional 4 mA +#define GPIO_PC_EDM7_S 14 +#define GPIO_PC_EDM6_S 12 +#define GPIO_PC_EDM5_S 10 +#define GPIO_PC_EDM4_S 8 +#define GPIO_PC_EDM3_S 6 +#define GPIO_PC_EDM2_S 4 +#define GPIO_PC_EDM1_S 2 + +#endif // __HW_GPIO_H__ diff --git a/os/common/ext/TivaWare/inc/hw_hibernate.h b/os/common/ext/TivaWare/inc/hw_hibernate.h new file mode 100644 index 0000000..6c9b4be --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_hibernate.h @@ -0,0 +1,483 @@ +//***************************************************************************** +// +// hw_hibernate.h - Defines and Macros for the Hibernation module. +// +// Copyright (c) 2007-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_HIBERNATE_H__ +#define __HW_HIBERNATE_H__ + +//***************************************************************************** +// +// The following are defines for the Hibernation module register addresses. +// +//***************************************************************************** +#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter +#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0 +#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load +#define HIB_CTL 0x400FC010 // Hibernation Control +#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask +#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status +#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt + // Status +#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear +#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim +#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds +#define HIB_IO 0x400FC02C // Hibernation IO Configuration +#define HIB_DATA 0x400FC030 // Hibernation Data +#define HIB_CALCTL 0x400FC300 // Hibernation Calendar Control +#define HIB_CAL0 0x400FC310 // Hibernation Calendar 0 +#define HIB_CAL1 0x400FC314 // Hibernation Calendar 1 +#define HIB_CALLD0 0x400FC320 // Hibernation Calendar Load 0 +#define HIB_CALLD1 0x400FC324 // Hibernation Calendar Load +#define HIB_CALM0 0x400FC330 // Hibernation Calendar Match 0 +#define HIB_CALM1 0x400FC334 // Hibernation Calendar Match 1 +#define HIB_LOCK 0x400FC360 // Hibernation Lock +#define HIB_TPCTL 0x400FC400 // HIB Tamper Control +#define HIB_TPSTAT 0x400FC404 // HIB Tamper Status +#define HIB_TPIO 0x400FC410 // HIB Tamper I/O Control +#define HIB_TPLOG0 0x400FC4E0 // HIB Tamper Log 0 +#define HIB_TPLOG1 0x400FC4E4 // HIB Tamper Log 1 +#define HIB_TPLOG2 0x400FC4E8 // HIB Tamper Log 2 +#define HIB_TPLOG3 0x400FC4EC // HIB Tamper Log 3 +#define HIB_TPLOG4 0x400FC4F0 // HIB Tamper Log 4 +#define HIB_TPLOG5 0x400FC4F4 // HIB Tamper Log 5 +#define HIB_TPLOG6 0x400FC4F8 // HIB Tamper Log 6 +#define HIB_TPLOG7 0x400FC4FC // HIB Tamper Log 7 +#define HIB_PP 0x400FCFC0 // Hibernation Peripheral + // Properties +#define HIB_CC 0x400FCFC8 // Hibernation Clock Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCC register. +// +//***************************************************************************** +#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter +#define HIB_RTCC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCM0 register. +// +//***************************************************************************** +#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 +#define HIB_RTCM0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCLD register. +// +//***************************************************************************** +#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load +#define HIB_RTCLD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CTL register. +// +//***************************************************************************** +#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable +#define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear +#define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select +#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability +#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass +#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery + // Comparator +#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts +#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) +#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts +#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts +#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status +#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery +#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered +#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable +#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable +#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable +#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable +#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request +#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IM register. +// +//***************************************************************************** +#define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask +#define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt + // Mask +#define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask +#define HIB_IM_WC 0x00000010 // External Write Complete/Capable + // Interrupt Mask +#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask +#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Mask +#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RIS register. +// +//***************************************************************************** +#define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status +#define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw + // Interrupt Status +#define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt + // Status +#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw + // Interrupt Status +#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt + // Status +#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw + // Interrupt Status +#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_MIS register. +// +//***************************************************************************** +#define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask +#define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt + // Mask +#define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask +#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked + // Interrupt Status +#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked + // Interrupt Status +#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked + // Interrupt Status +#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IC register. +// +//***************************************************************************** +#define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear +#define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt + // Clear +#define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear +#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt + // Clear +#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear +#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Clear +#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCT register. +// +//***************************************************************************** +#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value +#define HIB_RTCT_TRIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCSS register. +// +//***************************************************************************** +#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match +#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count +#define HIB_RTCSS_RTCSSM_S 16 +#define HIB_RTCSS_RTCSSC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IO register. +// +//***************************************************************************** +#define HIB_IO_IOWRC 0x80000000 // I/O Write Complete +#define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable +#define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_DATA register. +// +//***************************************************************************** +#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data +#define HIB_DATA_RTD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CALCTL register. +// +//***************************************************************************** +#define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode +#define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CAL0 register. +// +//***************************************************************************** +#define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load +#define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation +#define HIB_CAL0_HR_M 0x001F0000 // Hours +#define HIB_CAL0_MIN_M 0x00003F00 // Minutes +#define HIB_CAL0_SEC_M 0x0000003F // Seconds +#define HIB_CAL0_HR_S 16 +#define HIB_CAL0_MIN_S 8 +#define HIB_CAL0_SEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CAL1 register. +// +//***************************************************************************** +#define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load +#define HIB_CAL1_DOW_M 0x07000000 // Day of Week +#define HIB_CAL1_YEAR_M 0x007F0000 // Year Value +#define HIB_CAL1_MON_M 0x00000F00 // Month +#define HIB_CAL1_DOM_M 0x0000001F // Day of Month +#define HIB_CAL1_DOW_S 24 +#define HIB_CAL1_YEAR_S 16 +#define HIB_CAL1_MON_S 8 +#define HIB_CAL1_DOM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CALLD0 register. +// +//***************************************************************************** +#define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation +#define HIB_CALLD0_HR_M 0x001F0000 // Hours +#define HIB_CALLD0_MIN_M 0x00003F00 // Minutes +#define HIB_CALLD0_SEC_M 0x0000003F // Seconds +#define HIB_CALLD0_HR_S 16 +#define HIB_CALLD0_MIN_S 8 +#define HIB_CALLD0_SEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CALLD1 register. +// +//***************************************************************************** +#define HIB_CALLD1_DOW_M 0x07000000 // Day of Week +#define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value +#define HIB_CALLD1_MON_M 0x00000F00 // Month +#define HIB_CALLD1_DOM_M 0x0000001F // Day of Month +#define HIB_CALLD1_DOW_S 24 +#define HIB_CALLD1_YEAR_S 16 +#define HIB_CALLD1_MON_S 8 +#define HIB_CALLD1_DOM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CALM0 register. +// +//***************************************************************************** +#define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation +#define HIB_CALM0_HR_M 0x001F0000 // Hours +#define HIB_CALM0_MIN_M 0x00003F00 // Minutes +#define HIB_CALM0_SEC_M 0x0000003F // Seconds +#define HIB_CALM0_HR_S 16 +#define HIB_CALM0_MIN_S 8 +#define HIB_CALM0_SEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CALM1 register. +// +//***************************************************************************** +#define HIB_CALM1_DOM_M 0x0000001F // Day of Month +#define HIB_CALM1_DOM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_LOCK register. +// +//***************************************************************************** +#define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock +#define HIB_LOCK_HIBLOCK_KEY 0xA3359554 // Hibernate Lock Key +#define HIB_LOCK_HIBLOCK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPCTL register. +// +//***************************************************************************** +#define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper + // Event +#define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event +#define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on + // tamper event +#define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB + // memory on tamper event +#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB + // memory on tamper event +#define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper + // event +#define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear +#define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPSTAT register. +// +//***************************************************************************** +#define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status +#define HIB_TPSTAT_STATE_DISABLED \ + 0x00000000 // Tamper disabled +#define HIB_TPSTAT_STATE_CONFIGED \ + 0x00000004 // Tamper configured +#define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred +#define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status +#define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPIO register. +// +//***************************************************************************** +#define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering +#define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up + // Enable +#define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level +#define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable +#define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering +#define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up + // Enable +#define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level +#define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable +#define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering +#define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up + // Enable +#define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level +#define HIB_TPIO_EN1 0x00000100 // TMPR1Enable +#define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering +#define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up + // Enable +#define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level +#define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG0 register. +// +//***************************************************************************** +#define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information +#define HIB_TPLOG0_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG1 register. +// +//***************************************************************************** +#define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32 +#define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger +#define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger +#define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger +#define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG2 register. +// +//***************************************************************************** +#define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information +#define HIB_TPLOG2_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG3 register. +// +//***************************************************************************** +#define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32 +#define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger +#define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger +#define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger +#define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG4 register. +// +//***************************************************************************** +#define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information +#define HIB_TPLOG4_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG5 register. +// +//***************************************************************************** +#define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32 +#define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger +#define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger +#define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger +#define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG6 register. +// +//***************************************************************************** +#define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information +#define HIB_TPLOG6_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_TPLOG7 register. +// +//***************************************************************************** +#define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32 +#define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger +#define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger +#define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger +#define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_PP register. +// +//***************************************************************************** +#define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence +#define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CC register. +// +//***************************************************************************** +#define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable + +#endif // __HW_HIBERNATE_H__ diff --git a/os/common/ext/TivaWare/inc/hw_i2c.h b/os/common/ext/TivaWare/inc/hw_i2c.h new file mode 100644 index 0000000..2cc2032 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_i2c.h @@ -0,0 +1,470 @@ +//***************************************************************************** +// +// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following are defines for the I2C register offsets. +// +//***************************************************************************** +#define I2C_O_MSA 0x00000000 // I2C Master Slave Address +#define I2C_O_MCS 0x00000004 // I2C Master Control/Status +#define I2C_O_MDR 0x00000008 // I2C Master Data +#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period +#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask +#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status +#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt + // Status +#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear +#define I2C_O_MCR 0x00000020 // I2C Master Configuration +#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout + // Count +#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor +#define I2C_O_MBLEN 0x00000030 // I2C Master Burst Length +#define I2C_O_MBCNT 0x00000034 // I2C Master Burst Count +#define I2C_O_MCR2 0x00000038 // I2C Master Configuration 2 +#define I2C_O_SOAR 0x00000800 // I2C Slave Own Address +#define I2C_O_SCSR 0x00000804 // I2C Slave Control/Status +#define I2C_O_SDR 0x00000808 // I2C Slave Data +#define I2C_O_SIMR 0x0000080C // I2C Slave Interrupt Mask +#define I2C_O_SRIS 0x00000810 // I2C Slave Raw Interrupt Status +#define I2C_O_SMIS 0x00000814 // I2C Slave Masked Interrupt + // Status +#define I2C_O_SICR 0x00000818 // I2C Slave Interrupt Clear +#define I2C_O_SOAR2 0x0000081C // I2C Slave Own Address 2 +#define I2C_O_SACKCTL 0x00000820 // I2C Slave ACK Control +#define I2C_O_FIFODATA 0x00000F00 // I2C FIFO Data +#define I2C_O_FIFOCTL 0x00000F04 // I2C FIFO Control +#define I2C_O_FIFOSTATUS 0x00000F08 // I2C FIFO Status +#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties +#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//***************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address +#define I2C_MSA_RS 0x00000001 // Receive not send +#define I2C_MSA_SA_S 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//***************************************************************************** +#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error +#define I2C_MCS_BURST 0x00000040 // Burst Enable +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy +#define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_QCMD 0x00000020 // Quick Command +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_HS 0x00000010 // High-Speed Enable +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable +#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address +#define I2C_MCS_STOP 0x00000004 // Generate STOP +#define I2C_MCS_ERROR 0x00000002 // Error +#define I2C_MCS_START 0x00000002 // Generate START +#define I2C_MCS_RUN 0x00000001 // I2C Master Enable +#define I2C_MCS_BUSY 0x00000001 // I2C Busy + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//***************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data + // transferred during a transaction +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//***************************************************************************** +#define I2C_MTPR_PULSEL_M 0x00070000 // Glitch Suppression Pulse Width +#define I2C_MTPR_PULSEL_BYPASS 0x00000000 // Bypass +#define I2C_MTPR_PULSEL_1 0x00010000 // 1 clock +#define I2C_MTPR_PULSEL_2 0x00020000 // 2 clocks +#define I2C_MTPR_PULSEL_3 0x00030000 // 3 clocks +#define I2C_MTPR_PULSEL_4 0x00040000 // 4 clocks +#define I2C_MTPR_PULSEL_8 0x00050000 // 8 clocks +#define I2C_MTPR_PULSEL_16 0x00060000 // 16 clocks +#define I2C_MTPR_PULSEL_31 0x00070000 // 31 clocks +#define I2C_MTPR_HS 0x00000080 // High-Speed Enable +#define I2C_MTPR_TPR_M 0x0000007F // Timer Period +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//***************************************************************************** +#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt + // Mask +#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask +#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask +#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask +#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//***************************************************************************** +#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt + // Status +#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt + // Status +#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt + // Status +#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt + // Status +#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt + // Status +#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt + // Status +#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt + // Status +#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status +#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//***************************************************************************** +#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask +#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask +#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status +#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//***************************************************************************** +#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt + // Clear +#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt + // Clear +#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt + // Clear +#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt + // Clear +#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear +#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear +#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear +#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt + // Clear +#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear +#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear +#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//***************************************************************************** +#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//***************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//***************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBLEN register. +// +//***************************************************************************** +#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length +#define I2C_MBLEN_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBCNT register. +// +//***************************************************************************** +#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count +#define I2C_MBCNT_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR2 register. +// +//***************************************************************************** +#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width +#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass +#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock +#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks +#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks +#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks +#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks +#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks +#define I2C_MCR2_GFPW_31 0x00000070 // 31 clocks + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//***************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//***************************************************************************** +#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write +#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched +#define I2C_SCSR_FBR 0x00000004 // First Byte Received +#define I2C_SCSR_RXFIFO 0x00000004 // RX FIFO Enable +#define I2C_SCSR_TXFIFO 0x00000002 // TX FIFO Enable +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request +#define I2C_SCSR_DA 0x00000001 // Device Active +#define I2C_SCSR_RREQ 0x00000001 // Receive Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//***************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//***************************************************************************** +#define I2C_SIMR_RXFFIM 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask +#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//***************************************************************************** +#define I2C_SRIS_RXFFRIS 0x00000100 // Receive FIFO Full Raw Interrupt + // Status +#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt + // Status +#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt + // Status +#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//***************************************************************************** +#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt + // Status +#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt + // Status +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//***************************************************************************** +#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask +#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask +#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear +#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear +#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//***************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//***************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFODATA register. +// +//***************************************************************************** +#define I2C_FIFODATA_DATA_M 0x000000FF // I2C TX FIFO Write Data Byte +#define I2C_FIFODATA_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOCTL register. +// +//***************************************************************************** +#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment +#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush +#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable +#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger +#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment +#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush +#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable +#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger +#define I2C_FIFOCTL_RXTRIG_S 16 +#define I2C_FIFOCTL_TXTRIG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOSTATUS +// register. +// +//***************************************************************************** +#define I2C_FIFOSTATUS_RXABVTRIG \ + 0x00040000 // RX FIFO Above Trigger Level +#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full +#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty +#define I2C_FIFOSTATUS_TXBLWTRIG \ + 0x00000004 // TX FIFO Below Trigger Level +#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full +#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//***************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//***************************************************************************** +#define I2C_PC_HS 0x00000001 // High-Speed Capable + +#endif // __HW_I2C_H__ diff --git a/os/common/ext/TivaWare/inc/hw_ints.h b/os/common/ext/TivaWare/inc/hw_ints.h new file mode 100644 index 0000000..d8efb43 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_ints.h @@ -0,0 +1,491 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series +// MCUs. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// TM4C123 Class Interrupts +// +//***************************************************************************** +#define INT_GPIOA_TM4C123 16 // GPIO Port A +#define INT_GPIOB_TM4C123 17 // GPIO Port B +#define INT_GPIOC_TM4C123 18 // GPIO Port C +#define INT_GPIOD_TM4C123 19 // GPIO Port D +#define INT_GPIOE_TM4C123 20 // GPIO Port E +#define INT_UART0_TM4C123 21 // UART0 +#define INT_UART1_TM4C123 22 // UART1 +#define INT_SSI0_TM4C123 23 // SSI0 +#define INT_I2C0_TM4C123 24 // I2C0 +#define INT_PWM0_FAULT_TM4C123 25 // PWM0 Fault +#define INT_PWM0_0_TM4C123 26 // PWM0 Generator 0 +#define INT_PWM0_1_TM4C123 27 // PWM0 Generator 1 +#define INT_PWM0_2_TM4C123 28 // PWM0 Generator 2 +#define INT_QEI0_TM4C123 29 // QEI0 +#define INT_ADC0SS0_TM4C123 30 // ADC0 Sequence 0 +#define INT_ADC0SS1_TM4C123 31 // ADC0 Sequence 1 +#define INT_ADC0SS2_TM4C123 32 // ADC0 Sequence 2 +#define INT_ADC0SS3_TM4C123 33 // ADC0 Sequence 3 +#define INT_WATCHDOG_TM4C123 34 // Watchdog Timers 0 and 1 +#define INT_TIMER0A_TM4C123 35 // 16/32-Bit Timer 0A +#define INT_TIMER0B_TM4C123 36 // 16/32-Bit Timer 0B +#define INT_TIMER1A_TM4C123 37 // 16/32-Bit Timer 1A +#define INT_TIMER1B_TM4C123 38 // 16/32-Bit Timer 1B +#define INT_TIMER2A_TM4C123 39 // 16/32-Bit Timer 2A +#define INT_TIMER2B_TM4C123 40 // 16/32-Bit Timer 2B +#define INT_COMP0_TM4C123 41 // Analog Comparator 0 +#define INT_COMP1_TM4C123 42 // Analog Comparator 1 +#define INT_COMP2_TM4C123 43 // Analog Comparator 2 +#define INT_SYSCTL_TM4C123 44 // System Control +#define INT_FLASH_TM4C123 45 // Flash Memory Control and EEPROM + // Control +#define INT_GPIOF_TM4C123 46 // GPIO Port F +#define INT_GPIOG_TM4C123 47 // GPIO Port G +#define INT_GPIOH_TM4C123 48 // GPIO Port H +#define INT_UART2_TM4C123 49 // UART2 +#define INT_SSI1_TM4C123 50 // SSI1 +#define INT_TIMER3A_TM4C123 51 // 16/32-Bit Timer 3A +#define INT_TIMER3B_TM4C123 52 // Timer 3B +#define INT_I2C1_TM4C123 53 // I2C1 +#define INT_QEI1_TM4C123 54 // QEI1 +#define INT_CAN0_TM4C123 55 // CAN0 +#define INT_CAN1_TM4C123 56 // CAN1 +#define INT_HIBERNATE_TM4C123 59 // Hibernation Module +#define INT_USB0_TM4C123 60 // USB +#define INT_PWM0_3_TM4C123 61 // PWM Generator 3 +#define INT_UDMA_TM4C123 62 // uDMA Software +#define INT_UDMAERR_TM4C123 63 // uDMA Error +#define INT_ADC1SS0_TM4C123 64 // ADC1 Sequence 0 +#define INT_ADC1SS1_TM4C123 65 // ADC1 Sequence 1 +#define INT_ADC1SS2_TM4C123 66 // ADC1 Sequence 2 +#define INT_ADC1SS3_TM4C123 67 // ADC1 Sequence 3 +#define INT_GPIOJ_TM4C123 70 // GPIO Port J +#define INT_GPIOK_TM4C123 71 // GPIO Port K +#define INT_GPIOL_TM4C123 72 // GPIO Port L +#define INT_SSI2_TM4C123 73 // SSI2 +#define INT_SSI3_TM4C123 74 // SSI3 +#define INT_UART3_TM4C123 75 // UART3 +#define INT_UART4_TM4C123 76 // UART4 +#define INT_UART5_TM4C123 77 // UART5 +#define INT_UART6_TM4C123 78 // UART6 +#define INT_UART7_TM4C123 79 // UART7 +#define INT_I2C2_TM4C123 84 // I2C2 +#define INT_I2C3_TM4C123 85 // I2C3 +#define INT_TIMER4A_TM4C123 86 // 16/32-Bit Timer 4A +#define INT_TIMER4B_TM4C123 87 // 16/32-Bit Timer 4B +#define INT_TIMER5A_TM4C123 108 // 16/32-Bit Timer 5A +#define INT_TIMER5B_TM4C123 109 // 16/32-Bit Timer 5B +#define INT_WTIMER0A_TM4C123 110 // 32/64-Bit Timer 0A +#define INT_WTIMER0B_TM4C123 111 // 32/64-Bit Timer 0B +#define INT_WTIMER1A_TM4C123 112 // 32/64-Bit Timer 1A +#define INT_WTIMER1B_TM4C123 113 // 32/64-Bit Timer 1B +#define INT_WTIMER2A_TM4C123 114 // 32/64-Bit Timer 2A +#define INT_WTIMER2B_TM4C123 115 // 32/64-Bit Timer 2B +#define INT_WTIMER3A_TM4C123 116 // 32/64-Bit Timer 3A +#define INT_WTIMER3B_TM4C123 117 // 32/64-Bit Timer 3B +#define INT_WTIMER4A_TM4C123 118 // 32/64-Bit Timer 4A +#define INT_WTIMER4B_TM4C123 119 // 32/64-Bit Timer 4B +#define INT_WTIMER5A_TM4C123 120 // 32/64-Bit Timer 5A +#define INT_WTIMER5B_TM4C123 121 // 32/64-Bit Timer 5B +#define INT_SYSEXC_TM4C123 122 // System Exception (imprecise) +#define INT_I2C4_TM4C123 125 // I2C4 +#define INT_I2C5_TM4C123 126 // I2C5 +#define INT_GPIOM_TM4C123 127 // GPIO Port M +#define INT_GPION_TM4C123 128 // GPIO Port N +#define INT_GPIOP0_TM4C123 132 // GPIO Port P (Summary or P0) +#define INT_GPIOP1_TM4C123 133 // GPIO Port P1 +#define INT_GPIOP2_TM4C123 134 // GPIO Port P2 +#define INT_GPIOP3_TM4C123 135 // GPIO Port P3 +#define INT_GPIOP4_TM4C123 136 // GPIO Port P4 +#define INT_GPIOP5_TM4C123 137 // GPIO Port P5 +#define INT_GPIOP6_TM4C123 138 // GPIO Port P6 +#define INT_GPIOP7_TM4C123 139 // GPIO Port P7 +#define INT_GPIOQ0_TM4C123 140 // GPIO Port Q (Summary or Q0) +#define INT_GPIOQ1_TM4C123 141 // GPIO Port Q1 +#define INT_GPIOQ2_TM4C123 142 // GPIO Port Q2 +#define INT_GPIOQ3_TM4C123 143 // GPIO Port Q3 +#define INT_GPIOQ4_TM4C123 144 // GPIO Port Q4 +#define INT_GPIOQ5_TM4C123 145 // GPIO Port Q5 +#define INT_GPIOQ6_TM4C123 146 // GPIO Port Q6 +#define INT_GPIOQ7_TM4C123 147 // GPIO Port Q7 +#define INT_PWM1_0_TM4C123 150 // PWM1 Generator 0 +#define INT_PWM1_1_TM4C123 151 // PWM1 Generator 1 +#define INT_PWM1_2_TM4C123 152 // PWM1 Generator 2 +#define INT_PWM1_3_TM4C123 153 // PWM1 Generator 3 +#define INT_PWM1_FAULT_TM4C123 154 // PWM1 Fault +#define NUM_INTERRUPTS_TM4C123 155 + +//***************************************************************************** +// +// TM4C129 Class Interrupts +// +//***************************************************************************** +#define INT_GPIOA_TM4C129 16 // GPIO Port A +#define INT_GPIOB_TM4C129 17 // GPIO Port B +#define INT_GPIOC_TM4C129 18 // GPIO Port C +#define INT_GPIOD_TM4C129 19 // GPIO Port D +#define INT_GPIOE_TM4C129 20 // GPIO Port E +#define INT_UART0_TM4C129 21 // UART0 +#define INT_UART1_TM4C129 22 // UART1 +#define INT_SSI0_TM4C129 23 // SSI0 +#define INT_I2C0_TM4C129 24 // I2C0 +#define INT_PWM0_FAULT_TM4C129 25 // PWM Fault +#define INT_PWM0_0_TM4C129 26 // PWM Generator 0 +#define INT_PWM0_1_TM4C129 27 // PWM Generator 1 +#define INT_PWM0_2_TM4C129 28 // PWM Generator 2 +#define INT_QEI0_TM4C129 29 // QEI0 +#define INT_ADC0SS0_TM4C129 30 // ADC0 Sequence 0 +#define INT_ADC0SS1_TM4C129 31 // ADC0 Sequence 1 +#define INT_ADC0SS2_TM4C129 32 // ADC0 Sequence 2 +#define INT_ADC0SS3_TM4C129 33 // ADC0 Sequence 3 +#define INT_WATCHDOG_TM4C129 34 // Watchdog Timers 0 and 1 +#define INT_TIMER0A_TM4C129 35 // 16/32-Bit Timer 0A +#define INT_TIMER0B_TM4C129 36 // 16/32-Bit Timer 0B +#define INT_TIMER1A_TM4C129 37 // 16/32-Bit Timer 1A +#define INT_TIMER1B_TM4C129 38 // 16/32-Bit Timer 1B +#define INT_TIMER2A_TM4C129 39 // 16/32-Bit Timer 2A +#define INT_TIMER2B_TM4C129 40 // 16/32-Bit Timer 2B +#define INT_COMP0_TM4C129 41 // Analog Comparator 0 +#define INT_COMP1_TM4C129 42 // Analog Comparator 1 +#define INT_COMP2_TM4C129 43 // Analog Comparator 2 +#define INT_SYSCTL_TM4C129 44 // System Control +#define INT_FLASH_TM4C129 45 // Flash Memory Control +#define INT_GPIOF_TM4C129 46 // GPIO Port F +#define INT_GPIOG_TM4C129 47 // GPIO Port G +#define INT_GPIOH_TM4C129 48 // GPIO Port H +#define INT_UART2_TM4C129 49 // UART2 +#define INT_SSI1_TM4C129 50 // SSI1 +#define INT_TIMER3A_TM4C129 51 // 16/32-Bit Timer 3A +#define INT_TIMER3B_TM4C129 52 // 16/32-Bit Timer 3B +#define INT_I2C1_TM4C129 53 // I2C1 +#define INT_CAN0_TM4C129 54 // CAN 0 +#define INT_CAN1_TM4C129 55 // CAN1 +#define INT_EMAC0_TM4C129 56 // Ethernet MAC +#define INT_HIBERNATE_TM4C129 57 // HIB +#define INT_USB0_TM4C129 58 // USB MAC +#define INT_PWM0_3_TM4C129 59 // PWM Generator 3 +#define INT_UDMA_TM4C129 60 // uDMA 0 Software +#define INT_UDMAERR_TM4C129 61 // uDMA 0 Error +#define INT_ADC1SS0_TM4C129 62 // ADC1 Sequence 0 +#define INT_ADC1SS1_TM4C129 63 // ADC1 Sequence 1 +#define INT_ADC1SS2_TM4C129 64 // ADC1 Sequence 2 +#define INT_ADC1SS3_TM4C129 65 // ADC1 Sequence 3 +#define INT_EPI0_TM4C129 66 // EPI 0 +#define INT_GPIOJ_TM4C129 67 // GPIO Port J +#define INT_GPIOK_TM4C129 68 // GPIO Port K +#define INT_GPIOL_TM4C129 69 // GPIO Port L +#define INT_SSI2_TM4C129 70 // SSI 2 +#define INT_SSI3_TM4C129 71 // SSI 3 +#define INT_UART3_TM4C129 72 // UART 3 +#define INT_UART4_TM4C129 73 // UART 4 +#define INT_UART5_TM4C129 74 // UART 5 +#define INT_UART6_TM4C129 75 // UART 6 +#define INT_UART7_TM4C129 76 // UART 7 +#define INT_I2C2_TM4C129 77 // I2C 2 +#define INT_I2C3_TM4C129 78 // I2C 3 +#define INT_TIMER4A_TM4C129 79 // Timer 4A +#define INT_TIMER4B_TM4C129 80 // Timer 4B +#define INT_TIMER5A_TM4C129 81 // Timer 5A +#define INT_TIMER5B_TM4C129 82 // Timer 5B +#define INT_SYSEXC_TM4C129 83 // Floating-Point Exception + // (imprecise) +#define INT_I2C4_TM4C129 86 // I2C 4 +#define INT_I2C5_TM4C129 87 // I2C 5 +#define INT_GPIOM_TM4C129 88 // GPIO Port M +#define INT_GPION_TM4C129 89 // GPIO Port N +#define INT_TAMPER0_TM4C129 91 // Tamper +#define INT_GPIOP0_TM4C129 92 // GPIO Port P (Summary or P0) +#define INT_GPIOP1_TM4C129 93 // GPIO Port P1 +#define INT_GPIOP2_TM4C129 94 // GPIO Port P2 +#define INT_GPIOP3_TM4C129 95 // GPIO Port P3 +#define INT_GPIOP4_TM4C129 96 // GPIO Port P4 +#define INT_GPIOP5_TM4C129 97 // GPIO Port P5 +#define INT_GPIOP6_TM4C129 98 // GPIO Port P6 +#define INT_GPIOP7_TM4C129 99 // GPIO Port P7 +#define INT_GPIOQ0_TM4C129 100 // GPIO Port Q (Summary or Q0) +#define INT_GPIOQ1_TM4C129 101 // GPIO Port Q1 +#define INT_GPIOQ2_TM4C129 102 // GPIO Port Q2 +#define INT_GPIOQ3_TM4C129 103 // GPIO Port Q3 +#define INT_GPIOQ4_TM4C129 104 // GPIO Port Q4 +#define INT_GPIOQ5_TM4C129 105 // GPIO Port Q5 +#define INT_GPIOQ6_TM4C129 106 // GPIO Port Q6 +#define INT_GPIOQ7_TM4C129 107 // GPIO Port Q7 +#define INT_GPIOR_TM4C129 108 // GPIO Port R +#define INT_GPIOS_TM4C129 109 // GPIO Port S +#define INT_SHA0_TM4C129 110 // SHA/MD5 +#define INT_AES0_TM4C129 111 // AES +#define INT_DES0_TM4C129 112 // DES +#define INT_LCD0_TM4C129 113 // LCD +#define INT_TIMER6A_TM4C129 114 // 16/32-Bit Timer 6A +#define INT_TIMER6B_TM4C129 115 // 16/32-Bit Timer 6B +#define INT_TIMER7A_TM4C129 116 // 16/32-Bit Timer 7A +#define INT_TIMER7B_TM4C129 117 // 16/32-Bit Timer 7B +#define INT_I2C6_TM4C129 118 // I2C 6 +#define INT_I2C7_TM4C129 119 // I2C 7 +#define INT_ONEWIRE0_TM4C129 121 // 1-Wire +#define INT_I2C8_TM4C129 125 // I2C 8 +#define INT_I2C9_TM4C129 126 // I2C 9 +#define INT_GPIOT_TM4C129 127 // GPIO T +#define NUM_INTERRUPTS_TM4C129 129 + +//***************************************************************************** +// +// TM4C123 Interrupt Class Definition +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \ + defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \ + defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \ + defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \ + defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \ + defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \ + defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \ + defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \ + defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \ + defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \ + defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \ + defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \ + defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \ + defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \ + defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \ + defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \ + defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \ + defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \ + defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \ + defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \ + defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \ + defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \ + defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \ + defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \ + defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \ + defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \ + defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \ + defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR) +#define INT_RESOLVE(intname, class) intname##TM4C123 + +//***************************************************************************** +// +// TM4C129 Interrupt Class Definition +// +//***************************************************************************** +#elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \ + defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \ + defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \ + defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \ + defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \ + defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \ + defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \ + defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \ + defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \ + defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \ + defined(PART_TM4C129XNCZAD) +#define INT_RESOLVE(intname, class) intname##TM4C129 +#else +#define INT_DEVICE_CLASS "UNKNOWN" +#endif + +//***************************************************************************** +// +// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name. +// +//***************************************************************************** +#define INT_CONCAT(intname, class) INT_RESOLVE(intname, class) + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS) +#define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS) +#define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS) +#define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS) +#define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS) +#define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS) +#define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS) +#define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS) +#define INT_AES0 INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS) +#define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS) +#define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS) +#define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS) +#define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS) +#define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS) +#define INT_DES0 INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS) +#define INT_EMAC0 INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS) +#define INT_EPI0 INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS) +#define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS) +#define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS) +#define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS) +#define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS) +#define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS) +#define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS) +#define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS) +#define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS) +#define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS) +#define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS) +#define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS) +#define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS) +#define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS) +#define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS) +#define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS) +#define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS) +#define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS) +#define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS) +#define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS) +#define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS) +#define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS) +#define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS) +#define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS) +#define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS) +#define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS) +#define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS) +#define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS) +#define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS) +#define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS) +#define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS) +#define INT_GPIOR INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS) +#define INT_GPIOS INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS) +#define INT_GPIOT INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS) +#define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS) +#define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS) +#define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS) +#define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS) +#define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS) +#define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS) +#define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS) +#define INT_I2C6 INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS) +#define INT_I2C7 INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS) +#define INT_I2C8 INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS) +#define INT_I2C9 INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS) +#define INT_LCD0 INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS) +#define INT_ONEWIRE0 INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS) +#define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS) +#define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS) +#define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS) +#define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS) +#define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS) +#define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS) +#define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS) +#define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS) +#define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS) +#define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS) +#define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS) +#define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS) +#define INT_SHA0 INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS) +#define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS) +#define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS) +#define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS) +#define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS) +#define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS) +#define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS) +#define INT_TAMPER0 INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS) +#define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS) +#define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS) +#define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS) +#define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS) +#define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS) +#define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS) +#define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS) +#define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS) +#define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS) +#define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS) +#define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS) +#define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS) +#define INT_TIMER6A INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS) +#define INT_TIMER6B INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS) +#define INT_TIMER7A INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS) +#define INT_TIMER7B INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS) +#define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS) +#define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS) +#define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS) +#define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS) +#define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS) +#define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS) +#define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS) +#define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS) +#define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS) +#define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS) +#define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS) +#define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS) +#define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS) +#define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS) +#define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS) +#define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS) +#define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS) +#define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS) +#define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS) +#define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS) +#define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS) +#define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS) +#define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS) +#define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS) + +//***************************************************************************** +// +// The following are defines for the total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS) + +//***************************************************************************** +// +// The following are defines for the total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/os/common/ext/TivaWare/inc/hw_lcd.h b/os/common/ext/TivaWare/inc/hw_lcd.h new file mode 100644 index 0000000..f8711be --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_lcd.h @@ -0,0 +1,575 @@ +//***************************************************************************** +// +// hw_lcd.h - Defines and macros used when accessing the LCD controller. +// +// Copyright (c) 2011-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_LCD_H__ +#define __HW_LCD_H__ + +//***************************************************************************** +// +// The following are defines for the LCD register offsets. +// +//***************************************************************************** +#define LCD_O_PID 0x00000000 // LCD PID Register Format +#define LCD_O_CTL 0x00000004 // LCD Control +#define LCD_O_LIDDCTL 0x0000000C // LCD LIDD Control +#define LCD_O_LIDDCS0CFG 0x00000010 // LCD LIDD CS0 Configuration +#define LCD_O_LIDDCS0ADDR 0x00000014 // LIDD CS0 Read/Write Address +#define LCD_O_LIDDCS0DATA 0x00000018 // LIDD CS0 Data Read/Write + // Initiation +#define LCD_O_LIDDCS1CFG 0x0000001C // LIDD CS1 Configuration +#define LCD_O_LIDDCS1ADDR 0x00000020 // LIDD CS1 Address Read/Write + // Initiation +#define LCD_O_LIDDCS1DATA 0x00000024 // LIDD CS1 Data Read/Write + // Initiation +#define LCD_O_RASTRCTL 0x00000028 // LCD Raster Control +#define LCD_O_RASTRTIM0 0x0000002C // LCD Raster Timing 0 +#define LCD_O_RASTRTIM1 0x00000030 // LCD Raster Timing 1 +#define LCD_O_RASTRTIM2 0x00000034 // LCD Raster Timing 2 +#define LCD_O_RASTRSUBP1 0x00000038 // LCD Raster Subpanel Display 1 +#define LCD_O_RASTRSUBP2 0x0000003C // LCD Raster Subpanel Display 2 +#define LCD_O_DMACTL 0x00000040 // LCD DMA Control +#define LCD_O_DMABAFB0 0x00000044 // LCD DMA Frame Buffer 0 Base + // Address +#define LCD_O_DMACAFB0 0x00000048 // LCD DMA Frame Buffer 0 Ceiling + // Address +#define LCD_O_DMABAFB1 0x0000004C // LCD DMA Frame Buffer 1 Base + // Address +#define LCD_O_DMACAFB1 0x00000050 // LCD DMA Frame Buffer 1 Ceiling + // Address +#define LCD_O_SYSCFG 0x00000054 // LCD System Configuration + // Register +#define LCD_O_RISSET 0x00000058 // LCD Interrupt Raw Status and Set + // Register +#define LCD_O_MISCLR 0x0000005C // LCD Interrupt Status and Clear +#define LCD_O_IM 0x00000060 // LCD Interrupt Mask +#define LCD_O_IENC 0x00000064 // LCD Interrupt Enable Clear +#define LCD_O_CLKEN 0x0000006C // LCD Clock Enable +#define LCD_O_CLKRESET 0x00000070 // LCD Clock Resets + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_PID register. +// +//***************************************************************************** +#define LCD_PID_MAJOR_M 0x00000700 // Major Release Number +#define LCD_PID_MINOR_M 0x0000003F // Minor Release Number +#define LCD_PID_MAJOR_S 8 +#define LCD_PID_MINOR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_CTL register. +// +//***************************************************************************** +#define LCD_CTL_CLKDIV_M 0x0000FF00 // Clock Divisor +#define LCD_CTL_UFLOWRST 0x00000002 // Underflow Restart +#define LCD_CTL_LCDMODE 0x00000001 // LCD Mode Select +#define LCD_CTL_CLKDIV_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCTL register. +// +//***************************************************************************** +#define LCD_LIDDCTL_DMACS 0x00000200 // CS0/CS1 Select for LIDD DMA + // Writes +#define LCD_LIDDCTL_DMAEN 0x00000100 // LIDD DMA Enable +#define LCD_LIDDCTL_CS1E1 0x00000080 // Chip Select 1 (CS1)/Enable 1(E1) + // Polarity Control +#define LCD_LIDDCTL_CS0E0 0x00000040 // Chip Select 0 (CS0)/Enable 0 + // (E0) Polarity Control +#define LCD_LIDDCTL_WRDIRINV 0x00000020 // Write Strobe (WR) /Direction + // (DIR) Polarity Control +#define LCD_LIDDCTL_RDEN 0x00000010 // Read Strobe (RD) /Direct Enable + // (EN) Polarity Control +#define LCD_LIDDCTL_ALE 0x00000008 // Address Latch Enable (ALE) + // Polarity Control +#define LCD_LIDDCTL_MODE_M 0x00000007 // LIDD Mode Select +#define LCD_LIDDCTL_MODE_SYNCM68 \ + 0x00000000 // Synchronous Motorola 6800 Mode +#define LCD_LIDDCTL_MODE_ASYNCM68 \ + 0x00000001 // Asynchronous Motorola 6800 Mode +#define LCD_LIDDCTL_MODE_SYNCM80 \ + 0x00000002 // Synchronous Intel 8080 mode +#define LCD_LIDDCTL_MODE_ASYNCM80 \ + 0x00000003 // Asynchronous Intel 8080 mode +#define LCD_LIDDCTL_MODE_ASYNCHIT \ + 0x00000004 // Asynchronous Hitachi mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS0CFG +// register. +// +//***************************************************************************** +#define LCD_LIDDCS0CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles +#define LCD_LIDDCS0CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration + // Cycles +#define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles +#define LCD_LIDDCS0CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles +#define LCD_LIDDCS0CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles +#define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles +#define LCD_LIDDCS0CFG_GAP_M 0x00000003 // Field value defines the number + // of LCDMCLK cycles (GAP +1) + // between the end of one CS0 + // (LCDAC) device access and the + // start of another CS0 (LCDAC) + // device access unless the two + // accesses are both reads +#define LCD_LIDDCS0CFG_WRSU_S 27 +#define LCD_LIDDCS0CFG_WRDUR_S 21 +#define LCD_LIDDCS0CFG_WRHOLD_S 17 +#define LCD_LIDDCS0CFG_RDSU_S 12 +#define LCD_LIDDCS0CFG_RDDUR_S 6 +#define LCD_LIDDCS0CFG_RDHOLD_S 2 +#define LCD_LIDDCS0CFG_GAP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR +// register. +// +//***************************************************************************** +#define LCD_LIDDCS0ADDR_CS0ADDR_M \ + 0x0000FFFF // LCD Address +#define LCD_LIDDCS0ADDR_CS0ADDR_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS0DATA +// register. +// +//***************************************************************************** +#define LCD_LIDDCS0DATA_CS0DATA_M \ + 0x0000FFFF // LCD Data Read/Write +#define LCD_LIDDCS0DATA_CS0DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS1CFG +// register. +// +//***************************************************************************** +#define LCD_LIDDCS1CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles +#define LCD_LIDDCS1CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration + // Cycles +#define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles +#define LCD_LIDDCS1CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles +#define LCD_LIDDCS1CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles +#define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles +#define LCD_LIDDCS1CFG_GAP_M 0x00000003 // Field value defines the number + // of LCDMCLK cycles (GAP + 1) + // between the end of one CS1 + // (LCDAC) device access and the + // start of another CS0 (LCDAC) + // device access unless the two + // accesses are both reads +#define LCD_LIDDCS1CFG_WRSU_S 27 +#define LCD_LIDDCS1CFG_WRDUR_S 21 +#define LCD_LIDDCS1CFG_WRHOLD_S 17 +#define LCD_LIDDCS1CFG_RDSU_S 12 +#define LCD_LIDDCS1CFG_RDDUR_S 6 +#define LCD_LIDDCS1CFG_RDHOLD_S 2 +#define LCD_LIDDCS1CFG_GAP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR +// register. +// +//***************************************************************************** +#define LCD_LIDDCS1ADDR_CS1ADDR_M \ + 0x0000FFFF // LCD Address Bus +#define LCD_LIDDCS1ADDR_CS1ADDR_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_LIDDCS1DATA +// register. +// +//***************************************************************************** +#define LCD_LIDDCS1DATA_CS0DATA_M \ + 0x0000FFFF // LCD Data Read/Write Initiation +#define LCD_LIDDCS1DATA_CS0DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRCTL register. +// +//***************************************************************************** +#define LCD_RASTRCTL_TFT24UPCK 0x04000000 // 24-bit TFT Mode Packing +#define LCD_RASTRCTL_TFT24 0x02000000 // 24-Bit TFT Mode +#define LCD_RASTRCTL_FRMBUFSZ 0x01000000 // Frame Buffer Select +#define LCD_RASTRCTL_TFTMAP 0x00800000 // TFT Mode Alternate Signal + // Mapping for Palettized + // Framebuffer +#define LCD_RASTRCTL_NIBMODE 0x00400000 // Nibble Mode +#define LCD_RASTRCTL_PALMODE_M 0x00300000 // Pallette Loading Mode +#define LCD_RASTRCTL_PALMODE_PALDAT \ + 0x00000000 // Palette and data loading, reset + // value +#define LCD_RASTRCTL_PALMODE_PAL \ + 0x00100000 // Palette loading only +#define LCD_RASTRCTL_PALMODE_DAT \ + 0x00200000 // Data loading only +#define LCD_RASTRCTL_REQDLY_M 0x000FF000 // Palette Loading Delay +#define LCD_RASTRCTL_MONO8B 0x00000200 // Mono 8-Bit +#define LCD_RASTRCTL_RDORDER 0x00000100 // Raster Data Order Select +#define LCD_RASTRCTL_LCDTFT 0x00000080 // LCD TFT +#define LCD_RASTRCTL_LCDBW 0x00000002 // LCD Monochrome +#define LCD_RASTRCTL_LCDEN 0x00000001 // LCD Controller Enable for Raster + // Operations +#define LCD_RASTRCTL_REQDLY_S 12 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRTIM0 +// register. +// +//***************************************************************************** +#define LCD_RASTRTIM0_HBP_M 0xFF000000 // Horizontal Back Porch Lowbits +#define LCD_RASTRTIM0_HFP_M 0x00FF0000 // Horizontal Front Porch Lowbits +#define LCD_RASTRTIM0_HSW_M 0x0000FC00 // Horizontal Sync Pulse Width + // Lowbits +#define LCD_RASTRTIM0_PPL_M 0x000003F0 // Pixels-per-line LSB[9:4] +#define LCD_RASTRTIM0_MSBPPL 0x00000008 // Pixels-per-line MSB[10] +#define LCD_RASTRTIM0_HBP_S 24 +#define LCD_RASTRTIM0_HFP_S 16 +#define LCD_RASTRTIM0_HSW_S 10 +#define LCD_RASTRTIM0_PPL_S 4 +#define LCD_RASTRTIM0_MSBPPL_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRTIM1 +// register. +// +//***************************************************************************** +#define LCD_RASTRTIM1_VBP_M 0xFF000000 // Vertical Back Porch +#define LCD_RASTRTIM1_VFP_M 0x00FF0000 // Vertical Front Porch +#define LCD_RASTRTIM1_VSW_M 0x0000FC00 // Vertical Sync Width Pulse +#define LCD_RASTRTIM1_LPP_M 0x000003FF // Lines Per Panel +#define LCD_RASTRTIM1_VBP_S 24 +#define LCD_RASTRTIM1_VFP_S 16 +#define LCD_RASTRTIM1_VSW_S 10 +#define LCD_RASTRTIM1_LPP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRTIM2 +// register. +// +//***************************************************************************** +#define LCD_RASTRTIM2_HSW_M 0x78000000 // Bits 9:6 of the horizontal sync + // width field +#define LCD_RASTRTIM2_MSBLPP 0x04000000 // MSB of Lines Per Panel +#define LCD_RASTRTIM2_PXLCLKCTL 0x02000000 // Hsync/Vsync Pixel Clock Control + // On/Off +#define LCD_RASTRTIM2_PSYNCRF 0x01000000 // Program HSYNC/VSYNC Rise or Fall +#define LCD_RASTRTIM2_INVOE 0x00800000 // Invert Output Enable +#define LCD_RASTRTIM2_INVPXLCLK 0x00400000 // Invert Pixel Clock +#define LCD_RASTRTIM2_IHS 0x00200000 // Invert Hysync +#define LCD_RASTRTIM2_IVS 0x00100000 // Invert Vsync +#define LCD_RASTRTIM2_ACBI_M 0x000F0000 // AC Bias Pins Transitions per + // Interrupt +#define LCD_RASTRTIM2_ACBF_M 0x0000FF00 // AC Bias Pin Frequency +#define LCD_RASTRTIM2_MSBHBP_M 0x00000030 // Bits 9:8 of the horizontal back + // porch field +#define LCD_RASTRTIM2_MSBHFP_M 0x00000003 // Bits 9:8 of the horizontal front + // porch field +#define LCD_RASTRTIM2_HSW_S 27 +#define LCD_RASTRTIM2_MSBLPP_S 26 +#define LCD_RASTRTIM2_ACBI_S 16 +#define LCD_RASTRTIM2_ACBF_S 8 +#define LCD_RASTRTIM2_MSBHBP_S 4 +#define LCD_RASTRTIM2_MSBHFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRSUBP1 +// register. +// +//***************************************************************************** +#define LCD_RASTRSUBP1_SPEN 0x80000000 // Sub Panel Enable +#define LCD_RASTRSUBP1_HOLS 0x20000000 // High or Low Signal +#define LCD_RASTRSUBP1_LPPT_M 0x03FF0000 // Line Per Panel Threshold +#define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF // Default Pixel Data LSB[15:0] +#define LCD_RASTRSUBP1_LPPT_S 16 +#define LCD_RASTRSUBP1_DPDLSB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RASTRSUBP2 +// register. +// +//***************************************************************************** +#define LCD_RASTRSUBP2_LPPTMSB 0x00000100 // Lines Per Panel Threshold Bit 10 +#define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF // Default Pixel Data MSB [23:16] +#define LCD_RASTRSUBP2_DPDMSB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_DMACTL register. +// +//***************************************************************************** +#define LCD_DMACTL_FIFORDY_M 0x00000700 // DMA FIFO threshold +#define LCD_DMACTL_FIFORDY_8 0x00000000 // 8 words +#define LCD_DMACTL_FIFORDY_16 0x00000100 // 16 words +#define LCD_DMACTL_FIFORDY_32 0x00000200 // 32 words +#define LCD_DMACTL_FIFORDY_64 0x00000300 // 64 words +#define LCD_DMACTL_FIFORDY_128 0x00000400 // 128 words +#define LCD_DMACTL_FIFORDY_256 0x00000500 // 256 words +#define LCD_DMACTL_FIFORDY_512 0x00000600 // 512 words +#define LCD_DMACTL_BURSTSZ_M 0x00000070 // Burst Size setting for DMA + // transfers (all DMA transfers are + // 32 bits wide): +#define LCD_DMACTL_BURSTSZ_4 0x00000020 // burst size of 4 +#define LCD_DMACTL_BURSTSZ_8 0x00000030 // burst size of 8 +#define LCD_DMACTL_BURSTSZ_16 0x00000040 // burst size of 16 +#define LCD_DMACTL_BYTESWAP 0x00000008 // This bit controls the bytelane + // ordering of the data on the + // output of the DMA module +#define LCD_DMACTL_BIGDEND 0x00000002 // Big Endian Enable +#define LCD_DMACTL_FMODE 0x00000001 // Frame Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_DMABAFB0 register. +// +//***************************************************************************** +#define LCD_DMABAFB0_FB0BA_M 0xFFFFFFFC // Frame Buffer 0 Base Address + // pointer +#define LCD_DMABAFB0_FB0BA_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_DMACAFB0 register. +// +//***************************************************************************** +#define LCD_DMACAFB0_FB0CA_M 0xFFFFFFFC // Frame Buffer 0 Ceiling Address + // pointer +#define LCD_DMACAFB0_FB0CA_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_DMABAFB1 register. +// +//***************************************************************************** +#define LCD_DMABAFB1_FB1BA_M 0xFFFFFFFC // Frame Buffer 1 Base Address + // pointer +#define LCD_DMABAFB1_FB1BA_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_DMACAFB1 register. +// +//***************************************************************************** +#define LCD_DMACAFB1_FB1CA_M 0xFFFFFFFC // Frame Buffer 1 Ceiling Address + // pointer +#define LCD_DMACAFB1_FB1CA_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_SYSCFG register. +// +//***************************************************************************** +#define LCD_SYSCFG_STDBY_M 0x00000030 // Standby Mode +#define LCD_SYSCFG_STDBY_FORCE 0x00000000 // Force-standby mode: local + // initiator is unconditionally + // placed in standby state. Backup + // mode, for debug only +#define LCD_SYSCFG_STDBY_NONE 0x00000010 // No-standby mode: local initiator + // is unconditionally placed out of + // standby state. Backup mode, for + // debug only +#define LCD_SYSCFG_STDBY_SMART 0x00000020 // Smart-standby mode: local + // initiator standby status depends + // on local conditions, that is, + // the module's functional + // requirement from the initiator. + // IP module shall not generate + // (initiator-related) wakeup + // events +#define LCD_SYSCFG_IDLEMODE_M 0x0000000C // Idle Mode +#define LCD_SYSCFG_IDLEMODE_FORCE \ + 0x00000000 // Force-idle mode: local target's + // idle state follows + // (acknowledges) the system's idle + // requests unconditionally, that + // is, regardless of the IP + // module's internal requirements. + // Backup mode, for debug only +#define LCD_SYSCFG_IDLEMODE_NONE \ + 0x00000004 // No-idle mode: local target never + // enters idle state. Backup mode, + // for debug only +#define LCD_SYSCFG_IDLEMODE_SMART \ + 0x00000008 // Smart-idle mode: local target's + // idle state eventually follows + // (acknowledges) the system's idle + // requests, depending on the IP + // module's internal requirements. + // IP module shall not generate + // (IRQ- or DMA-requestrelated) + // wakeup events + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_RISSET register. +// +//***************************************************************************** +#define LCD_RISSET_EOF1 0x00000200 // DMA End-of-Frame 1 Raw Interrupt + // Status and Set +#define LCD_RISSET_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt + // Status and Set +#define LCD_RISSET_PALLOAD 0x00000040 // DMA Palette Loaded Raw Interrupt + // Status and Set +#define LCD_RISSET_FIFOU 0x00000020 // DMA FIFO Underflow Raw Interrupt + // Status and Set +#define LCD_RISSET_ACBS 0x00000008 // AC Bias Count Raw Interrupt + // Status and Set +#define LCD_RISSET_SYNCS 0x00000004 // Frame Synchronization Lost Raw + // Interrupt Status and Set +#define LCD_RISSET_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt +#define LCD_RISSET_DONE 0x00000001 // Raster or LIDD Frame Done + // (shared, depends on whether + // Raster or LIDD mode enabled) Raw + // Interrupt Status and Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_MISCLR register. +// +//***************************************************************************** +#define LCD_MISCLR_EOF1 0x00000200 // DMA End-of-Frame 1 Enabled + // Interrupt and Clear +#define LCD_MISCLR_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt + // and Clear +#define LCD_MISCLR_PALLOAD 0x00000040 // DMA Palette Loaded Enabled + // Interrupt and Clear +#define LCD_MISCLR_FIFOU 0x00000020 // DMA FIFO Underflow Enabled + // Interrupt and Clear +#define LCD_MISCLR_ACBS 0x00000008 // AC Bias Count Enabled Interrupt + // and Clear +#define LCD_MISCLR_SYNCS 0x00000004 // Frame Synchronization Lost + // Enabled Interrupt and Clear +#define LCD_MISCLR_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt +#define LCD_MISCLR_DONE 0x00000001 // Raster or LIDD Frame Done + // (shared, depends on whether + // Raster or LIDD mode enabled) + // Enabled Interrupt and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_IM register. +// +//***************************************************************************** +#define LCD_IM_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt + // Enable Set +#define LCD_IM_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt + // Enable Set +#define LCD_IM_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt + // Enable Set +#define LCD_IM_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt + // Enable Set +#define LCD_IM_ACBS 0x00000008 // AC Bias Count Interrupt Enable + // Set +#define LCD_IM_SYNCS 0x00000004 // Frame Synchronization Lost + // Interrupt Enable Set +#define LCD_IM_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt + // Enable Set +#define LCD_IM_DONE 0x00000001 // Raster or LIDD Frame Done + // (shared, depends on whether + // Raster or LIDD mode enabled) + // Interrupt Enable Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_IENC register. +// +//***************************************************************************** +#define LCD_IENC_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt + // Enable Clear +#define LCD_IENC_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt + // Enable Clear +#define LCD_IENC_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt + // Enable Clear +#define LCD_IENC_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt + // Enable Clear +#define LCD_IENC_ACBS 0x00000008 // AC Bias Count Interrupt Enable + // Clear +#define LCD_IENC_SYNCS 0x00000004 // Frame Synchronization Lost + // Interrupt Enable Clear +#define LCD_IENC_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt + // Enable Clear +#define LCD_IENC_DONE 0x00000001 // Raster or LIDD Frame Done + // (shared, depends on whether + // Raster or LIDD mode enabled) + // Interrupt Enable Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_CLKEN register. +// +//***************************************************************************** +#define LCD_CLKEN_DMA 0x00000004 // DMA Clock Enable +#define LCD_CLKEN_LIDD 0x00000002 // LIDD Submodule Clock Enable +#define LCD_CLKEN_CORE 0x00000001 // LCD Core Clock Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the LCD_O_CLKRESET register. +// +//***************************************************************************** +#define LCD_CLKRESET_MAIN 0x00000008 // Software Reset for the entire + // LCD module +#define LCD_CLKRESET_DMA 0x00000004 // Software Reset for the DMA + // submodule +#define LCD_CLKRESET_LIDD 0x00000002 // Software Reset for the LIDD + // submodule (character displays) +#define LCD_CLKRESET_CORE 0x00000001 // Software Reset for the Core, + // which encompasses the Raster + // Active Matrix and Passive Matrix + // logic + +#endif // __HW_LCD_H__ diff --git a/os/common/ext/TivaWare/inc/hw_memmap.h b/os/common/ext/TivaWare/inc/hw_memmap.h new file mode 100644 index 0000000..dafd4f7 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_memmap.h @@ -0,0 +1,151 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of the device. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG0_BASE 0x40000000 // Watchdog0 +#define WATCHDOG1_BASE 0x40001000 // Watchdog1 +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI0_BASE 0x40008000 // SSI0 +#define SSI1_BASE 0x40009000 // SSI1 +#define SSI2_BASE 0x4000A000 // SSI2 +#define SSI3_BASE 0x4000B000 // SSI3 +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define UART2_BASE 0x4000E000 // UART2 +#define UART3_BASE 0x4000F000 // UART3 +#define UART4_BASE 0x40010000 // UART4 +#define UART5_BASE 0x40011000 // UART5 +#define UART6_BASE 0x40012000 // UART6 +#define UART7_BASE 0x40013000 // UART7 +#define I2C0_BASE 0x40020000 // I2C0 +#define I2C1_BASE 0x40021000 // I2C1 +#define I2C2_BASE 0x40022000 // I2C2 +#define I2C3_BASE 0x40023000 // I2C3 +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F +#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G +#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H +#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM) +#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM) +#define QEI0_BASE 0x4002C000 // QEI0 +#define QEI1_BASE 0x4002D000 // QEI1 +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define TIMER3_BASE 0x40033000 // Timer3 +#define TIMER4_BASE 0x40034000 // Timer4 +#define TIMER5_BASE 0x40035000 // Timer5 +#define WTIMER0_BASE 0x40036000 // Wide Timer0 +#define WTIMER1_BASE 0x40037000 // Wide Timer1 +#define ADC0_BASE 0x40038000 // ADC0 +#define ADC1_BASE 0x40039000 // ADC1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J +#define CAN0_BASE 0x40040000 // CAN0 +#define CAN1_BASE 0x40041000 // CAN1 +#define WTIMER2_BASE 0x4004C000 // Wide Timer2 +#define WTIMER3_BASE 0x4004D000 // Wide Timer3 +#define WTIMER4_BASE 0x4004E000 // Wide Timer4 +#define WTIMER5_BASE 0x4004F000 // Wide Timer5 +#define USB0_BASE 0x40050000 // USB 0 Controller +#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) +#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed) +#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed) +#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed) +#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed) +#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed) +#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) +#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) +#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed) +#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K +#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L +#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M +#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N +#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P +#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q +#define GPIO_PORTR_BASE 0x40067000 // General-Purpose Input/Outputs + // (GPIOs) +#define GPIO_PORTS_BASE 0x40068000 // General-Purpose Input/Outputs + // (GPIOs) +#define GPIO_PORTT_BASE 0x40069000 // General-Purpose Input/Outputs + // (GPIOs) +#define EEPROM_BASE 0x400AF000 // EEPROM memory +#define ONEWIRE0_BASE 0x400B6000 // 1-Wire Master Module +#define I2C8_BASE 0x400B8000 // I2C8 +#define I2C9_BASE 0x400B9000 // I2C9 +#define I2C4_BASE 0x400C0000 // I2C4 +#define I2C5_BASE 0x400C1000 // I2C5 +#define I2C6_BASE 0x400C2000 // I2C6 +#define I2C7_BASE 0x400C3000 // I2C7 +#define EPI0_BASE 0x400D0000 // EPI0 +#define TIMER6_BASE 0x400E0000 // General-Purpose Timers +#define TIMER7_BASE 0x400E1000 // General-Purpose Timers +#define EMAC0_BASE 0x400EC000 // Ethernet Controller +#define SYSEXC_BASE 0x400F9000 // System Exception Module +#define HIB_BASE 0x400FC000 // Hibernation Module +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define UDMA_BASE 0x400FF000 // uDMA Controller +#define CCM0_BASE 0x44030000 // Cyclical Redundancy Check (CRC) +#define SHAMD5_BASE 0x44034000 // SHA/MD5 Accelerator +#define AES_BASE 0x44036000 // Advance Encryption + // Hardware-Accelerated Module +#define DES_BASE 0x44038000 // Data Encryption Standard + // Accelerator (DES) +#define LCD0_BASE 0x44050000 // LCD Controller +// #define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +// #define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +// #define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +// #define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +// #define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/os/common/ext/TivaWare/inc/hw_nvic.h b/os/common/ext/TivaWare/inc/hw_nvic.h new file mode 100644 index 0000000..c7b3568 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_nvic.h @@ -0,0 +1,1414 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-63 Set Enable +#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable +#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable +#define NVIC_EN4 0xE000E110 // Interrupt 128-159 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-63 Clear Enable +#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable +#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable +#define NVIC_DIS4 0xE000E190 // Interrupt 128-159 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-63 Set Pending +#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending +#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending +#define NVIC_PEND4 0xE000E210 // Interrupt 128-159 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-63 Clear Pending +#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending +#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending +#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-159 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-63 Active Bit +#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit +#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit +#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-159 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority +#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority +#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority +#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority +#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority +#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority +#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority +#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority +#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority +#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority +#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority +#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority +#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority +#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority +#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority +#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority +#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority +#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority +#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority +#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority +#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt +#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control +#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address +#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating + // Point +#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI33 register. +// +//***************************************************************************** +#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI33_INTD_S 29 +#define NVIC_PRI33_INTC_S 21 +#define NVIC_PRI33_INTB_S 13 +#define NVIC_PRI33_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI34 register. +// +//***************************************************************************** +#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI34_INTD_S 29 +#define NVIC_PRI34_INTC_S 21 +#define NVIC_PRI34_INTB_S 13 +#define NVIC_PRI34_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPAC register. +// +//***************************************************************************** +#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only +#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access +#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only +#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access +#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none +#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only +#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw +#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none +#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable +#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable +#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable +#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable +#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable +#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable +#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable +#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes +#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes +#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes +#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes +#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes +#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes +#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes +#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes +#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes +#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes +#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes +#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes +#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes +#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes +#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes +#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes +#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes +#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes +#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes +#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes +#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes +#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes +#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes +#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes +#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes +#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes +#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes +#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCC register. +// +//***************************************************************************** +#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation + // Enable +#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable +#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready +#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready +#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready +#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready +#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode +#define NVIC_FPCC_USER 0x00000002 // User Privilege Level +#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCA register. +// +//***************************************************************************** +#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address +#define NVIC_FPCA_ADDRESS_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPDSC register. +// +//***************************************************************************** +#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default +#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default +#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default +#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default +#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode +#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) + // mode +#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity + // (RM) mode +#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode + +#endif // __HW_NVIC_H__ diff --git a/os/common/ext/TivaWare/inc/hw_onewire.h b/os/common/ext/TivaWare/inc/hw_onewire.h new file mode 100644 index 0000000..8910a7d --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_onewire.h @@ -0,0 +1,223 @@ +//***************************************************************************** +// +// hw_onewire.h - Macros used when accessing the One wire hardware. +// +// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_ONEWIRE_H__ +#define __HW_ONEWIRE_H__ + +//***************************************************************************** +// +// The following are defines for the One wire register offsets. +// +//***************************************************************************** +#define ONEWIRE_O_CS 0x00000000 // 1-Wire Control and Status +#define ONEWIRE_O_TIM 0x00000004 // 1-Wire Timing Override +#define ONEWIRE_O_DATW 0x00000008 // 1-Wire Data Write +#define ONEWIRE_O_DATR 0x0000000C // 1-Wire Data Read +#define ONEWIRE_O_IM 0x00000100 // 1-Wire Interrupt Mask +#define ONEWIRE_O_RIS 0x00000104 // 1-Wire Raw Interrupt Status +#define ONEWIRE_O_MIS 0x00000108 // 1-Wire Masked Interrupt Status +#define ONEWIRE_O_ICR 0x0000010C // 1-Wire Interrupt Clear +#define ONEWIRE_O_DMA 0x00000120 // 1-Wire uDMA Control +#define ONEWIRE_O_PP 0x00000FC0 // 1-Wire Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_CS register. +// +//***************************************************************************** +#define ONEWIRE_CS_USEALT 0x80000000 // Two Wire Enable +#define ONEWIRE_CS_ALTP 0x40000000 // Alternate Polarity Enable +#define ONEWIRE_CS_BSIZE_M 0x00070000 // Last Byte Size +#define ONEWIRE_CS_BSIZE_8 0x00000000 // 8 bits (1 byte) +#define ONEWIRE_CS_BSIZE_1 0x00010000 // 1 bit +#define ONEWIRE_CS_BSIZE_2 0x00020000 // 2 bits +#define ONEWIRE_CS_BSIZE_3 0x00030000 // 3 bits +#define ONEWIRE_CS_BSIZE_4 0x00040000 // 4 bits +#define ONEWIRE_CS_BSIZE_5 0x00050000 // 5 bits +#define ONEWIRE_CS_BSIZE_6 0x00060000 // 6 bits +#define ONEWIRE_CS_BSIZE_7 0x00070000 // 7 bits +#define ONEWIRE_CS_STUCK 0x00000400 // STUCK Status +#define ONEWIRE_CS_NOATR 0x00000200 // Answer-to-Reset Status +#define ONEWIRE_CS_BUSY 0x00000100 // Busy Status +#define ONEWIRE_CS_SKATR 0x00000080 // Skip Answer-to-Reset Enable +#define ONEWIRE_CS_LSAM 0x00000040 // Late Sample Enable +#define ONEWIRE_CS_ODRV 0x00000020 // Overdrive Enable +#define ONEWIRE_CS_SZ_M 0x00000018 // Data Operation Size +#define ONEWIRE_CS_OP_M 0x00000006 // Operation Request +#define ONEWIRE_CS_OP_NONE 0x00000000 // No operation +#define ONEWIRE_CS_OP_RD 0x00000002 // Read +#define ONEWIRE_CS_OP_WR 0x00000004 // Write +#define ONEWIRE_CS_OP_WRRD 0x00000006 // Write/Read +#define ONEWIRE_CS_RST 0x00000001 // Reset Request +#define ONEWIRE_CS_SZ_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_TIM register. +// +//***************************************************************************** +#define ONEWIRE_TIM_W1TIM_M 0xF0000000 // Value '1' Timing +#define ONEWIRE_TIM_W0TIM_M 0x0F800000 // Value '0' Timing +#define ONEWIRE_TIM_W0REST_M 0x00780000 // Rest Time +#define ONEWIRE_TIM_W1SAM_M 0x00078000 // Sample Time +#define ONEWIRE_TIM_ATRSAM_M 0x00007800 // Answer-to-Reset Sample +#define ONEWIRE_TIM_ATRTIM_M 0x000007C0 // Answer-to-Reset/Rest Period +#define ONEWIRE_TIM_RSTTIM_M 0x0000003F // Reset Low Time +#define ONEWIRE_TIM_W1TIM_S 28 +#define ONEWIRE_TIM_W0TIM_S 23 +#define ONEWIRE_TIM_W0REST_S 19 +#define ONEWIRE_TIM_W1SAM_S 15 +#define ONEWIRE_TIM_ATRSAM_S 11 +#define ONEWIRE_TIM_ATRTIM_S 6 +#define ONEWIRE_TIM_RSTTIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_DATW register. +// +//***************************************************************************** +#define ONEWIRE_DATW_B3_M 0xFF000000 // Upper Data Byte +#define ONEWIRE_DATW_B2_M 0x00FF0000 // Upper Middle Data Byte +#define ONEWIRE_DATW_B1_M 0x0000FF00 // Lower Middle Data Byte +#define ONEWIRE_DATW_B0_M 0x000000FF // Lowest Data Byte +#define ONEWIRE_DATW_B3_S 24 +#define ONEWIRE_DATW_B2_S 16 +#define ONEWIRE_DATW_B1_S 8 +#define ONEWIRE_DATW_B0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_DATR register. +// +//***************************************************************************** +#define ONEWIRE_DATR_B3_M 0xFF000000 // Upper Data Byte +#define ONEWIRE_DATR_B2_M 0x00FF0000 // Upper Middle Data Byte +#define ONEWIRE_DATR_B1_M 0x0000FF00 // Lower Middle Data Byte +#define ONEWIRE_DATR_B0_M 0x000000FF // Lowest Data Byte +#define ONEWIRE_DATR_B3_S 24 +#define ONEWIRE_DATR_B2_S 16 +#define ONEWIRE_DATR_B1_S 8 +#define ONEWIRE_DATR_B0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_IM register. +// +//***************************************************************************** +#define ONEWIRE_IM_DMA 0x00000010 // DMA Done Interrupt Mask +#define ONEWIRE_IM_STUCK 0x00000008 // Stuck Status Interrupt Mask +#define ONEWIRE_IM_NOATR 0x00000004 // No Answer-to-Reset Interrupt + // Mask +#define ONEWIRE_IM_OPC 0x00000002 // Operation Complete Interrupt + // Mask +#define ONEWIRE_IM_RST 0x00000001 // Reset Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_RIS register. +// +//***************************************************************************** +#define ONEWIRE_RIS_DMA 0x00000010 // DMA Done Raw Interrupt Status +#define ONEWIRE_RIS_STUCK 0x00000008 // Stuck Status Raw Interrupt + // Status +#define ONEWIRE_RIS_NOATR 0x00000004 // No Answer-to-Reset Raw Interrupt + // Status +#define ONEWIRE_RIS_OPC 0x00000002 // Operation Complete Raw Interrupt + // Status +#define ONEWIRE_RIS_RST 0x00000001 // Reset Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_MIS register. +// +//***************************************************************************** +#define ONEWIRE_MIS_DMA 0x00000010 // DMA Done Masked Interrupt Status +#define ONEWIRE_MIS_STUCK 0x00000008 // Stuck Status Masked Interrupt + // Status +#define ONEWIRE_MIS_NOATR 0x00000004 // No Answer-to-Reset Masked + // Interrupt Status +#define ONEWIRE_MIS_OPC 0x00000002 // Operation Complete Masked + // Interrupt Status +#define ONEWIRE_MIS_RST 0x00000001 // Reset Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_ICR register. +// +//***************************************************************************** +#define ONEWIRE_ICR_DMA 0x00000010 // DMA Done Interrupt Clear +#define ONEWIRE_ICR_STUCK 0x00000008 // Stuck Status Interrupt Clear +#define ONEWIRE_ICR_NOATR 0x00000004 // No Answer-to-Reset Interrupt + // Clear +#define ONEWIRE_ICR_OPC 0x00000002 // Operation Complete Interrupt + // Clear +#define ONEWIRE_ICR_RST 0x00000001 // Reset Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_DMA register. +// +//***************************************************************************** +#define ONEWIRE_DMA_SG 0x00000008 // Scatter-Gather Enable +#define ONEWIRE_DMA_DMAOP_M 0x00000006 // uDMA Operation +#define ONEWIRE_DMA_DMAOP_DIS 0x00000000 // uDMA disabled +#define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002 // uDMA single read: 1-Wire + // requests uDMA to read + // ONEWIREDATR register after each + // read transaction +#define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004 // uDMA multiple write: 1-Wire + // requests uDMA to load whenever + // the ONEWIREDATW register is + // empty +#define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006 // uDMA multiple read: An initial + // read occurs and subsequent reads + // start after uDMA has read the + // ONEWIREDATR register +#define ONEWIRE_DMA_RST 0x00000001 // uDMA Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_PP register. +// +//***************************************************************************** +#define ONEWIRE_PP_DMAP 0x00000010 // uDMA Present +#define ONEWIRE_PP_CNT_M 0x00000003 // 1-Wire Bus Count +#define ONEWIRE_PP_CNT_S 0 + +#endif // __HW_ONEWIRE_H__ diff --git a/os/common/ext/TivaWare/inc/hw_pwm.h b/os/common/ext/TivaWare/inc/hw_pwm.h new file mode 100644 index 0000000..00d42bf --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_pwm.h @@ -0,0 +1,1885 @@ +//***************************************************************************** +// +// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_PWM_H__ +#define __HW_PWM_H__ + +//***************************************************************************** +// +// The following are defines for the PWM register offsets. +// +//***************************************************************************** +#define PWM_O_CTL 0x00000000 // PWM Master Control +#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync +#define PWM_O_ENABLE 0x00000008 // PWM Output Enable +#define PWM_O_INVERT 0x0000000C // PWM Output Inversion +#define PWM_O_FAULT 0x00000010 // PWM Output Fault +#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable +#define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status +#define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear +#define PWM_O_STATUS 0x00000020 // PWM Status +#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value +#define PWM_O_ENUPD 0x00000028 // PWM Enable Update +#define PWM_O_0_CTL 0x00000040 // PWM0 Control +#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger + // Enable +#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status +#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear +#define PWM_O_0_LOAD 0x00000050 // PWM0 Load +#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter +#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A +#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B +#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control +#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control +#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control +#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay +#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band + // Falling-Edge-Delay +#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0 +#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1 +#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period +#define PWM_O_1_CTL 0x00000080 // PWM1 Control +#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger + // Enable +#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status +#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear +#define PWM_O_1_LOAD 0x00000090 // PWM1 Load +#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter +#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A +#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B +#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control +#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control +#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control +#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay +#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band + // Falling-Edge-Delay +#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0 +#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1 +#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period +#define PWM_O_2_CTL 0x000000C0 // PWM2 Control +#define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger + // Enable +#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status +#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear +#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load +#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter +#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A +#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B +#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control +#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control +#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control +#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay +#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band + // Falling-Edge-Delay +#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0 +#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1 +#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period +#define PWM_O_3_CTL 0x00000100 // PWM3 Control +#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger + // Enable +#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status +#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear +#define PWM_O_3_LOAD 0x00000110 // PWM3 Load +#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter +#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A +#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B +#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control +#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control +#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control +#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay +#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band + // Falling-Edge-Delay +#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0 +#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1 +#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period +#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense +#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0 +#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1 +#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense +#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0 +#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1 +#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense +#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0 +#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1 +#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense +#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0 +#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1 +#define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties +#define PWM_O_CC 0x00000FC8 // PWM Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_CTL register. +// +//***************************************************************************** +#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 +#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 +#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 +#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_SYNC register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter +#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENABLE register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM7EN 0x00000080 // MnPWM7 Output Enable +#define PWM_ENABLE_PWM6EN 0x00000040 // MnPWM6 Output Enable +#define PWM_ENABLE_PWM5EN 0x00000020 // MnPWM5 Output Enable +#define PWM_ENABLE_PWM4EN 0x00000010 // MnPWM4 Output Enable +#define PWM_ENABLE_PWM3EN 0x00000008 // MnPWM3 Output Enable +#define PWM_ENABLE_PWM2EN 0x00000004 // MnPWM2 Output Enable +#define PWM_ENABLE_PWM1EN 0x00000002 // MnPWM1 Output Enable +#define PWM_ENABLE_PWM0EN 0x00000001 // MnPWM0 Output Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INVERT register. +// +//***************************************************************************** +#define PWM_INVERT_PWM7INV 0x00000080 // Invert MnPWM7 Signal +#define PWM_INVERT_PWM6INV 0x00000040 // Invert MnPWM6 Signal +#define PWM_INVERT_PWM5INV 0x00000020 // Invert MnPWM5 Signal +#define PWM_INVERT_PWM4INV 0x00000010 // Invert MnPWM4 Signal +#define PWM_INVERT_PWM3INV 0x00000008 // Invert MnPWM3 Signal +#define PWM_INVERT_PWM2INV 0x00000004 // Invert MnPWM2 Signal +#define PWM_INVERT_PWM1INV 0x00000002 // Invert MnPWM1 Signal +#define PWM_INVERT_PWM0INV 0x00000001 // Invert MnPWM0 Signal + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULT register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT7 0x00000080 // MnPWM7 Fault +#define PWM_FAULT_FAULT6 0x00000040 // MnPWM6 Fault +#define PWM_FAULT_FAULT5 0x00000020 // MnPWM5 Fault +#define PWM_FAULT_FAULT4 0x00000010 // MnPWM4 Fault +#define PWM_FAULT_FAULT3 0x00000008 // MnPWM3 Fault +#define PWM_FAULT_FAULT2 0x00000004 // MnPWM2 Fault +#define PWM_FAULT_FAULT1 0x00000002 // MnPWM1 Fault +#define PWM_FAULT_FAULT0 0x00000001 // MnPWM0 Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INTEN register. +// +//***************************************************************************** +#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3 +#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2 +#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 +#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 +#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable +#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable +#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable +#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_RIS register. +// +//***************************************************************************** +#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3 +#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2 +#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 +#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 +#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted +#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted +#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted +#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ISC register. +// +//***************************************************************************** +#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted +#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted +#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted +#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted +#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status +#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status +#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status +#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_STATUS register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status +#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status +#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status +#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULTVAL register. +// +//***************************************************************************** +#define PWM_FAULTVAL_PWM7 0x00000080 // MnPWM7 Fault Value +#define PWM_FAULTVAL_PWM6 0x00000040 // MnPWM6 Fault Value +#define PWM_FAULTVAL_PWM5 0x00000020 // MnPWM5 Fault Value +#define PWM_FAULTVAL_PWM4 0x00000010 // MnPWM4 Fault Value +#define PWM_FAULTVAL_PWM3 0x00000008 // MnPWM3 Fault Value +#define PWM_FAULTVAL_PWM2 0x00000004 // MnPWM2 Fault Value +#define PWM_FAULTVAL_PWM1 0x00000002 // MnPWM1 Fault Value +#define PWM_FAULTVAL_PWM0 0x00000001 // MnPWM0 Fault Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENUPD register. +// +//***************************************************************************** +#define PWM_ENUPD_ENUPD7_M 0x0000C000 // MnPWM7 Enable Update Mode +#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized +#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized +#define PWM_ENUPD_ENUPD6_M 0x00003000 // MnPWM6 Enable Update Mode +#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized +#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized +#define PWM_ENUPD_ENUPD5_M 0x00000C00 // MnPWM5 Enable Update Mode +#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized +#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized +#define PWM_ENUPD_ENUPD4_M 0x00000300 // MnPWM4 Enable Update Mode +#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized +#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized +#define PWM_ENUPD_ENUPD3_M 0x000000C0 // MnPWM3 Enable Update Mode +#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized +#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized +#define PWM_ENUPD_ENUPD2_M 0x00000030 // MnPWM2 Enable Update Mode +#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized +#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized +#define PWM_ENUPD_ENUPD1_M 0x0000000C // MnPWM1 Enable Update Mode +#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized +#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized +#define PWM_ENUPD_ENUPD0_M 0x00000003 // MnPWM0 Enable Update Mode +#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized +#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CTL register. +// +//***************************************************************************** +#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_0_CTL_MODE 0x00000002 // Counter Mode +#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_INTEN register. +// +//***************************************************************************** +#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_RIS register. +// +//***************************************************************************** +#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_ISC register. +// +//***************************************************************************** +#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_LOAD register. +// +//***************************************************************************** +#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_0_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_COUNT register. +// +//***************************************************************************** +#define PWM_0_COUNT_M 0x0000FFFF // Counter Value +#define PWM_0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPA register. +// +//***************************************************************************** +#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value +#define PWM_0_CMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPB register. +// +//***************************************************************************** +#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value +#define PWM_0_CMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENA register. +// +//***************************************************************************** +#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_0_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_0_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_0_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_0_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENB register. +// +//***************************************************************************** +#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_0_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_0_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_0_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_0_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBCTL register. +// +//***************************************************************************** +#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBRISE register. +// +//***************************************************************************** +#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay +#define PWM_0_DBRISE_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBFALL register. +// +//***************************************************************************** +#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay +#define PWM_0_DBFALL_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period +#define PWM_0_MINFLTPER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CTL register. +// +//***************************************************************************** +#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_1_CTL_MODE 0x00000002 // Counter Mode +#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_INTEN register. +// +//***************************************************************************** +#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_RIS register. +// +//***************************************************************************** +#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_ISC register. +// +//***************************************************************************** +#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_LOAD register. +// +//***************************************************************************** +#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_1_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_COUNT register. +// +//***************************************************************************** +#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_1_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPA register. +// +//***************************************************************************** +#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_1_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPB register. +// +//***************************************************************************** +#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_1_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENA register. +// +//***************************************************************************** +#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_1_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_1_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_1_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_1_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENB register. +// +//***************************************************************************** +#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_1_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_1_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_1_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_1_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBCTL register. +// +//***************************************************************************** +#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBRISE register. +// +//***************************************************************************** +#define PWM_1_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_1_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBFALL register. +// +//***************************************************************************** +#define PWM_1_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_1_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_1_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CTL register. +// +//***************************************************************************** +#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_2_CTL_MODE 0x00000002 // Counter Mode +#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_INTEN register. +// +//***************************************************************************** +#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_RIS register. +// +//***************************************************************************** +#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_ISC register. +// +//***************************************************************************** +#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_LOAD register. +// +//***************************************************************************** +#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_2_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_COUNT register. +// +//***************************************************************************** +#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_2_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPA register. +// +//***************************************************************************** +#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_2_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPB register. +// +//***************************************************************************** +#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_2_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENA register. +// +//***************************************************************************** +#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_2_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_2_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_2_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_2_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENB register. +// +//***************************************************************************** +#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_2_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_2_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_2_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_2_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBCTL register. +// +//***************************************************************************** +#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBRISE register. +// +//***************************************************************************** +#define PWM_2_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_2_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBFALL register. +// +//***************************************************************************** +#define PWM_2_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_2_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_2_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CTL register. +// +//***************************************************************************** +#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_3_CTL_MODE 0x00000002 // Counter Mode +#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_INTEN register. +// +//***************************************************************************** +#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_RIS register. +// +//***************************************************************************** +#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_ISC register. +// +//***************************************************************************** +#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_LOAD register. +// +//***************************************************************************** +#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_3_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_COUNT register. +// +//***************************************************************************** +#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_3_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPA register. +// +//***************************************************************************** +#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_3_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPB register. +// +//***************************************************************************** +#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_3_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENA register. +// +//***************************************************************************** +#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_3_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_3_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_3_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_3_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENB register. +// +//***************************************************************************** +#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_3_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_3_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_3_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_3_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBCTL register. +// +//***************************************************************************** +#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBRISE register. +// +//***************************************************************************** +#define PWM_3_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_3_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBFALL register. +// +//***************************************************************************** +#define PWM_3_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_3_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_3_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSEN register. +// +//***************************************************************************** +#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSEN register. +// +//***************************************************************************** +#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSEN register. +// +//***************************************************************************** +#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSEN register. +// +//***************************************************************************** +#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_PP register. +// +//***************************************************************************** +#define PWM_PP_GCNT_M 0x0000000F // Generators +#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs (per PWM unit) +#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization +#define PWM_PP_EFAULT 0x00000200 // Extended Fault +#define PWM_PP_ONE 0x00000400 // One-Shot Mode +#define PWM_PP_GCNT_S 0 +#define PWM_PP_FCNT_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_CC register. +// +//***************************************************************************** +#define PWM_CC_USEPWM 0x00000100 // Use PWM Clock Divisor +#define PWM_CC_PWMDIV_M 0x00000007 // PWM Clock Divider +#define PWM_CC_PWMDIV_2 0x00000000 // /2 +#define PWM_CC_PWMDIV_4 0x00000001 // /4 +#define PWM_CC_PWMDIV_8 0x00000002 // /8 +#define PWM_CC_PWMDIV_16 0x00000003 // /16 +#define PWM_CC_PWMDIV_32 0x00000004 // /32 +#define PWM_CC_PWMDIV_64 0x00000005 // /64 + +//***************************************************************************** +// +// The following are defines for the PWM Generator standard offsets. +// +//***************************************************************************** +#define PWM_O_X_CTL 0x00000000 // Gen Control Reg +#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg +#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg +#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg +#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg +#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg +#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg +#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg +#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg +#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg +#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg +#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg +#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg +#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition +#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition +#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension +#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base +#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base +#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base +#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CTL register. +// +//***************************************************************************** +#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_X_CTL_MODE 0x00000002 // Counter Mode +#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_INTEN register. +// +//***************************************************************************** +#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_RIS register. +// +//***************************************************************************** +#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_ISC register. +// +//***************************************************************************** +#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_LOAD register. +// +//***************************************************************************** +#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_X_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_COUNT register. +// +//***************************************************************************** +#define PWM_X_COUNT_M 0x0000FFFF // Counter Value +#define PWM_X_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CMPA register. +// +//***************************************************************************** +#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value +#define PWM_X_CMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_CMPB register. +// +//***************************************************************************** +#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value +#define PWM_X_CMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_GENA register. +// +//***************************************************************************** +#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_X_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_X_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_X_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_X_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_X_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_X_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_X_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_X_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_GENB register. +// +//***************************************************************************** +#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_X_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_X_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_X_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_X_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_X_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_X_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_X_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_X_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBCTL register. +// +//***************************************************************************** +#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBRISE register. +// +//***************************************************************************** +#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay +#define PWM_X_DBRISE_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_DBFALL register. +// +//***************************************************************************** +#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay +#define PWM_X_DBFALL_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input +#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input +#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period +#define PWM_X_MINFLTPER_S 0 + +//***************************************************************************** +// +// The following are defines for the PWM Generator extended offsets. +// +//***************************************************************************** +#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense +#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status +#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status +#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base +#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base +#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base +#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSEN register. +// +//***************************************************************************** +#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense +#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense +#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3 +#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2 +#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +#endif // __HW_PWM_H__ diff --git a/os/common/ext/TivaWare/inc/hw_qei.h b/os/common/ext/TivaWare/inc/hw_qei.h new file mode 100644 index 0000000..93c4a07 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_qei.h @@ -0,0 +1,178 @@ +//***************************************************************************** +// +// hw_qei.h - Macros used when accessing the QEI hardware. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_QEI_H__ +#define __HW_QEI_H__ + +//***************************************************************************** +// +// The following are defines for the QEI register offsets. +// +//***************************************************************************** +#define QEI_O_CTL 0x00000000 // QEI Control +#define QEI_O_STAT 0x00000004 // QEI Status +#define QEI_O_POS 0x00000008 // QEI Position +#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position +#define QEI_O_LOAD 0x00000010 // QEI Timer Load +#define QEI_O_TIME 0x00000014 // QEI Timer +#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter +#define QEI_O_SPEED 0x0000001C // QEI Velocity +#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable +#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status +#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_CTL register. +// +//***************************************************************************** +#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count +#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter +#define QEI_CTL_STALLEN 0x00001000 // Stall QEI +#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse +#define QEI_CTL_INVB 0x00000400 // Invert PhB +#define QEI_CTL_INVA 0x00000200 // Invert PhA +#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity +#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 +#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 +#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 +#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 +#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 +#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 +#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 +#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 +#define QEI_CTL_VELEN 0x00000020 // Capture Velocity +#define QEI_CTL_RESMODE 0x00000010 // Reset Mode +#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode +#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode +#define QEI_CTL_SWAP 0x00000002 // Swap Signals +#define QEI_CTL_ENABLE 0x00000001 // Enable QEI +#define QEI_CTL_FILTCNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation +#define QEI_STAT_ERROR 0x00000001 // Error Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator + // Value +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator + // Value +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Velocity +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable +#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt + // Enable +#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable +#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected +#define QEI_RIS_DIR 0x00000004 // Direction Change Detected +#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired +#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_ISC register. +// +//***************************************************************************** +#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt +#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt +#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt +#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt + +#endif // __HW_QEI_H__ diff --git a/os/common/ext/TivaWare/inc/hw_shamd5.h b/os/common/ext/TivaWare/inc/hw_shamd5.h new file mode 100644 index 0000000..1f697fe --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_shamd5.h @@ -0,0 +1,548 @@ +//***************************************************************************** +// +// hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware. +// +// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SHAMD5_H__ +#define __HW_SHAMD5_H__ + +//***************************************************************************** +// +// The following are defines for the SHA/MD5 register offsets. +// +//***************************************************************************** +#define SHAMD5_O_ODIGEST_A 0x00000000 // SHA Outer Digest A +#define SHAMD5_O_ODIGEST_B 0x00000004 // SHA Outer Digest B +#define SHAMD5_O_ODIGEST_C 0x00000008 // SHA Outer Digest C +#define SHAMD5_O_ODIGEST_D 0x0000000C // SHA Outer Digest D +#define SHAMD5_O_ODIGEST_E 0x00000010 // SHA Outer Digest E +#define SHAMD5_O_ODIGEST_F 0x00000014 // SHA Outer Digest F +#define SHAMD5_O_ODIGEST_G 0x00000018 // SHA Outer Digest G +#define SHAMD5_O_ODIGEST_H 0x0000001C // SHA Outer Digest H +#define SHAMD5_O_IDIGEST_A 0x00000020 // SHA Inner Digest A +#define SHAMD5_O_IDIGEST_B 0x00000024 // SHA Inner Digest B +#define SHAMD5_O_IDIGEST_C 0x00000028 // SHA Inner Digest C +#define SHAMD5_O_IDIGEST_D 0x0000002C // SHA Inner Digest D +#define SHAMD5_O_IDIGEST_E 0x00000030 // SHA Inner Digest E +#define SHAMD5_O_IDIGEST_F 0x00000034 // SHA Inner Digest F +#define SHAMD5_O_IDIGEST_G 0x00000038 // SHA Inner Digest G +#define SHAMD5_O_IDIGEST_H 0x0000003C // SHA Inner Digest H +#define SHAMD5_O_DIGEST_COUNT 0x00000040 // SHA Digest Count +#define SHAMD5_O_MODE 0x00000044 // SHA Mode +#define SHAMD5_O_LENGTH 0x00000048 // SHA Length +#define SHAMD5_O_DATA_0_IN 0x00000080 // SHA Data 0 Input +#define SHAMD5_O_DATA_1_IN 0x00000084 // SHA Data 1 Input +#define SHAMD5_O_DATA_2_IN 0x00000088 // SHA Data 2 Input +#define SHAMD5_O_DATA_3_IN 0x0000008C // SHA Data 3 Input +#define SHAMD5_O_DATA_4_IN 0x00000090 // SHA Data 4 Input +#define SHAMD5_O_DATA_5_IN 0x00000094 // SHA Data 5 Input +#define SHAMD5_O_DATA_6_IN 0x00000098 // SHA Data 6 Input +#define SHAMD5_O_DATA_7_IN 0x0000009C // SHA Data 7 Input +#define SHAMD5_O_DATA_8_IN 0x000000A0 // SHA Data 8 Input +#define SHAMD5_O_DATA_9_IN 0x000000A4 // SHA Data 9 Input +#define SHAMD5_O_DATA_10_IN 0x000000A8 // SHA Data 10 Input +#define SHAMD5_O_DATA_11_IN 0x000000AC // SHA Data 11 Input +#define SHAMD5_O_DATA_12_IN 0x000000B0 // SHA Data 12 Input +#define SHAMD5_O_DATA_13_IN 0x000000B4 // SHA Data 13 Input +#define SHAMD5_O_DATA_14_IN 0x000000B8 // SHA Data 14 Input +#define SHAMD5_O_DATA_15_IN 0x000000BC // SHA Data 15 Input +#define SHAMD5_O_REVISION 0x00000100 // SHA Revision +#define SHAMD5_O_SYSCONFIG 0x00000110 // SHA System Configuration +#define SHAMD5_O_SYSSTATUS 0x00000114 // SHA System Status +#define SHAMD5_O_IRQSTATUS 0x00000118 // SHA Interrupt Status +#define SHAMD5_O_IRQENABLE 0x0000011C // SHA Interrupt Enable +#define SHAMD5_O_DMAIM 0xFFFFC010 // SHA DMA Interrupt Mask +#define SHAMD5_O_DMARIS 0xFFFFC014 // SHA DMA Raw Interrupt Status +#define SHAMD5_O_DMAMIS 0xFFFFC018 // SHA DMA Masked Interrupt Status +#define SHAMD5_O_DMAIC 0xFFFFC01C // SHA DMA Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_A_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_B_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_C_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_D_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_E_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_F_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_G_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H +// register. +// +//***************************************************************************** +#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_ODIGEST_H_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_A_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_B_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_C_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_D_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_E_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_F_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_G_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H +// register. +// +//***************************************************************************** +#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_IDIGEST_H_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT +// register. +// +//***************************************************************************** +#define SHAMD5_DIGEST_COUNT_M 0xFFFFFFFF // Digest Count +#define SHAMD5_DIGEST_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_MODE register. +// +//***************************************************************************** +#define SHAMD5_MODE_HMAC_OUTER_HASH \ + 0x00000080 // HMAC Outer Hash Processing + // Enable +#define SHAMD5_MODE_HMAC_KEY_PROC \ + 0x00000020 // HMAC Key Processing Enable +#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding, the + // Hash/HMAC will be 'closed' at + // the end of the block, as per + // MD5/SHA-1/SHA-2 specification +#define SHAMD5_MODE_ALGO_CONSTANT \ + 0x00000008 // The initial digest register will + // be overwritten with the + // algorithm constants for the + // selected algorithm when hashing + // and the initial digest count + // register will be reset to 0 +#define SHAMD5_MODE_ALGO_M 0x00000007 // Hash Algorithm +#define SHAMD5_MODE_ALGO_MD5 0x00000000 // MD5 +#define SHAMD5_MODE_ALGO_SHA1 0x00000002 // SHA-1 +#define SHAMD5_MODE_ALGO_SHA224 0x00000004 // SHA-224 +#define SHAMD5_MODE_ALGO_SHA256 0x00000006 // SHA-256 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_LENGTH +// register. +// +//***************************************************************************** +#define SHAMD5_LENGTH_M 0xFFFFFFFF // Block Length/Remaining Byte + // Count +#define SHAMD5_LENGTH_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_0_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_1_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_2_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_3_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_4_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_5_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_6_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_7_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_8_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_9_IN_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_10_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_10_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_11_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_11_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_12_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_12_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_13_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_13_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_14_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_14_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN +// register. +// +//***************************************************************************** +#define SHAMD5_DATA_15_IN_DATA_M \ + 0xFFFFFFFF // Digest/Key Data +#define SHAMD5_DATA_15_IN_DATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_REVISION +// register. +// +//***************************************************************************** +#define SHAMD5_REVISION_M 0xFFFFFFFF // Revision Number +#define SHAMD5_REVISION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG +// register. +// +//***************************************************************************** +#define SHAMD5_SYSCONFIG_SADVANCED \ + 0x00000080 // Advanced Mode Enable +#define SHAMD5_SYSCONFIG_SIDLE_M \ + 0x00000030 // Sidle mode +#define SHAMD5_SYSCONFIG_SIDLE_FORCE \ + 0x00000000 // Force-idle mode +#define SHAMD5_SYSCONFIG_DMA_EN 0x00000008 // uDMA Request Enable +#define SHAMD5_SYSCONFIG_IT_EN 0x00000004 // Interrupt Enable +#define SHAMD5_SYSCONFIG_SOFTRESET \ + 0x00000002 // Soft reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS +// register. +// +//***************************************************************************** +#define SHAMD5_SYSSTATUS_RESETDONE \ + 0x00000001 // Reset done status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS +// register. +// +//***************************************************************************** +#define SHAMD5_IRQSTATUS_CONTEXT_READY \ + 0x00000008 // Context Ready Status +#define SHAMD5_IRQSTATUS_INPUT_READY \ + 0x00000002 // Input Ready Status +#define SHAMD5_IRQSTATUS_OUTPUT_READY \ + 0x00000001 // Output Ready Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE +// register. +// +//***************************************************************************** +#define SHAMD5_IRQENABLE_CONTEXT_READY \ + 0x00000008 // Mask for context ready interrupt +#define SHAMD5_IRQENABLE_INPUT_READY \ + 0x00000002 // Mask for input ready interrupt +#define SHAMD5_IRQENABLE_OUTPUT_READY \ + 0x00000001 // Mask for output ready interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DMAIM register. +// +//***************************************************************************** +#define SHAMD5_DMAIM_COUT 0x00000004 // Context Out DMA Done Interrupt + // Mask +#define SHAMD5_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask +#define SHAMD5_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DMARIS +// register. +// +//***************************************************************************** +#define SHAMD5_DMARIS_COUT 0x00000004 // Context Out DMA Done Raw + // Interrupt Status +#define SHAMD5_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt + // Status +#define SHAMD5_DMARIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DMAMIS +// register. +// +//***************************************************************************** +#define SHAMD5_DMAMIS_COUT 0x00000004 // Context Out DMA Done Masked + // Interrupt Status +#define SHAMD5_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked + // Interrupt Status +#define SHAMD5_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DMAIC register. +// +//***************************************************************************** +#define SHAMD5_DMAIC_COUT 0x00000004 // Context Out DMA Done Masked + // Interrupt Status +#define SHAMD5_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear +#define SHAMD5_DMAIC_CIN 0x00000001 // Context In DMA Done Raw + // Interrupt Status + +#endif // __HW_SHAMD5_H__ diff --git a/os/common/ext/TivaWare/inc/hw_ssi.h b/os/common/ext/TivaWare/inc/hw_ssi.h new file mode 100644 index 0000000..3a1503d --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_ssi.h @@ -0,0 +1,237 @@ +//***************************************************************************** +// +// hw_ssi.h - Macros used when accessing the SSI hardware. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// The following are defines for the SSI register offsets. +// +//***************************************************************************** +#define SSI_O_CR0 0x00000000 // SSI Control 0 +#define SSI_O_CR1 0x00000004 // SSI Control 1 +#define SSI_O_DR 0x00000008 // SSI Data +#define SSI_O_SR 0x0000000C // SSI Status +#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale +#define SSI_O_IM 0x00000014 // SSI Interrupt Mask +#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status +#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status +#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear +#define SSI_O_DMACTL 0x00000024 // SSI DMA Control +#define SSI_O_PP 0x00000FC0 // SSI Peripheral Properties +#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR0 register. +// +//***************************************************************************** +#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate +#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase +#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity +#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select +#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format +#define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format +#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format +#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select +#define SSI_CR0_DSS_4 0x00000003 // 4-bit data +#define SSI_CR0_DSS_5 0x00000004 // 5-bit data +#define SSI_CR0_DSS_6 0x00000005 // 6-bit data +#define SSI_CR0_DSS_7 0x00000006 // 7-bit data +#define SSI_CR0_DSS_8 0x00000007 // 8-bit data +#define SSI_CR0_DSS_9 0x00000008 // 9-bit data +#define SSI_CR0_DSS_10 0x00000009 // 10-bit data +#define SSI_CR0_DSS_11 0x0000000A // 11-bit data +#define SSI_CR0_DSS_12 0x0000000B // 12-bit data +#define SSI_CR0_DSS_13 0x0000000C // 13-bit data +#define SSI_CR0_DSS_14 0x0000000D // 14-bit data +#define SSI_CR0_DSS_15 0x0000000E // 15-bit data +#define SSI_CR0_DSS_16 0x0000000F // 16-bit data +#define SSI_CR0_SCR_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR1 register. +// +//***************************************************************************** +#define SSI_CR1_EOM 0x00000800 // Stop Frame (End of Message) +#define SSI_CR1_FSSHLDFRM 0x00000400 // FSS Hold Frame +#define SSI_CR1_HSCLKEN 0x00000200 // High Speed Clock Enable +#define SSI_CR1_DIR 0x00000100 // SSI Direction of Operation +#define SSI_CR1_MODE_M 0x000000C0 // SSI Mode +#define SSI_CR1_MODE_LEGACY 0x00000000 // Legacy SSI mode +#define SSI_CR1_MODE_BI 0x00000040 // Bi-SSI mode +#define SSI_CR1_MODE_QUAD 0x00000080 // Quad-SSI Mode +#define SSI_CR1_MODE_ADVANCED 0x000000C0 // Advanced SSI Mode with 8-bit + // packet size +#define SSI_CR1_EOT 0x00000010 // End of Transmission +#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select +#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port + // Enable +#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DR register. +// +//***************************************************************************** +#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_SR register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI Busy Bit +#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full +#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty +#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full +#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CPSR register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_IM register. +// +//***************************************************************************** +#define SSI_IM_EOTIM 0x00000040 // End of Transmit Interrupt Mask +#define SSI_IM_DMATXIM 0x00000020 // SSI Transmit DMA Interrupt Mask +#define SSI_IM_DMARXIM 0x00000010 // SSI Receive DMA Interrupt Mask +#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask +#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask +#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt + // Mask +#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_RIS register. +// +//***************************************************************************** +#define SSI_RIS_EOTRIS 0x00000040 // End of Transmit Raw Interrupt + // Status +#define SSI_RIS_DMATXRIS 0x00000020 // SSI Transmit DMA Raw Interrupt + // Status +#define SSI_RIS_DMARXRIS 0x00000010 // SSI Receive DMA Raw Interrupt + // Status +#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt + // Status +#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt + // Status +#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw + // Interrupt Status +#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_MIS register. +// +//***************************************************************************** +#define SSI_MIS_EOTMIS 0x00000040 // End of Transmit Masked Interrupt + // Status +#define SSI_MIS_DMATXMIS 0x00000020 // SSI Transmit DMA Masked + // Interrupt Status +#define SSI_MIS_DMARXMIS 0x00000010 // SSI Receive DMA Masked Interrupt + // Status +#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked + // Interrupt Status +#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked + // Interrupt Status +#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked + // Interrupt Status +#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_ICR register. +// +//***************************************************************************** +#define SSI_ICR_EOTIC 0x00000040 // End of Transmit Interrupt Clear +#define SSI_ICR_DMATXIC 0x00000020 // SSI Transmit DMA Interrupt Clear +#define SSI_ICR_DMARXIC 0x00000010 // SSI Receive DMA Interrupt Clear +#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt + // Clear +#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DMACTL register. +// +//***************************************************************************** +#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_PP register. +// +//***************************************************************************** +#define SSI_PP_FSSHLDFRM 0x00000008 // FSS Hold Frame Capability +#define SSI_PP_MODE_M 0x00000006 // Mode of Operation +#define SSI_PP_MODE_LEGACY 0x00000000 // Legacy SSI mode +#define SSI_PP_MODE_ADVBI 0x00000002 // Legacy mode, Advanced SSI mode + // and Bi-SSI mode enabled +#define SSI_PP_MODE_ADVBIQUAD 0x00000004 // Legacy mode, Advanced mode, + // Bi-SSI and Quad-SSI mode enabled +#define SSI_PP_HSCLK 0x00000001 // High Speed Capability + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CC register. +// +//***************************************************************************** +#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source +#define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock + // source and divisor factor) +#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC + +#endif // __HW_SSI_H__ diff --git a/os/common/ext/TivaWare/inc/hw_sysctl.h b/os/common/ext/TivaWare/inc/hw_sysctl.h new file mode 100644 index 0000000..6f78204 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_sysctl.h @@ -0,0 +1,3749 @@ +//***************************************************************************** +// +// hw_sysctl.h - Macros used when accessing the system control hardware. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + +//***************************************************************************** +// +// The following are defines for the System Control register addresses. +// +//***************************************************************************** +#define SYSCTL_DID0 0x400FE000 // Device Identification 0 +#define SYSCTL_DID1 0x400FE004 // Device Identification 1 +#define SYSCTL_DC0 0x400FE008 // Device Capabilities 0 +#define SYSCTL_DC1 0x400FE010 // Device Capabilities 1 +#define SYSCTL_DC2 0x400FE014 // Device Capabilities 2 +#define SYSCTL_DC3 0x400FE018 // Device Capabilities 3 +#define SYSCTL_DC4 0x400FE01C // Device Capabilities 4 +#define SYSCTL_DC5 0x400FE020 // Device Capabilities 5 +#define SYSCTL_DC6 0x400FE024 // Device Capabilities 6 +#define SYSCTL_DC7 0x400FE028 // Device Capabilities 7 +#define SYSCTL_DC8 0x400FE02C // Device Capabilities 8 +#define SYSCTL_PBORCTL 0x400FE030 // Brown-Out Reset Control +#define SYSCTL_PTBOCTL 0x400FE038 // Power-Temp Brown Out Control +#define SYSCTL_SRCR0 0x400FE040 // Software Reset Control 0 +#define SYSCTL_SRCR1 0x400FE044 // Software Reset Control 1 +#define SYSCTL_SRCR2 0x400FE048 // Software Reset Control 2 +#define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status +#define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control +#define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and + // Clear +#define SYSCTL_RESC 0x400FE05C // Reset Cause +#define SYSCTL_PWRTC 0x400FE060 // Power-Temperature Cause +#define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration +#define SYSCTL_NMIC 0x400FE064 // NMI Cause Register +#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus + // Control +#define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2 +#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control +#define SYSCTL_RSCLKCFG 0x400FE0B0 // Run and Sleep Mode Configuration + // Register +#define SYSCTL_MEMTIM0 0x400FE0C0 // Memory Timing Parameter Register + // 0 for Main Flash and EEPROM +#define SYSCTL_RCGC0 0x400FE100 // Run Mode Clock Gating Control + // Register 0 +#define SYSCTL_RCGC1 0x400FE104 // Run Mode Clock Gating Control + // Register 1 +#define SYSCTL_RCGC2 0x400FE108 // Run Mode Clock Gating Control + // Register 2 +#define SYSCTL_SCGC0 0x400FE110 // Sleep Mode Clock Gating Control + // Register 0 +#define SYSCTL_SCGC1 0x400FE114 // Sleep Mode Clock Gating Control + // Register 1 +#define SYSCTL_SCGC2 0x400FE118 // Sleep Mode Clock Gating Control + // Register 2 +#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep Mode Clock Gating + // Control Register 0 +#define SYSCTL_DCGC1 0x400FE124 // Deep-Sleep Mode Clock Gating + // Control Register 1 +#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating + // Control Register 2 +#define SYSCTL_ALTCLKCFG 0x400FE138 // Alternate Clock Configuration +#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration +#define SYSCTL_DSCLKCFG 0x400FE144 // Deep Sleep Clock Configuration + // Register +#define SYSCTL_DIVSCLK 0x400FE148 // Divisor and Source Clock + // Configuration +#define SYSCTL_SYSPROP 0x400FE14C // System Properties +#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator + // Calibration +#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator + // Statistics +#define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0 +#define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1 +#define SYSCTL_PLLSTAT 0x400FE168 // PLL Status +#define SYSCTL_SLPPWRCFG 0x400FE188 // Sleep Power Configuration +#define SYSCTL_DSLPPWRCFG 0x400FE18C // Deep-Sleep Power Configuration +#define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 +#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information +#define SYSCTL_LDOSPCTL 0x400FE1B4 // LDO Sleep Power Control +#define SYSCTL_LDODPCTL 0x400FE1BC // LDO Deep-Sleep Power Control +#define SYSCTL_RESBEHAVCTL 0x400FE1D8 // Reset Behavior Control Register +#define SYSCTL_HSSR 0x400FE1F4 // Hardware System Service Request +#define SYSCTL_USBPDS 0x400FE280 // USB Power Domain Status +#define SYSCTL_USBMPC 0x400FE284 // USB Memory Power Control +#define SYSCTL_EMACPDS 0x400FE288 // Ethernet MAC Power Domain Status +#define SYSCTL_EMACMPC 0x400FE28C // Ethernet MAC Memory Power + // Control +#define SYSCTL_LCDMPC 0x400FE294 // LCD Memory Power Control +#define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral + // Present +#define SYSCTL_PPTIMER 0x400FE304 // 16/32-Bit General-Purpose Timer + // Peripheral Present +#define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output + // Peripheral Present +#define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access + // Peripheral Present +#define SYSCTL_PPEPI 0x400FE310 // EPI Peripheral Present +#define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present +#define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous + // Receiver/Transmitter Peripheral + // Present +#define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface + // Peripheral Present +#define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit + // Peripheral Present +#define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral + // Present +#define SYSCTL_PPEPHY 0x400FE330 // Ethernet PHY Peripheral Present +#define SYSCTL_PPCAN 0x400FE334 // Controller Area Network + // Peripheral Present +#define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter + // Peripheral Present +#define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral + // Present +#define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral + // Present +#define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface + // Peripheral Present +#define SYSCTL_PPLPC 0x400FE348 // Low Pin Count Interface + // Peripheral Present +#define SYSCTL_PPPECI 0x400FE350 // Platform Environment Control + // Interface Peripheral Present +#define SYSCTL_PPFAN 0x400FE354 // Fan Control Peripheral Present +#define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present +#define SYSCTL_PPWTIMER 0x400FE35C // 32/64-Bit Wide General-Purpose + // Timer Peripheral Present +#define SYSCTL_PPRTS 0x400FE370 // Remote Temperature Sensor + // Peripheral Present +#define SYSCTL_PPCCM 0x400FE374 // CRC and Cryptographic Modules + // Peripheral Present +#define SYSCTL_PPLCD 0x400FE390 // LCD Peripheral Present +#define SYSCTL_PPOWIRE 0x400FE398 // 1-Wire Peripheral Present +#define SYSCTL_PPEMAC 0x400FE39C // Ethernet MAC Peripheral Present +#define SYSCTL_PPHIM 0x400FE3A4 // Human Interface Master + // Peripheral Present +#define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset +#define SYSCTL_SRTIMER 0x400FE504 // 16/32-Bit General-Purpose Timer + // Software Reset +#define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output + // Software Reset +#define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access + // Software Reset +#define SYSCTL_SREPI 0x400FE510 // EPI Software Reset +#define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset +#define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous + // Receiver/Transmitter Software + // Reset +#define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface + // Software Reset +#define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit + // Software Reset +#define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software + // Reset +#define SYSCTL_SREPHY 0x400FE530 // Ethernet PHY Software Reset +#define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software + // Reset +#define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter + // Software Reset +#define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset +#define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software + // Reset +#define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface + // Software Reset +#define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset +#define SYSCTL_SRWTIMER 0x400FE55C // 32/64-Bit Wide General-Purpose + // Timer Software Reset +#define SYSCTL_SRCCM 0x400FE574 // CRC and Cryptographic Modules + // Software Reset +#define SYSCTL_SRLCD 0x400FE590 // LCD Controller Software Reset +#define SYSCTL_SROWIRE 0x400FE598 // 1-Wire Software Reset +#define SYSCTL_SREMAC 0x400FE59C // Ethernet MAC Software Reset +#define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock + // Gating Control +#define SYSCTL_RCGCTIMER 0x400FE604 // 16/32-Bit General-Purpose Timer + // Run Mode Clock Gating Control +#define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run + // Mode Clock Gating Control +#define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run + // Mode Clock Gating Control +#define SYSCTL_RCGCEPI 0x400FE610 // EPI Run Mode Clock Gating + // Control +#define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous + // Receiver/Transmitter Run Mode + // Clock Gating Control +#define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run + // Mode Clock Gating Control +#define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run + // Mode Clock Gating Control +#define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode + // Clock Gating Control +#define SYSCTL_RCGCEPHY 0x400FE630 // Ethernet PHY Run Mode Clock + // Gating Control +#define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode + // Clock Gating Control +#define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run + // Mode Clock Gating Control +#define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock + // Gating Control +#define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode + // Clock Gating Control +#define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run + // Mode Clock Gating Control +#define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER 0x400FE65C // 32/64-Bit Wide General-Purpose + // Timer Run Mode Clock Gating + // Control +#define SYSCTL_RCGCCCM 0x400FE674 // CRC and Cryptographic Modules + // Run Mode Clock Gating Control +#define SYSCTL_RCGCLCD 0x400FE690 // LCD Controller Run Mode Clock + // Gating Control +#define SYSCTL_RCGCOWIRE 0x400FE698 // 1-Wire Run Mode Clock Gating + // Control +#define SYSCTL_RCGCEMAC 0x400FE69C // Ethernet MAC Run Mode Clock + // Gating Control +#define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCTIMER 0x400FE704 // 16/32-Bit General-Purpose Timer + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCEPI 0x400FE710 // EPI Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous + // Receiver/Transmitter Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCEPHY 0x400FE730 // Ethernet PHY Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep + // Mode Clock Gating Control +#define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER 0x400FE75C // 32/64-Bit Wide General-Purpose + // Timer Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCCCM 0x400FE774 // CRC and Cryptographic Modules + // Sleep Mode Clock Gating Control +#define SYSCTL_SCGCLCD 0x400FE790 // LCD Controller Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCOWIRE 0x400FE798 // 1-Wire Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCEMAC 0x400FE79C // Ethernet MAC Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCTIMER 0x400FE804 // 16/32-Bit General-Purpose Timer + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCEPI 0x400FE810 // EPI Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous + // Receiver/Transmitter Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCEPHY 0x400FE830 // Ethernet PHY Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep + // Mode Clock Gating Control +#define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER 0x400FE85C // 32/64-Bit Wide General-Purpose + // Timer Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCCCM 0x400FE874 // CRC and Cryptographic Modules + // Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCLCD 0x400FE890 // LCD Controller Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCOWIRE 0x400FE898 // 1-Wire Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCEMAC 0x400FE89C // Ethernet MAC Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control +#define SYSCTL_PCTIMER 0x400FE904 // 16/32-Bit General-Purpose Timer + // Power Control +#define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output + // Power Control +#define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power + // Control +#define SYSCTL_PCEPI 0x400FE910 // External Peripheral Interface + // Power Control +#define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control +#define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous + // Receiver/Transmitter Power + // Control +#define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface + // Power Control +#define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power + // Control +#define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power + // Control +#define SYSCTL_PCEPHY 0x400FE930 // Ethernet PHY Power Control +#define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power + // Control +#define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter + // Power Control +#define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control +#define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power + // Control +#define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface + // Power Control +#define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control +#define SYSCTL_PCCCM 0x400FE974 // CRC and Cryptographic Modules + // Power Control +#define SYSCTL_PCLCD 0x400FE990 // LCD Controller Power Control +#define SYSCTL_PCOWIRE 0x400FE998 // 1-Wire Power Control +#define SYSCTL_PCEMAC 0x400FE99C // Ethernet MAC Power Control +#define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready +#define SYSCTL_PRTIMER 0x400FEA04 // 16/32-Bit General-Purpose Timer + // Peripheral Ready +#define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output + // Peripheral Ready +#define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access + // Peripheral Ready +#define SYSCTL_PREPI 0x400FEA10 // EPI Peripheral Ready +#define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready +#define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous + // Receiver/Transmitter Peripheral + // Ready +#define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface + // Peripheral Ready +#define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit + // Peripheral Ready +#define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral + // Ready +#define SYSCTL_PREPHY 0x400FEA30 // Ethernet PHY Peripheral Ready +#define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network + // Peripheral Ready +#define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter + // Peripheral Ready +#define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral + // Ready +#define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral + // Ready +#define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface + // Peripheral Ready +#define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready +#define SYSCTL_PRWTIMER 0x400FEA5C // 32/64-Bit Wide General-Purpose + // Timer Peripheral Ready +#define SYSCTL_PRCCM 0x400FEA74 // CRC and Cryptographic Modules + // Peripheral Ready +#define SYSCTL_PRLCD 0x400FEA90 // LCD Controller Peripheral Ready +#define SYSCTL_PROWIRE 0x400FEA98 // 1-Wire Peripheral Ready +#define SYSCTL_PREMAC 0x400FEA9C // Ethernet MAC Peripheral Ready +#define SYSCTL_UNIQUEID0 0x400FEF20 // Unique ID 0 +#define SYSCTL_UNIQUEID1 0x400FEF24 // Unique ID 1 +#define SYSCTL_UNIQUEID2 0x400FEF28 // Unique ID 2 +#define SYSCTL_UNIQUEID3 0x400FEF2C // Unique ID 3 +#define SYSCTL_CCMCGREQ 0x44030204 // Cryptographic Modules Clock + // Gating Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version +#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 + // register format. +#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class +#define SYSCTL_DID0_CLASS_TM4C123 \ + 0x00050000 // Tiva TM4C123x and TM4E123x + // microcontrollers +#define SYSCTL_DID0_CLASS_TM4C129 \ + 0x000A0000 // Tiva(TM) TM4C129-class + // microcontrollers +#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision +#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) +#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer + // revision) +#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer + // revision) +#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision +#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major + // revision update +#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change +#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version +#define SYSCTL_DID1_VER_1 0x10000000 // fury_ib +#define SYSCTL_DID1_FAM_M 0x0F000000 // Family +#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers +#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number +#define SYSCTL_DID1_PRTNO_TM4C1230C3PM \ + 0x00220000 // TM4C1230C3PM +#define SYSCTL_DID1_PRTNO_TM4C1230D5PM \ + 0x00230000 // TM4C1230D5PM +#define SYSCTL_DID1_PRTNO_TM4C1230E6PM \ + 0x00200000 // TM4C1230E6PM +#define SYSCTL_DID1_PRTNO_TM4C1230H6PM \ + 0x00210000 // TM4C1230H6PM +#define SYSCTL_DID1_PRTNO_TM4C1231C3PM \ + 0x00180000 // TM4C1231C3PM +#define SYSCTL_DID1_PRTNO_TM4C1231D5PM \ + 0x00190000 // TM4C1231D5PM +#define SYSCTL_DID1_PRTNO_TM4C1231D5PZ \ + 0x00360000 // TM4C1231D5PZ +#define SYSCTL_DID1_PRTNO_TM4C1231E6PM \ + 0x00100000 // TM4C1231E6PM +#define SYSCTL_DID1_PRTNO_TM4C1231E6PZ \ + 0x00300000 // TM4C1231E6PZ +#define SYSCTL_DID1_PRTNO_TM4C1231H6PGE \ + 0x00350000 // TM4C1231H6PGE +#define SYSCTL_DID1_PRTNO_TM4C1231H6PM \ + 0x00110000 // TM4C1231H6PM +#define SYSCTL_DID1_PRTNO_TM4C1231H6PZ \ + 0x00310000 // TM4C1231H6PZ +#define SYSCTL_DID1_PRTNO_TM4C1232C3PM \ + 0x00080000 // TM4C1232C3PM +#define SYSCTL_DID1_PRTNO_TM4C1232D5PM \ + 0x00090000 // TM4C1232D5PM +#define SYSCTL_DID1_PRTNO_TM4C1232E6PM \ + 0x000A0000 // TM4C1232E6PM +#define SYSCTL_DID1_PRTNO_TM4C1232H6PM \ + 0x000B0000 // TM4C1232H6PM +#define SYSCTL_DID1_PRTNO_TM4C1233C3PM \ + 0x00010000 // TM4C1233C3PM +#define SYSCTL_DID1_PRTNO_TM4C1233D5PM \ + 0x00020000 // TM4C1233D5PM +#define SYSCTL_DID1_PRTNO_TM4C1233D5PZ \ + 0x00D00000 // TM4C1233D5PZ +#define SYSCTL_DID1_PRTNO_TM4C1233E6PM \ + 0x00030000 // TM4C1233E6PM +#define SYSCTL_DID1_PRTNO_TM4C1233E6PZ \ + 0x00D10000 // TM4C1233E6PZ +#define SYSCTL_DID1_PRTNO_TM4C1233H6PGE \ + 0x00D60000 // TM4C1233H6PGE +#define SYSCTL_DID1_PRTNO_TM4C1233H6PM \ + 0x00040000 // TM4C1233H6PM +#define SYSCTL_DID1_PRTNO_TM4C1233H6PZ \ + 0x00D20000 // TM4C1233H6PZ +#define SYSCTL_DID1_PRTNO_TM4C1236D5PM \ + 0x00520000 // TM4C1236D5PM +#define SYSCTL_DID1_PRTNO_TM4C1236E6PM \ + 0x00500000 // TM4C1236E6PM +#define SYSCTL_DID1_PRTNO_TM4C1236H6PM \ + 0x00510000 // TM4C1236H6PM +#define SYSCTL_DID1_PRTNO_TM4C1237D5PM \ + 0x00480000 // TM4C1237D5PM +#define SYSCTL_DID1_PRTNO_TM4C1237D5PZ \ + 0x00660000 // TM4C1237D5PZ +#define SYSCTL_DID1_PRTNO_TM4C1237E6PM \ + 0x00400000 // TM4C1237E6PM +#define SYSCTL_DID1_PRTNO_TM4C1237E6PZ \ + 0x00600000 // TM4C1237E6PZ +#define SYSCTL_DID1_PRTNO_TM4C1237H6PGE \ + 0x00650000 // TM4C1237H6PGE +#define SYSCTL_DID1_PRTNO_TM4C1237H6PM \ + 0x00410000 // TM4C1237H6PM +#define SYSCTL_DID1_PRTNO_TM4C1237H6PZ \ + 0x00610000 // TM4C1237H6PZ +#define SYSCTL_DID1_PRTNO_TM4C123AE6PM \ + 0x00800000 // TM4C123AE6PM +#define SYSCTL_DID1_PRTNO_TM4C123AH6PM \ + 0x00830000 // TM4C123AH6PM +#define SYSCTL_DID1_PRTNO_TM4C123BE6PM \ + 0x00700000 // TM4C123BE6PM +#define SYSCTL_DID1_PRTNO_TM4C123BE6PZ \ + 0x00C30000 // TM4C123BE6PZ +#define SYSCTL_DID1_PRTNO_TM4C123BH6PGE \ + 0x00C60000 // TM4C123BH6PGE +#define SYSCTL_DID1_PRTNO_TM4C123BH6PM \ + 0x00730000 // TM4C123BH6PM +#define SYSCTL_DID1_PRTNO_TM4C123BH6PZ \ + 0x00C40000 // TM4C123BH6PZ +#define SYSCTL_DID1_PRTNO_TM4C123BH6ZRB \ + 0x00E90000 // TM4C123BH6ZRB +#define SYSCTL_DID1_PRTNO_TM4C123FE6PM \ + 0x00B00000 // TM4C123FE6PM +#define SYSCTL_DID1_PRTNO_TM4C123FH6PM \ + 0x00B10000 // TM4C123FH6PM +#define SYSCTL_DID1_PRTNO_TM4C123GE6PM \ + 0x00A00000 // TM4C123GE6PM +#define SYSCTL_DID1_PRTNO_TM4C123GE6PZ \ + 0x00C00000 // TM4C123GE6PZ +#define SYSCTL_DID1_PRTNO_TM4C123GH6PGE \ + 0x00C50000 // TM4C123GH6PGE +#define SYSCTL_DID1_PRTNO_TM4C123GH6PM \ + 0x00A10000 // TM4C123GH6PM +#define SYSCTL_DID1_PRTNO_TM4C123GH6PZ \ + 0x00C10000 // TM4C123GH6PZ +#define SYSCTL_DID1_PRTNO_TM4C123GH6ZRB \ + 0x00E30000 // TM4C123GH6ZRB +#define SYSCTL_DID1_PRTNO_TM4C1290NCPDT \ + 0x00190000 // TM4C1290NCPDT +#define SYSCTL_DID1_PRTNO_TM4C1290NCZAD \ + 0x001B0000 // TM4C1290NCZAD +#define SYSCTL_DID1_PRTNO_TM4C1292NCPDT \ + 0x001C0000 // TM4C1292NCPDT +#define SYSCTL_DID1_PRTNO_TM4C1292NCZAD \ + 0x001E0000 // TM4C1292NCZAD +#define SYSCTL_DID1_PRTNO_TM4C1294KCPDT \ + 0x00340000 // TM4C1294KCPDT +#define SYSCTL_DID1_PRTNO_TM4C1294NCPDT \ + 0x001F0000 // TM4C1294NCPDT +#define SYSCTL_DID1_PRTNO_TM4C1294NCZAD \ + 0x00210000 // TM4C1294NCZAD +#define SYSCTL_DID1_PRTNO_TM4C1297NCZAD \ + 0x00220000 // TM4C1297NCZAD +#define SYSCTL_DID1_PRTNO_TM4C1299KCZAD \ + 0x00360000 // TM4C1299KCZAD +#define SYSCTL_DID1_PRTNO_TM4C1299NCZAD \ + 0x00230000 // TM4C1299NCZAD +#define SYSCTL_DID1_PRTNO_TM4C129CNCPDT \ + 0x00240000 // TM4C129CNCPDT +#define SYSCTL_DID1_PRTNO_TM4C129CNCZAD \ + 0x00260000 // TM4C129CNCZAD +#define SYSCTL_DID1_PRTNO_TM4C129DNCPDT \ + 0x00270000 // TM4C129DNCPDT +#define SYSCTL_DID1_PRTNO_TM4C129DNCZAD \ + 0x00290000 // TM4C129DNCZAD +#define SYSCTL_DID1_PRTNO_TM4C129EKCPDT \ + 0x00350000 // TM4C129EKCPDT +#define SYSCTL_DID1_PRTNO_TM4C129ENCPDT \ + 0x002D0000 // TM4C129ENCPDT +#define SYSCTL_DID1_PRTNO_TM4C129ENCZAD \ + 0x002F0000 // TM4C129ENCZAD +#define SYSCTL_DID1_PRTNO_TM4C129LNCZAD \ + 0x00300000 // TM4C129LNCZAD +#define SYSCTL_DID1_PRTNO_TM4C129XKCZAD \ + 0x00370000 // TM4C129XKCZAD +#define SYSCTL_DID1_PRTNO_TM4C129XNCZAD \ + 0x00320000 // TM4C129XNCZAD +#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count +#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin LQFP package +#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin LQFP package +#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin LQFP package +#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin BGA package +#define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package +#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range +#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range +#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range +#define SYSCTL_DID1_TEMP_IE 0x00000060 // Available in both industrial + // temperature range (-40C to 85C) + // and extended temperature range + // (-40C to 105C) devices. See +#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type +#define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package +#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package +#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance +#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM +#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash +#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash +#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash +#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash +#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present +#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present +#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present +#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present +#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present +#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present +#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present +#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider +#define SYSCTL_DC1_MINSYSDIV_80 0x00002000 // Specifies an 80-MHz CPU clock + // with a PLL divider of 2.5 +#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock + // with a PLL divider of 4 +#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock + // with a PLL divider of 5 +#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a + // PLL divider of 8 +#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a + // PLL divider of 10 +#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed +#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second +#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second +#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed +#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second +#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second +#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_DC1_MPU 0x00000080 // MPU Present +#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present +#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present +#define SYSCTL_DC1_PLL 0x00000010 // PLL Present +#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present +#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present +#define SYSCTL_DC1_SWD 0x00000002 // SWD Present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present +#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present +#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present +#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present +#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed +#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present +#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed +#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present +#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present +#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present +#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present +#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present +#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present +#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present +#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available +#define SYSCTL_DC3_CCP5 0x20000000 // T2CCP1 Pin Present +#define SYSCTL_DC3_CCP4 0x10000000 // T2CCP0 Pin Present +#define SYSCTL_DC3_CCP3 0x08000000 // T1CCP1 Pin Present +#define SYSCTL_DC3_CCP2 0x04000000 // T1CCP0 Pin Present +#define SYSCTL_DC3_CCP1 0x02000000 // T0CCP1 Pin Present +#define SYSCTL_DC3_CCP0 0x01000000 // T0CCP0 Pin Present +#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present +#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present +#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present +#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present +#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present +#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present +#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable +#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate +#define SYSCTL_DC4_CCP7 0x00008000 // T3CCP1 Pin Present +#define SYSCTL_DC4_CCP6 0x00004000 // T3CCP0 Pin Present +#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present +#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present +#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present +#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present +#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present +#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC5 register. +// +//***************************************************************************** +#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present +#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present +#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present +#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present +#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active +#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active +#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present +#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present +#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC6 register. +// +//***************************************************************************** +#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present +#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present +#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only +#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host +#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC7 register. +// +//***************************************************************************** +#define SYSCTL_DC7_DMACH30 0x40000000 // DMA Channel 30 +#define SYSCTL_DC7_DMACH29 0x20000000 // DMA Channel 29 +#define SYSCTL_DC7_DMACH28 0x10000000 // DMA Channel 28 +#define SYSCTL_DC7_DMACH27 0x08000000 // DMA Channel 27 +#define SYSCTL_DC7_DMACH26 0x04000000 // DMA Channel 26 +#define SYSCTL_DC7_DMACH25 0x02000000 // DMA Channel 25 +#define SYSCTL_DC7_DMACH24 0x01000000 // DMA Channel 24 +#define SYSCTL_DC7_DMACH23 0x00800000 // DMA Channel 23 +#define SYSCTL_DC7_DMACH22 0x00400000 // DMA Channel 22 +#define SYSCTL_DC7_DMACH21 0x00200000 // DMA Channel 21 +#define SYSCTL_DC7_DMACH20 0x00100000 // DMA Channel 20 +#define SYSCTL_DC7_DMACH19 0x00080000 // DMA Channel 19 +#define SYSCTL_DC7_DMACH18 0x00040000 // DMA Channel 18 +#define SYSCTL_DC7_DMACH17 0x00020000 // DMA Channel 17 +#define SYSCTL_DC7_DMACH16 0x00010000 // DMA Channel 16 +#define SYSCTL_DC7_DMACH15 0x00008000 // DMA Channel 15 +#define SYSCTL_DC7_DMACH14 0x00004000 // DMA Channel 14 +#define SYSCTL_DC7_DMACH13 0x00002000 // DMA Channel 13 +#define SYSCTL_DC7_DMACH12 0x00001000 // DMA Channel 12 +#define SYSCTL_DC7_DMACH11 0x00000800 // DMA Channel 11 +#define SYSCTL_DC7_DMACH10 0x00000400 // DMA Channel 10 +#define SYSCTL_DC7_DMACH9 0x00000200 // DMA Channel 9 +#define SYSCTL_DC7_DMACH8 0x00000100 // DMA Channel 8 +#define SYSCTL_DC7_DMACH7 0x00000080 // DMA Channel 7 +#define SYSCTL_DC7_DMACH6 0x00000040 // DMA Channel 6 +#define SYSCTL_DC7_DMACH5 0x00000020 // DMA Channel 5 +#define SYSCTL_DC7_DMACH4 0x00000010 // DMA Channel 4 +#define SYSCTL_DC7_DMACH3 0x00000008 // DMA Channel 3 +#define SYSCTL_DC7_DMACH2 0x00000004 // DMA Channel 2 +#define SYSCTL_DC7_DMACH1 0x00000002 // DMA Channel 1 +#define SYSCTL_DC7_DMACH0 0x00000001 // DMA Channel 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC8 register. +// +//***************************************************************************** +#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present +#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present +#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present +#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present +#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present +#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present +#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present +#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present +#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present +#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present +#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present +#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present +#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present +#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present +#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present +#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present +#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present +#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present +#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present +#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present +#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present +#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present +#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present +#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present +#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR0 0x00000004 // VDD under BOR0 Event Action +#define SYSCTL_PBORCTL_BOR1 0x00000002 // VDD under BOR1 Event Action + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PTBOCTL register. +// +//***************************************************************************** +#define SYSCTL_PTBOCTL_VDDA_UBOR_M \ + 0x00000300 // VDDA under BOR Event Action +#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE \ + 0x00000000 // No Action +#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT \ + 0x00000100 // System control interrupt +#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI \ + 0x00000200 // NMI +#define SYSCTL_PTBOCTL_VDDA_UBOR_RST \ + 0x00000300 // Reset +#define SYSCTL_PTBOCTL_VDD_UBOR_M \ + 0x00000003 // VDD (VDDS) under BOR Event + // Action +#define SYSCTL_PTBOCTL_VDD_UBOR_NONE \ + 0x00000000 // No Action +#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT \ + 0x00000001 // System control interrupt +#define SYSCTL_PTBOCTL_VDD_UBOR_NMI \ + 0x00000002 // NMI +#define SYSCTL_PTBOCTL_VDD_UBOR_RST \ + 0x00000003 // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR0 register. +// +//***************************************************************************** +#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control +#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control +#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control +#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control +#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control +#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control +#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control +#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR1 register. +// +//***************************************************************************** +#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control +#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control +#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control +#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control +#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control +#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control +#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control +#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control +#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control +#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control +#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control +#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control +#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control +#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control +#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control +#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR2 register. +// +//***************************************************************************** +#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control +#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control +#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control +#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control +#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control +#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control +#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control +#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control +#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control +#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control +#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RIS register. +// +//***************************************************************************** +#define SYSCTL_RIS_BOR0RIS 0x00000800 // VDD under BOR0 Raw Interrupt + // Status +#define SYSCTL_RIS_VDDARIS 0x00000400 // VDDA Power OK Event Raw + // Interrupt Status +#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt + // Status +#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt + // Status +#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status +#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw + // Interrupt Status +#define SYSCTL_RIS_BOR1RIS 0x00000002 // VDD under BOR1 Raw Interrupt + // Status +#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_IMC register. +// +//***************************************************************************** +#define SYSCTL_IMC_BOR0IM 0x00000800 // VDD under BOR0 Interrupt Mask +#define SYSCTL_IMC_VDDAIM 0x00000400 // VDDA Power OK Interrupt Mask +#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask +#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask +#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask +#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure + // Interrupt Mask +#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask +#define SYSCTL_IMC_BOR1IM 0x00000002 // VDD under BOR1 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MISC register. +// +//***************************************************************************** +#define SYSCTL_MISC_BOR0MIS 0x00000800 // VDD under BOR0 Masked Interrupt + // Status +#define SYSCTL_MISC_VDDAMIS 0x00000400 // VDDA Power OK Masked Interrupt + // Status +#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt + // Status +#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt + // Status +#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status +#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked + // Interrupt Status +#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status +#define SYSCTL_MISC_BOR1MIS 0x00000002 // VDD under BOR1 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset +#define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset +#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset +#define SYSCTL_RESC_SW 0x00000010 // Software Reset +#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset +#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset +#define SYSCTL_RESC_EXT 0x00000001 // External Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PWRTC register. +// +//***************************************************************************** +#define SYSCTL_PWRTC_VDDA_UBOR 0x00000010 // VDDA Under BOR Status +#define SYSCTL_PWRTC_VDD_UBOR 0x00000001 // VDD Under BOR Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating +#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor +#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider +#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor +#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass +#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value +#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz +#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz +#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz +#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz +#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz +#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz +#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz +#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz +#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz (USB) +#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz (USB) +#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz (USB) +#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz (USB) +#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 +#define SYSCTL_RCC_OSCSRC_30 0x00000030 // LFIOSC +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable +#define SYSCTL_RCC_SYSDIV_S 23 +#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_NMIC register. +// +//***************************************************************************** +#define SYSCTL_NMIC_MOSCFAIL 0x00010000 // MOSC Failure NMI +#define SYSCTL_NMIC_TAMPER 0x00000200 // Tamper Event NMI +#define SYSCTL_NMIC_WDT1 0x00000020 // Watch Dog Timer (WDT) 1 NMI +#define SYSCTL_NMIC_WDT0 0x00000008 // Watch Dog Timer (WDT) 0 NMI +#define SYSCTL_NMIC_POWER 0x00000004 // Power/Brown Out Event NMI +#define SYSCTL_NMIC_EXTERNAL 0x00000001 // External Pin NMI + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL +// register. +// +//***************************************************************************** +#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance + // Bus + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC2 register. +// +//***************************************************************************** +#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 +#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200 + // MHz +#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 +#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2 +#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL +#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 +#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 +#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 +#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC +#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC +#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 +#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // LFIOSC +#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz +#define SYSCTL_RCC2_SYSDIV2_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. +// +//***************************************************************************** +#define SYSCTL_MOSCCTL_OSCRNG 0x00000010 // Oscillator Range +#define SYSCTL_MOSCCTL_PWRDN 0x00000008 // Power Down +#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected +#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action +#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RSCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000 // Memory Timing Register Update +#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000 // New PLLFREQ Accept +#define SYSCTL_RSCLKCFG_ACG 0x20000000 // Auto Clock Gating +#define SYSCTL_RSCLKCFG_USEPLL 0x10000000 // Use PLL +#define SYSCTL_RSCLKCFG_PLLSRC_M \ + 0x0F000000 // PLL Source +#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC \ + 0x00000000 // PIOSC is PLL input clock source +#define SYSCTL_RSCLKCFG_PLLSRC_MOSC \ + 0x03000000 // MOSC is the PLL input clock + // source +#define SYSCTL_RSCLKCFG_OSCSRC_M \ + 0x00F00000 // Oscillator Source +#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC \ + 0x00000000 // PIOSC is oscillator source +#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC \ + 0x00200000 // LFIOSC is oscillator source +#define SYSCTL_RSCLKCFG_OSCSRC_MOSC \ + 0x00300000 // MOSC is oscillator source +#define SYSCTL_RSCLKCFG_OSCSRC_RTC \ + 0x00400000 // Hibernation Module RTC + // Oscillator (RTCOSC) +#define SYSCTL_RSCLKCFG_OSYSDIV_M \ + 0x000FFC00 // Oscillator System Clock Divisor +#define SYSCTL_RSCLKCFG_PSYSDIV_M \ + 0x000003FF // PLL System Clock Divisor +#define SYSCTL_RSCLKCFG_OSYSDIV_S \ + 10 +#define SYSCTL_RSCLKCFG_PSYSDIV_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register. +// +//***************************************************************************** +#define SYSCTL_MEMTIM0_EBCHT_M 0x03C00000 // EEPROM Clock High Time +#define SYSCTL_MEMTIM0_EBCHT_0_5 \ + 0x00000000 // 1/2 system clock period +#define SYSCTL_MEMTIM0_EBCHT_1 0x00400000 // 1 system clock period +#define SYSCTL_MEMTIM0_EBCHT_1_5 \ + 0x00800000 // 1.5 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_2 0x00C00000 // 2 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_2_5 \ + 0x01000000 // 2.5 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_3 0x01400000 // 3 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_3_5 \ + 0x01800000 // 3.5 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_4 0x01C00000 // 4 system clock periods +#define SYSCTL_MEMTIM0_EBCHT_4_5 \ + 0x02000000 // 4.5 system clock periods +#define SYSCTL_MEMTIM0_EBCE 0x00200000 // EEPROM Bank Clock Edge +#define SYSCTL_MEMTIM0_MB1 0x00100010 // Must be one +#define SYSCTL_MEMTIM0_EWS_M 0x000F0000 // EEPROM Wait States +#define SYSCTL_MEMTIM0_FBCHT_M 0x000003C0 // Flash Bank Clock High Time +#define SYSCTL_MEMTIM0_FBCHT_0_5 \ + 0x00000000 // 1/2 system clock period +#define SYSCTL_MEMTIM0_FBCHT_1 0x00000040 // 1 system clock period +#define SYSCTL_MEMTIM0_FBCHT_1_5 \ + 0x00000080 // 1.5 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_2 0x000000C0 // 2 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_2_5 \ + 0x00000100 // 2.5 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_3 0x00000140 // 3 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_3_5 \ + 0x00000180 // 3.5 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_4 0x000001C0 // 4 system clock periods +#define SYSCTL_MEMTIM0_FBCHT_4_5 \ + 0x00000200 // 4.5 system clock periods +#define SYSCTL_MEMTIM0_FBCE 0x00000020 // Flash Bank Clock Edge +#define SYSCTL_MEMTIM0_FWS_M 0x0000000F // Flash Wait State +#define SYSCTL_MEMTIM0_EWS_S 16 +#define SYSCTL_MEMTIM0_FWS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC0 register. +// +//***************************************************************************** +#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed +#define SYSCTL_RCGC0_ADC1SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC1SPD_250K \ + 0x00000400 // 250K samples/second +#define SYSCTL_RCGC0_ADC1SPD_500K \ + 0x00000800 // 500K samples/second +#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed +#define SYSCTL_RCGC0_ADC0SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC0SPD_250K \ + 0x00000100 // 250K samples/second +#define SYSCTL_RCGC0_ADC0SPD_500K \ + 0x00000200 // 500K samples/second +#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC1 register. +// +//***************************************************************************** +#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC2 register. +// +//***************************************************************************** +#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC0 register. +// +//***************************************************************************** +#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed +#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC1 register. +// +//***************************************************************************** +#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC2 register. +// +//***************************************************************************** +#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC0 register. +// +//***************************************************************************** +#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC1 register. +// +//***************************************************************************** +#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating +#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC2 register. +// +//***************************************************************************** +#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control +#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control +#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control +#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_ALTCLKCFG_ALTCLK_M \ + 0x0000000F // Alternate Clock Source +#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC \ + 0x00000000 // PIOSC +#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC \ + 0x00000003 // Hibernation Module Real-time + // clock output (RTCOSC) +#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC \ + 0x00000004 // Low-frequency internal + // oscillator (LFIOSC) + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override +#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source +#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC +#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC +#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // LFIOSC +#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz +#define SYSCTL_DSLPCLKCFG_PIOSCPD \ + 0x00000002 // PIOSC Power Down Request +#define SYSCTL_DSLPCLKCFG_D_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000 // PIOSC Power Down +#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000 // MOSC Disable Power Down +#define SYSCTL_DSCLKCFG_DSOSCSRC_M \ + 0x00F00000 // Deep Sleep Oscillator Source +#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC \ + 0x00000000 // PIOSC +#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC \ + 0x00200000 // LFIOSC +#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC \ + 0x00300000 // MOSC +#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC \ + 0x00400000 // Hibernation Module RTCOSC +#define SYSCTL_DSCLKCFG_DSSYSDIV_M \ + 0x000003FF // Deep Sleep Clock Divisor +#define SYSCTL_DSCLKCFG_DSSYSDIV_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DIVSCLK register. +// +//***************************************************************************** +#define SYSCTL_DIVSCLK_EN 0x80000000 // DIVSCLK Enable +#define SYSCTL_DIVSCLK_SRC_M 0x00030000 // Clock Source +#define SYSCTL_DIVSCLK_SRC_SYSCLK \ + 0x00000000 // System Clock +#define SYSCTL_DIVSCLK_SRC_PIOSC \ + 0x00010000 // PIOSC +#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000 // MOSC +#define SYSCTL_DIVSCLK_DIV_M 0x000000FF // Divisor Value +#define SYSCTL_DIVSCLK_DIV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SYSPROP register. +// +//***************************************************************************** +#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCCAL +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value +#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration +#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim +#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value +#define SYSCTL_PIOSCCAL_UT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value +#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result +#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been + // attempted +#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation + // completed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation + // failed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value +#define SYSCTL_PIOSCSTAT_DT_S 16 +#define SYSCTL_PIOSCSTAT_CT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ0_PLLPWR 0x00800000 // PLL Power +#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value +#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value +#define SYSCTL_PLLFREQ0_MFRAC_S 10 +#define SYSCTL_PLLFREQ0_MINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value +#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value +#define SYSCTL_PLLFREQ1_Q_S 8 +#define SYSCTL_PLLFREQ1_N_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. +// +//***************************************************************************** +#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG +// register. +// +//***************************************************************************** +#define SYSCTL_SLPPWRCFG_FLASHPM_M \ + 0x00000030 // Flash Power Modes +#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \ + 0x00000020 // Low Power Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_M \ + 0x00000003 // SRAM Power Modes +#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \ + 0x00000001 // Standby Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_LP \ + 0x00000003 // Low Power Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200 // LDO Sleep Mode +#define SYSCTL_DSLPPWRCFG_TSPD 0x00000100 // Temperature Sense Power Down +#define SYSCTL_DSLPPWRCFG_FLASHPM_M \ + 0x00000030 // Flash Power Modes +#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \ + 0x00000020 // Low Power Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_M \ + 0x00000003 // SRAM Power Modes +#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \ + 0x00000001 // Standby Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \ + 0x00000003 // Low Power Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC9 register. +// +//***************************************************************************** +#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present +#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present +#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present +#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present +#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present +#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present +#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present +#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present +#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present +#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present +#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present +#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present +#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present +#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present +#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present +#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. +// +//***************************************************************************** +#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer + // Available + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOSPCTL +// register. +// +//***************************************************************************** +#define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable +#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage +#define SYSCTL_LDOSPCTL_VLDO_0_90V \ + 0x00000012 // 0.90 V +#define SYSCTL_LDOSPCTL_VLDO_0_95V \ + 0x00000013 // 0.95 V +#define SYSCTL_LDOSPCTL_VLDO_1_00V \ + 0x00000014 // 1.00 V +#define SYSCTL_LDOSPCTL_VLDO_1_05V \ + 0x00000015 // 1.05 V +#define SYSCTL_LDOSPCTL_VLDO_1_10V \ + 0x00000016 // 1.10 V +#define SYSCTL_LDOSPCTL_VLDO_1_15V \ + 0x00000017 // 1.15 V +#define SYSCTL_LDOSPCTL_VLDO_1_20V \ + 0x00000018 // 1.20 V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDODPCTL +// register. +// +//***************************************************************************** +#define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable +#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage +#define SYSCTL_LDODPCTL_VLDO_0_90V \ + 0x00000012 // 0.90 V +#define SYSCTL_LDODPCTL_VLDO_0_95V \ + 0x00000013 // 0.95 V +#define SYSCTL_LDODPCTL_VLDO_1_00V \ + 0x00000014 // 1.00 V +#define SYSCTL_LDODPCTL_VLDO_1_05V \ + 0x00000015 // 1.05 V +#define SYSCTL_LDODPCTL_VLDO_1_10V \ + 0x00000016 // 1.10 V +#define SYSCTL_LDODPCTL_VLDO_1_15V \ + 0x00000017 // 1.15 V +#define SYSCTL_LDODPCTL_VLDO_1_20V \ + 0x00000018 // 1.20 V +#define SYSCTL_LDODPCTL_VLDO_1_25V \ + 0x00000019 // 1.25 V +#define SYSCTL_LDODPCTL_VLDO_1_30V \ + 0x0000001A // 1.30 V +#define SYSCTL_LDODPCTL_VLDO_1_35V \ + 0x0000001B // 1.35 V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL +// register. +// +//***************************************************************************** +#define SYSCTL_RESBEHAVCTL_WDOG1_M \ + 0x000000C0 // Watchdog 1 Reset Operation +#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST \ + 0x00000080 // Watchdog 1 issues a system + // reset. The application starts + // within 10 us +#define SYSCTL_RESBEHAVCTL_WDOG1_POR \ + 0x000000C0 // Watchdog 1 issues a simulated + // POR sequence. Application starts + // less than 500 us after + // deassertion (Default) +#define SYSCTL_RESBEHAVCTL_WDOG0_M \ + 0x00000030 // Watchdog 0 Reset Operation +#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST \ + 0x00000020 // Watchdog 0 issues a system + // reset. The application starts + // within 10 us +#define SYSCTL_RESBEHAVCTL_WDOG0_POR \ + 0x00000030 // Watchdog 0 issues a simulated + // POR sequence. Application starts + // less than 500 us after + // deassertion (Default) +#define SYSCTL_RESBEHAVCTL_BOR_M \ + 0x0000000C // BOR Reset operation +#define SYSCTL_RESBEHAVCTL_BOR_SYSRST \ + 0x00000008 // Brown Out Reset issues system + // reset. The application starts + // within 10 us +#define SYSCTL_RESBEHAVCTL_BOR_POR \ + 0x0000000C // Brown Out Reset issues a + // simulated POR sequence. The + // application starts less than 500 + // us after deassertion (Default) +#define SYSCTL_RESBEHAVCTL_EXTRES_M \ + 0x00000003 // External RST Pin Operation +#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST \ + 0x00000002 // External RST assertion issues a + // system reset. The application + // starts within 10 us +#define SYSCTL_RESBEHAVCTL_EXTRES_POR \ + 0x00000003 // External RST assertion issues a + // simulated POR sequence. + // Application starts less than 500 + // us after deassertion (Default) + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_HSSR register. +// +//***************************************************************************** +#define SYSCTL_HSSR_KEY_M 0xFF000000 // Write Key +#define SYSCTL_HSSR_CDOFF_M 0x00FFFFFF // Command Descriptor Pointer +#define SYSCTL_HSSR_KEY_S 24 +#define SYSCTL_HSSR_CDOFF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_USBPDS register. +// +//***************************************************************************** +#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C // Memory Array Power Status +#define SYSCTL_USBPDS_MEMSTAT_OFF \ + 0x00000000 // Array OFF +#define SYSCTL_USBPDS_MEMSTAT_RETAIN \ + 0x00000004 // SRAM Retention +#define SYSCTL_USBPDS_MEMSTAT_ON \ + 0x0000000C // Array On +#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003 // Power Domain Status +#define SYSCTL_USBPDS_PWRSTAT_OFF \ + 0x00000000 // OFF +#define SYSCTL_USBPDS_PWRSTAT_ON \ + 0x00000003 // ON + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_USBMPC register. +// +//***************************************************************************** +#define SYSCTL_USBMPC_PWRCTL_M 0x00000003 // Memory Array Power Control +#define SYSCTL_USBMPC_PWRCTL_OFF \ + 0x00000000 // Array OFF +#define SYSCTL_USBMPC_PWRCTL_RETAIN \ + 0x00000001 // SRAM Retention +#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003 // Array On + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_EMACPDS register. +// +//***************************************************************************** +#define SYSCTL_EMACPDS_MEMSTAT_M \ + 0x0000000C // Memory Array Power Status +#define SYSCTL_EMACPDS_MEMSTAT_OFF \ + 0x00000000 // Array OFF +#define SYSCTL_EMACPDS_MEMSTAT_ON \ + 0x0000000C // Array On +#define SYSCTL_EMACPDS_PWRSTAT_M \ + 0x00000003 // Power Domain Status +#define SYSCTL_EMACPDS_PWRSTAT_OFF \ + 0x00000000 // OFF +#define SYSCTL_EMACPDS_PWRSTAT_ON \ + 0x00000003 // ON + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_EMACMPC register. +// +//***************************************************************************** +#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003 // Memory Array Power Control +#define SYSCTL_EMACMPC_PWRCTL_OFF \ + 0x00000000 // Array OFF +#define SYSCTL_EMACMPC_PWRCTL_ON \ + 0x00000003 // Array On + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LCDMPC register. +// +//***************************************************************************** +#define SYSCTL_LCDMPC_PWRCTL_M 0x00000003 // Memory Array Power Control +#define SYSCTL_LCDMPC_PWRCTL_OFF \ + 0x00000000 // Array OFF +#define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003 // Array On + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWD register. +// +//***************************************************************************** +#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present +#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPTIMER register. +// +//***************************************************************************** +#define SYSCTL_PPTIMER_P7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Present +#define SYSCTL_PPTIMER_P6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Present +#define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Present +#define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Present +#define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Present +#define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Present +#define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Present +#define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPGPIO register. +// +//***************************************************************************** +#define SYSCTL_PPGPIO_P17 0x00020000 // GPIO Port T Present +#define SYSCTL_PPGPIO_P16 0x00010000 // GPIO Port S Present +#define SYSCTL_PPGPIO_P15 0x00008000 // GPIO Port R Present +#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present +#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present +#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present +#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present +#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present +#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present +#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present +#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present +#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present +#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present +#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present +#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present +#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present +#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present +#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPDMA register. +// +//***************************************************************************** +#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEPI register. +// +//***************************************************************************** +#define SYSCTL_PPEPI_P0 0x00000001 // EPI Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPHIB register. +// +//***************************************************************************** +#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUART register. +// +//***************************************************************************** +#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present +#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present +#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present +#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present +#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present +#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present +#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present +#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPSSI register. +// +//***************************************************************************** +#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present +#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present +#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present +#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPI2C register. +// +//***************************************************************************** +#define SYSCTL_PPI2C_P9 0x00000200 // I2C Module 9 Present +#define SYSCTL_PPI2C_P8 0x00000100 // I2C Module 8 Present +#define SYSCTL_PPI2C_P7 0x00000080 // I2C Module 7 Present +#define SYSCTL_PPI2C_P6 0x00000040 // I2C Module 6 Present +#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present +#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present +#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present +#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present +#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present +#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUSB register. +// +//***************************************************************************** +#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEPHY register. +// +//***************************************************************************** +#define SYSCTL_PPEPHY_P0 0x00000001 // Ethernet PHY Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPCAN register. +// +//***************************************************************************** +#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present +#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPADC register. +// +//***************************************************************************** +#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present +#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPACMP register. +// +//***************************************************************************** +#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPWM register. +// +//***************************************************************************** +#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present +#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPQEI register. +// +//***************************************************************************** +#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present +#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPLPC register. +// +//***************************************************************************** +#define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPECI register. +// +//***************************************************************************** +#define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPFAN register. +// +//***************************************************************************** +#define SYSCTL_PPFAN_P0 0x00000001 // FAN Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PPWTIMER_P5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Present +#define SYSCTL_PPWTIMER_P4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Present +#define SYSCTL_PPWTIMER_P3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Present +#define SYSCTL_PPWTIMER_P2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Present +#define SYSCTL_PPWTIMER_P1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Present +#define SYSCTL_PPWTIMER_P0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPRTS register. +// +//***************************************************************************** +#define SYSCTL_PPRTS_P0 0x00000001 // RTS Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPCCM register. +// +//***************************************************************************** +#define SYSCTL_PPCCM_P0 0x00000001 // CRC and Cryptographic Modules + // Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPLCD register. +// +//***************************************************************************** +#define SYSCTL_PPLCD_P0 0x00000001 // LCD Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPOWIRE register. +// +//***************************************************************************** +#define SYSCTL_PPOWIRE_P0 0x00000001 // 1-Wire Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEMAC register. +// +//***************************************************************************** +#define SYSCTL_PPEMAC_P0 0x00000001 // Ethernet Controller Module + // Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPHIM register. +// +//***************************************************************************** +#define SYSCTL_PPHIM_P0 0x00000001 // HIM Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWD register. +// +//***************************************************************************** +#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset +#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRTIMER register. +// +//***************************************************************************** +#define SYSCTL_SRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Software Reset +#define SYSCTL_SRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Software Reset +#define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Software Reset +#define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Software Reset +#define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Software Reset +#define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Software Reset +#define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Software Reset +#define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRGPIO register. +// +//***************************************************************************** +#define SYSCTL_SRGPIO_R17 0x00020000 // GPIO Port T Software Reset +#define SYSCTL_SRGPIO_R16 0x00010000 // GPIO Port S Software Reset +#define SYSCTL_SRGPIO_R15 0x00008000 // GPIO Port R Software Reset +#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset +#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset +#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset +#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset +#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset +#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset +#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset +#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset +#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset +#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset +#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset +#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset +#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset +#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset +#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRDMA register. +// +//***************************************************************************** +#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREPI register. +// +//***************************************************************************** +#define SYSCTL_SREPI_R0 0x00000001 // EPI Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRHIB register. +// +//***************************************************************************** +#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software + // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUART register. +// +//***************************************************************************** +#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset +#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset +#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset +#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset +#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset +#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset +#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset +#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRSSI register. +// +//***************************************************************************** +#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset +#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset +#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset +#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRI2C register. +// +//***************************************************************************** +#define SYSCTL_SRI2C_R9 0x00000200 // I2C Module 9 Software Reset +#define SYSCTL_SRI2C_R8 0x00000100 // I2C Module 8 Software Reset +#define SYSCTL_SRI2C_R7 0x00000080 // I2C Module 7 Software Reset +#define SYSCTL_SRI2C_R6 0x00000040 // I2C Module 6 Software Reset +#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset +#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset +#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset +#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset +#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset +#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUSB register. +// +//***************************************************************************** +#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREPHY register. +// +//***************************************************************************** +#define SYSCTL_SREPHY_R0 0x00000001 // Ethernet PHY Module Software + // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCAN register. +// +//***************************************************************************** +#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset +#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRADC register. +// +//***************************************************************************** +#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset +#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRACMP register. +// +//***************************************************************************** +#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRPWM register. +// +//***************************************************************************** +#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset +#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRQEI register. +// +//***************************************************************************** +#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset +#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Software Reset +#define SYSCTL_SRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Software Reset +#define SYSCTL_SRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Software Reset +#define SYSCTL_SRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Software Reset +#define SYSCTL_SRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Software Reset +#define SYSCTL_SRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCCM register. +// +//***************************************************************************** +#define SYSCTL_SRCCM_R0 0x00000001 // CRC and Cryptographic Modules + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRLCD register. +// +//***************************************************************************** +#define SYSCTL_SRLCD_R0 0x00000001 // LCD Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SROWIRE register. +// +//***************************************************************************** +#define SYSCTL_SROWIRE_R0 0x00000001 // 1-Wire Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREMAC register. +// +//***************************************************************************** +#define SYSCTL_SREMAC_R0 0x00000001 // Ethernet Controller MAC Module 0 + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWD register. +// +//***************************************************************************** +#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Run Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCGPIO_R17 0x00020000 // GPIO Port T Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R16 0x00010000 // GPIO Port S Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R15 0x00008000 // GPIO Port R Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEPI register. +// +//***************************************************************************** +#define SYSCTL_RCGCEPI_R0 0x00000001 // EPI Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_RCGCI2C_R9 0x00000200 // I2C Module 9 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R8 0x00000100 // I2C Module 8 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R7 0x00000080 // I2C Module 7 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R6 0x00000040 // I2C Module 6 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEPHY +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEPHY_R0 0x00000001 // Ethernet PHY Module Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCADC register. +// +//***************************************************************************** +#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCCCM register. +// +//***************************************************************************** +#define SYSCTL_RCGCCCM_R0 0x00000001 // CRC and Cryptographic Modules + // Run Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCLCD register. +// +//***************************************************************************** +#define SYSCTL_RCGCLCD_R0 0x00000001 // LCD Controller Module 0 Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCOWIRE +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCOWIRE_R0 0x00000001 // 1-Wire Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEMAC +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEMAC_R0 0x00000001 // Ethernet MAC Module 0 Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWD register. +// +//***************************************************************************** +#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCTIMER_S7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCGPIO_S17 0x00020000 // GPIO Port T Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S16 0x00010000 // GPIO Port S Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S15 0x00008000 // GPIO Port R Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEPI register. +// +//***************************************************************************** +#define SYSCTL_SCGCEPI_S0 0x00000001 // EPI Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_SCGCI2C_S9 0x00000200 // I2C Module 9 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S8 0x00000100 // I2C Module 8 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S7 0x00000080 // I2C Module 7 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S6 0x00000040 // I2C Module 6 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEPHY +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEPHY_S0 0x00000001 // PHY Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCADC register. +// +//***************************************************************************** +#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCWTIMER_S5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCCCM register. +// +//***************************************************************************** +#define SYSCTL_SCGCCCM_S0 0x00000001 // CRC and Cryptographic Modules + // Sleep Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCLCD register. +// +//***************************************************************************** +#define SYSCTL_SCGCLCD_S0 0x00000001 // LCD Controller Module 0 Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCOWIRE +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCOWIRE_S0 0x00000001 // 1-Wire Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEMAC +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEMAC_S0 0x00000001 // Ethernet MAC Module 0 Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWD register. +// +//***************************************************************************** +#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCTIMER_D7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCGPIO_D17 0x00020000 // GPIO Port T Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D16 0x00010000 // GPIO Port S Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D15 0x00008000 // GPIO Port R Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEPI register. +// +//***************************************************************************** +#define SYSCTL_DCGCEPI_D0 0x00000001 // EPI Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_DCGCI2C_D9 0x00000200 // I2C Module 9 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D8 0x00000100 // I2C Module 8 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D7 0x00000080 // I2C Module 7 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D6 0x00000040 // I2C Module 6 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEPHY +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEPHY_D0 0x00000001 // PHY Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCADC register. +// +//***************************************************************************** +#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCWTIMER_D5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCCCM register. +// +//***************************************************************************** +#define SYSCTL_DCGCCCM_D0 0x00000001 // CRC and Cryptographic Modules + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCLCD register. +// +//***************************************************************************** +#define SYSCTL_DCGCLCD_D0 0x00000001 // LCD Controller Module 0 + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCOWIRE +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCOWIRE_D0 0x00000001 // 1-Wire Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEMAC +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEMAC_D0 0x00000001 // Ethernet MAC Module 0 Deep-Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCWD register. +// +//***************************************************************************** +#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control +#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCTIMER register. +// +//***************************************************************************** +#define SYSCTL_PCTIMER_P7 0x00000080 // General-Purpose Timer 7 Power + // Control +#define SYSCTL_PCTIMER_P6 0x00000040 // General-Purpose Timer 6 Power + // Control +#define SYSCTL_PCTIMER_P5 0x00000020 // General-Purpose Timer 5 Power + // Control +#define SYSCTL_PCTIMER_P4 0x00000010 // General-Purpose Timer 4 Power + // Control +#define SYSCTL_PCTIMER_P3 0x00000008 // General-Purpose Timer 3 Power + // Control +#define SYSCTL_PCTIMER_P2 0x00000004 // General-Purpose Timer 2 Power + // Control +#define SYSCTL_PCTIMER_P1 0x00000002 // General-Purpose Timer 1 Power + // Control +#define SYSCTL_PCTIMER_P0 0x00000001 // General-Purpose Timer 0 Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCGPIO register. +// +//***************************************************************************** +#define SYSCTL_PCGPIO_P17 0x00020000 // GPIO Port T Power Control +#define SYSCTL_PCGPIO_P16 0x00010000 // GPIO Port S Power Control +#define SYSCTL_PCGPIO_P15 0x00008000 // GPIO Port R Power Control +#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control +#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control +#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control +#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control +#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control +#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control +#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control +#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control +#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control +#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control +#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control +#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control +#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control +#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control +#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCDMA register. +// +//***************************************************************************** +#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCEPI register. +// +//***************************************************************************** +#define SYSCTL_PCEPI_P0 0x00000001 // EPI Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCHIB register. +// +//***************************************************************************** +#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCUART register. +// +//***************************************************************************** +#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control +#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control +#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control +#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control +#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control +#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control +#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control +#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCSSI register. +// +//***************************************************************************** +#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control +#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control +#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control +#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCI2C register. +// +//***************************************************************************** +#define SYSCTL_PCI2C_P9 0x00000200 // I2C Module 9 Power Control +#define SYSCTL_PCI2C_P8 0x00000100 // I2C Module 8 Power Control +#define SYSCTL_PCI2C_P7 0x00000080 // I2C Module 7 Power Control +#define SYSCTL_PCI2C_P6 0x00000040 // I2C Module 6 Power Control +#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control +#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control +#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control +#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control +#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control +#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCUSB register. +// +//***************************************************************************** +#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCEPHY register. +// +//***************************************************************************** +#define SYSCTL_PCEPHY_P0 0x00000001 // Ethernet PHY Module Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCCAN register. +// +//***************************************************************************** +#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control +#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCADC register. +// +//***************************************************************************** +#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control +#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCACMP register. +// +//***************************************************************************** +#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCPWM register. +// +//***************************************************************************** +#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCQEI register. +// +//***************************************************************************** +#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCCCM register. +// +//***************************************************************************** +#define SYSCTL_PCCCM_P0 0x00000001 // CRC and Cryptographic Modules + // Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCLCD register. +// +//***************************************************************************** +#define SYSCTL_PCLCD_P0 0x00000001 // LCD Controller Module 0 Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCOWIRE register. +// +//***************************************************************************** +#define SYSCTL_PCOWIRE_P0 0x00000001 // 1-Wire Module 0 Power Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PCEMAC register. +// +//***************************************************************************** +#define SYSCTL_PCEMAC_P0 0x00000001 // Ethernet MAC Module 0 Power + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWD register. +// +//***************************************************************************** +#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral + // Ready +#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRTIMER register. +// +//***************************************************************************** +#define SYSCTL_PRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer + // 7 Peripheral Ready +#define SYSCTL_PRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer + // 6 Peripheral Ready +#define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Peripheral Ready +#define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Peripheral Ready +#define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Peripheral Ready +#define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Peripheral Ready +#define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Peripheral Ready +#define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRGPIO register. +// +//***************************************************************************** +#define SYSCTL_PRGPIO_R17 0x00020000 // GPIO Port T Peripheral Ready +#define SYSCTL_PRGPIO_R16 0x00010000 // GPIO Port S Peripheral Ready +#define SYSCTL_PRGPIO_R15 0x00008000 // GPIO Port R Peripheral Ready +#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready +#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready +#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready +#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready +#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready +#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready +#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready +#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready +#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready +#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready +#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready +#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready +#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready +#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready +#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRDMA register. +// +//***************************************************************************** +#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREPI register. +// +//***************************************************************************** +#define SYSCTL_PREPI_R0 0x00000001 // EPI Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRHIB register. +// +//***************************************************************************** +#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUART register. +// +//***************************************************************************** +#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready +#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready +#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready +#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready +#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready +#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready +#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready +#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRSSI register. +// +//***************************************************************************** +#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready +#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready +#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready +#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRI2C register. +// +//***************************************************************************** +#define SYSCTL_PRI2C_R9 0x00000200 // I2C Module 9 Peripheral Ready +#define SYSCTL_PRI2C_R8 0x00000100 // I2C Module 8 Peripheral Ready +#define SYSCTL_PRI2C_R7 0x00000080 // I2C Module 7 Peripheral Ready +#define SYSCTL_PRI2C_R6 0x00000040 // I2C Module 6 Peripheral Ready +#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready +#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready +#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready +#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready +#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready +#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUSB register. +// +//***************************************************************************** +#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREPHY register. +// +//***************************************************************************** +#define SYSCTL_PREPHY_R0 0x00000001 // Ethernet PHY Module Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRCAN register. +// +//***************************************************************************** +#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready +#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRADC register. +// +//***************************************************************************** +#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready +#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRACMP register. +// +//***************************************************************************** +#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRPWM register. +// +//***************************************************************************** +#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready +#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRQEI register. +// +//***************************************************************************** +#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready +#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Peripheral Ready +#define SYSCTL_PRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Peripheral Ready +#define SYSCTL_PRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Peripheral Ready +#define SYSCTL_PRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Peripheral Ready +#define SYSCTL_PRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Peripheral Ready +#define SYSCTL_PRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRCCM register. +// +//***************************************************************************** +#define SYSCTL_PRCCM_R0 0x00000001 // CRC and Cryptographic Modules + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRLCD register. +// +//***************************************************************************** +#define SYSCTL_PRLCD_R0 0x00000001 // LCD Controller Module 0 + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PROWIRE register. +// +//***************************************************************************** +#define SYSCTL_PROWIRE_R0 0x00000001 // 1-Wire Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREMAC register. +// +//***************************************************************************** +#define SYSCTL_PREMAC_R0 0x00000001 // Ethernet MAC Module 0 Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID0 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID0_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID0_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID1 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID1_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID2 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID2_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID3 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID3_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID3_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_CCMCGREQ +// register. +// +//***************************************************************************** +#define SYSCTL_CCMCGREQ_DESCFG 0x00000004 // DES Clock Gating Request +#define SYSCTL_CCMCGREQ_AESCFG 0x00000002 // AES Clock Gating Request +#define SYSCTL_CCMCGREQ_SHACFG 0x00000001 // SHA/MD5 Clock Gating Request + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_DID0 +// register. +// +//***************************************************************************** +#define SYSCTL_DID0_CLASS_BLIZZARD \ + 0x00050000 // Tiva(TM) C Series TM4C123-class + // microcontrollers +#define SYSCTL_DID0_CLASS_SNOWFLAKE \ + 0x000A0000 // Tiva(TM) C Series TM4C129-class + // microcontrollers + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RESC +// register. +// +//***************************************************************************** +#define SYSCTL_RESC_HIB 0x00000040 // HIB Reset + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_PWRTC +// register. +// +//***************************************************************************** +#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010 // VDDA Under BOR0 Status +#define SYSCTL_PWRTC_VDD_UBOR0 0x00000001 // VDD Under BOR0 Status + +#endif + +#endif // __HW_SYSCTL_H__ diff --git a/os/common/ext/TivaWare/inc/hw_sysexc.h b/os/common/ext/TivaWare/inc/hw_sysexc.h new file mode 100644 index 0000000..a6eec99 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_sysexc.h @@ -0,0 +1,132 @@ +//***************************************************************************** +// +// hw_sysexc.h - Macros used when accessing the system exception module. +// +// Copyright (c) 2011-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_SYSEXC_H__ +#define __HW_SYSEXC_H__ + +//***************************************************************************** +// +// The following are defines for the System Exception Module register +// addresses. +// +//***************************************************************************** +#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt + // Status +#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask +#define SYSEXC_MIS 0x400F9008 // System Exception Masked + // Interrupt Status +#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_RIS register. +// +//***************************************************************************** +#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception + // Raw Interrupt Status +#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation + // Raw Interrupt Status +#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0 + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal + // Exception Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IM register. +// +//***************************************************************************** +#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception + // Interrupt Mask +#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation + // Interrupt Mask +#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Mask +#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_MIS register. +// +//***************************************************************************** +#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception + // Masked Interrupt Status +#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation + // Masked Interrupt Status +#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0 + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal + // Exception Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IC register. +// +//***************************************************************************** +#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception + // Interrupt Clear +#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation + // Interrupt Clear +#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Clear +#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Clear + +#endif // __HW_SYSEXC_H__ diff --git a/os/common/ext/TivaWare/inc/hw_timer.h b/os/common/ext/TivaWare/inc/hw_timer.h new file mode 100644 index 0000000..25a7ed9 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_timer.h @@ -0,0 +1,700 @@ +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following are defines for the Timer register offsets. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // GPTM Configuration +#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode +#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode +#define TIMER_O_CTL 0x0000000C // GPTM Control +#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize +#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask +#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status +#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status +#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear +#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load +#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load +#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match +#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match +#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale +#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale +#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match +#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match +#define TIMER_O_TAR 0x00000048 // GPTM Timer A +#define TIMER_O_TBR 0x0000004C // GPTM Timer B +#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value +#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value +#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide +#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot +#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot +#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value +#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value +#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event +#define TIMER_O_ADCEV 0x00000070 // GPTM ADC Event +#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties +#define TIMER_O_CC 0x00000FC8 // GPTM Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this + // value selects the 32-bit timer + // configuration +#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this + // value selects the 32-bit + // real-time clock (RTC) counter + // configuration +#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this + // value selects the 16-bit timer + // configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +#define TIMER_TAMR_TCACT_M 0x0000E000 // Timer Compare Action Select +#define TIMER_TAMR_TCACT_NONE 0x00000000 // Disable compare operations +#define TIMER_TAMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out +#define TIMER_TAMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out +#define TIMER_TAMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out +#define TIMER_TAMR_TCACT_SETTOGTO \ + 0x00008000 // Set CCP immediately and toggle + // on Time-Out +#define TIMER_TAMR_TCACT_CLRTOGTO \ + 0x0000A000 // Clear CCP immediately and toggle + // on Time-Out +#define TIMER_TAMR_TCACT_SETCLRTO \ + 0x0000C000 // Set CCP immediately and clear on + // Time-Out +#define TIMER_TAMR_TCACT_CLRSETTO \ + 0x0000E000 // Clear CCP immediately and set on + // Time-Out +#define TIMER_TAMR_TACINTD 0x00001000 // One-shot/Periodic Interrupt + // Disable +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode + // Select +#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +#define TIMER_TBMR_TCACT_M 0x0000E000 // Timer Compare Action Select +#define TIMER_TBMR_TCACT_NONE 0x00000000 // Disable compare operations +#define TIMER_TBMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out +#define TIMER_TBMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out +#define TIMER_TBMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out +#define TIMER_TBMR_TCACT_SETTOGTO \ + 0x00008000 // Set CCP immediately and toggle + // on Time-Out +#define TIMER_TBMR_TCACT_CLRTOGTO \ + 0x0000A000 // Clear CCP immediately and toggle + // on Time-Out +#define TIMER_TBMR_TCACT_SETCLRTO \ + 0x0000C000 // Set CCP immediately and clear on + // Time-Out +#define TIMER_TBMR_TCACT_CLRSETTO \ + 0x0000E000 // Clear CCP immediately and set on + // Time-Out +#define TIMER_TBMR_TBCINTD 0x00001000 // One-Shot/Periodic Interrupt + // Disable +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode + // Select +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level +#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger + // Enable +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode +#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges +#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable +#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable +#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level +#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger + // Enable +#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode +#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges +#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable +#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer + // 5 +#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not + // affected +#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 5 is triggered +#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer + // 4 +#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not + // affected +#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 4 is triggered +#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer + // 3 +#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not + // affected +#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 3 is triggered +#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer + // 2 +#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not + // affected +#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 2 is triggered +#define TIMER_SYNC_SYNCT7_M 0x0000C000 // Synchronize GPTM Timer 7 +#define TIMER_SYNC_SYNCT7_NONE 0x00000000 // GPT7 is not affected +#define TIMER_SYNC_SYNCT7_TA 0x00004000 // A timeout event for Timer A of + // GPTM7 is triggered +#define TIMER_SYNC_SYNCT7_TB 0x00008000 // A timeout event for Timer B of + // GPTM7 is triggered +#define TIMER_SYNC_SYNCT7_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM7 is + // triggered +#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer + // 1 +#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not + // affected +#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 1 is triggered +#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer + // 0 +#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not + // affected +#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 0 is triggered +#define TIMER_SYNC_SYNCT6_M 0x00003000 // Synchronize GPTM Timer 6 +#define TIMER_SYNC_SYNCT6_NONE 0x00000000 // GPTM6 is not affected +#define TIMER_SYNC_SYNCT6_TA 0x00001000 // A timeout event for Timer A of + // GPTM6 is triggered +#define TIMER_SYNC_SYNCT6_TB 0x00002000 // A timeout event for Timer B of + // GPTM6 is triggered +#define TIMER_SYNC_SYNCT6_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM6 is + // triggered +#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5 +#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected +#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of + // GPTM5 is triggered +#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of + // GPTM5 is triggered +#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM5 is + // triggered +#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4 +#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected +#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of + // GPTM4 is triggered +#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of + // GPTM4 is triggered +#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM4 is + // triggered +#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3 +#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected +#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of + // GPTM3 is triggered +#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of + // GPTM3 is triggered +#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM3 is + // triggered +#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2 +#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected +#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of + // GPTM2 is triggered +#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of + // GPTM2 is triggered +#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM2 is + // triggered +#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1 +#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected +#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of + // GPTM1 is triggered +#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of + // GPTM1 is triggered +#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM1 is + // triggered +#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0 +#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected +#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of + // GPTM0 is triggered +#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of + // GPTM0 is triggered +#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM0 is + // triggered + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Mask +#define TIMER_IMR_DMABIM 0x00002000 // GPTM Timer B DMA Done Interrupt + // Mask +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt + // Mask +#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt + // Mask +#define TIMER_IMR_DMAAIM 0x00000020 // GPTM Timer A DMA Done Interrupt + // Mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt + // Mask +#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask +#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Raw Interrupt Status +#define TIMER_RIS_DMABRIS 0x00002000 // GPTM Timer B DMA Done Raw + // Interrupt Status +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt +#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw + // Interrupt +#define TIMER_RIS_DMAARIS 0x00000020 // GPTM Timer A DMA Done Raw + // Interrupt Status +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt +#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt +#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Masked Interrupt Status +#define TIMER_MIS_DMABMIS 0x00002000 // GPTM Timer B DMA Done Masked + // Interrupt +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked + // Interrupt +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked + // Interrupt +#define TIMER_MIS_DMAAMIS 0x00000020 // GPTM Timer A DMA Done Masked + // Interrupt +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked + // Interrupt +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Clear +#define TIMER_ICR_DMABINT 0x00002000 // GPTM Timer B DMA Done Interrupt + // Clear +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt + // Clear +#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt + // Clear +#define TIMER_ICR_DMAAINT 0x00000020 // GPTM Timer A DMA Done Interrupt + // Clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt + // Clear +#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear +#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register +#define TIMER_TAILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register +#define TIMER_TAMATCHR_TAMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register +#define TIMER_TBMATCHR_TBMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +#define TIMER_TAPR_TAPSRH_S 8 +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +#define TIMER_TBPR_TBPSRH_S 8 +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +#define TIMER_TAPMR_TAPSMRH_S 8 +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +#define TIMER_TBPMR_TBPSMRH_S 8 +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register +#define TIMER_TAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register +#define TIMER_TBR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value +#define TIMER_TAV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_DMAEV register. +// +//***************************************************************************** +#define TIMER_DMAEV_TBMDMAEN 0x00000800 // GPTM B Mode Match Event DMA + // Trigger Enable +#define TIMER_DMAEV_CBEDMAEN 0x00000400 // GPTM B Capture Event DMA Trigger + // Enable +#define TIMER_DMAEV_CBMDMAEN 0x00000200 // GPTM B Capture Match Event DMA + // Trigger Enable +#define TIMER_DMAEV_TBTODMAEN 0x00000100 // GPTM B Time-Out Event DMA + // Trigger Enable +#define TIMER_DMAEV_TAMDMAEN 0x00000010 // GPTM A Mode Match Event DMA + // Trigger Enable +#define TIMER_DMAEV_RTCDMAEN 0x00000008 // GPTM A RTC Match Event DMA + // Trigger Enable +#define TIMER_DMAEV_CAEDMAEN 0x00000004 // GPTM A Capture Event DMA Trigger + // Enable +#define TIMER_DMAEV_CAMDMAEN 0x00000002 // GPTM A Capture Match Event DMA + // Trigger Enable +#define TIMER_DMAEV_TATODMAEN 0x00000001 // GPTM A Time-Out Event DMA + // Trigger Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ADCEV register. +// +//***************************************************************************** +#define TIMER_ADCEV_TBMADCEN 0x00000800 // GPTM B Mode Match Event ADC + // Trigger Enable +#define TIMER_ADCEV_CBEADCEN 0x00000400 // GPTM B Capture Event ADC Trigger + // Enable +#define TIMER_ADCEV_CBMADCEN 0x00000200 // GPTM B Capture Match Event ADC + // Trigger Enable +#define TIMER_ADCEV_TBTOADCEN 0x00000100 // GPTM B Time-Out Event ADC + // Trigger Enable +#define TIMER_ADCEV_TAMADCEN 0x00000010 // GPTM A Mode Match Event ADC + // Trigger Enable +#define TIMER_ADCEV_RTCADCEN 0x00000008 // GPTM RTC Match Event ADC Trigger + // Enable +#define TIMER_ADCEV_CAEADCEN 0x00000004 // GPTM A Capture Event ADC Trigger + // Enable +#define TIMER_ADCEV_CAMADCEN 0x00000002 // GPTM A Capture Match Event ADC + // Trigger Enable +#define TIMER_ADCEV_TATOADCEN 0x00000001 // GPTM A Time-Out Event ADC + // Trigger Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_ALTCLK 0x00000040 // Alternate Clock Source +#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start +#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are + // 32 bits each with a 16-bit + // prescale counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CC register. +// +//***************************************************************************** +#define TIMER_CC_ALTCLK 0x00000001 // Alternate Clock Source + +#endif // __HW_TIMER_H__ diff --git a/os/common/ext/TivaWare/inc/hw_types.h b/os/common/ext/TivaWare/inc/hw_types.h new file mode 100644 index 0000000..6312a28 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_types.h @@ -0,0 +1,147 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +//***************************************************************************** +// +// Helper Macros for determining silicon revisions, etc. +// +// These macros will be used by Driverlib at "run-time" to create necessary +// conditional code blocks that will allow a single version of the Driverlib +// "binary" code to support multiple(all) Tiva silicon revisions. +// +// It is expected that these macros will be used inside of a standard 'C' +// conditional block of code, e.g. +// +// if(CLASS_IS_TM4C123) +// { +// do some TM4C123-class specific code here. +// } +// +// By default, these macros will be defined as run-time checks of the +// appropriate register(s) to allow creation of run-time conditional code +// blocks for a common DriverLib across the entire Tiva family. +// +// However, if code-space optimization is required, these macros can be "hard- +// coded" for a specific version of Tiva silicon. Many compilers will then +// detect the "hard-coded" conditionals, and appropriately optimize the code +// blocks, eliminating any "unreachable" code. This would result in a smaller +// Driverlib, thus producing a smaller final application size, but at the cost +// of limiting the Driverlib binary to a specific Tiva silicon revision. +// +//***************************************************************************** +#ifndef CLASS_IS_TM4C123 +#define CLASS_IS_TM4C123 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C123)) +#endif + +#ifndef CLASS_IS_TM4C129 +#define CLASS_IS_TM4C129 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C129)) +#endif + +#ifndef REVISION_IS_A0 +#define REVISION_IS_A0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A1 +#define REVISION_IS_A1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A2 +#define REVISION_IS_A2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2)) +#endif + +#ifndef REVISION_IS_B0 +#define REVISION_IS_B0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_B1 +#define REVISION_IS_B1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1)) +#endif + +//***************************************************************************** +// +// For TivaWare 2.1, we removed all references to Tiva IC codenames from the +// source. To ensure that existing customer code doesn't break as a result +// of this change, make sure that the old definitions are still available at +// least for the time being. +// +//***************************************************************************** +#ifndef DEPRECATED +#define CLASS_IS_BLIZZARD CLASS_IS_TM4C123 +#define CLASS_IS_SNOWFLAKE CLASS_IS_TM4C123 +#endif + +#endif // __HW_TYPES_H__ diff --git a/os/common/ext/TivaWare/inc/hw_uart.h b/os/common/ext/TivaWare/inc/hw_uart.h new file mode 100644 index 0000000..cca4b93 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_uart.h @@ -0,0 +1,367 @@ +//***************************************************************************** +// +// hw_uart.h - Macros and defines used when accessing the UART hardware. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// The following are defines for the UART register offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 // UART Data +#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear +#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear +#define UART_O_FR 0x00000018 // UART Flag +#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register +#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor +#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate + // Divisor +#define UART_O_LCRH 0x0000002C // UART Line Control +#define UART_O_CTL 0x00000030 // UART Control +#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select +#define UART_O_IM 0x00000038 // UART Interrupt Mask +#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status +#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status +#define UART_O_ICR 0x00000044 // UART Interrupt Clear +#define UART_O_DMACTL 0x00000048 // UART DMA Control +#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address +#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask +#define UART_O_PP 0x00000FC0 // UART Peripheral Properties +#define UART_O_CC 0x00000FC8 // UART Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // UART Overrun Error +#define UART_DR_BE 0x00000400 // UART Break Error +#define UART_DR_PE 0x00000200 // UART Parity Error +#define UART_DR_FE 0x00000100 // UART Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // UART Overrun Error +#define UART_RSR_BE 0x00000004 // UART Break Error +#define UART_RSR_PE 0x00000002 // UART Parity Error +#define UART_RSR_FE 0x00000001 // UART Framing Error + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//***************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear +#define UART_ECR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//***************************************************************************** +#define UART_FR_RI 0x00000100 // Ring Indicator +#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty +#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full +#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full +#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_DCD 0x00000004 // Data Carrier Detect +#define UART_FR_DSR 0x00000002 // Data Set Ready +#define UART_FR_CTS 0x00000001 // Clear To Send + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//***************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor +#define UART_ILPR_ILPDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//***************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//***************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable +#define UART_LCRH_BRK 0x00000001 // UART Send Break + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send +#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send +#define UART_CTL_RTS 0x00000800 // Request to Send +#define UART_CTL_DTR 0x00000400 // Data Terminal Ready +#define UART_CTL_RXE 0x00000200 // UART Receive Enable +#define UART_CTL_TXE 0x00000100 // UART Transmit Enable +#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable +#define UART_CTL_HSE 0x00000020 // High-Speed Enable +#define UART_CTL_EOT 0x00000010 // End of Transmission +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support +#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode +#define UART_CTL_SIREN 0x00000002 // UART SIR Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//***************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO + // Level Select +#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full +#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full +#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) +#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full +#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full +#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO + // Level Select +#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full +#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full +#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) +#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full +#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//***************************************************************************** +#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask +#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask +#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt + // Mask +#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt + // Mask +#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt + // Mask +#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt + // Mask +#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask +#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem + // Interrupt Mask +#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Mask +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask +#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem + // Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//***************************************************************************** +#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt + // Status +#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status +#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw + // Interrupt Status +#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt + // Status +#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt + // Status +#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt + // Status +#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt + // Status +#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw + // Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt + // Status +#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt + // Status +#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw + // Interrupt Status +#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem + // Raw Interrupt Status +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status +#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//***************************************************************************** +#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt + // Status +#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt + // Status +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status +#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked + // Interrupt Status +#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked + // Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked + // Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked + // Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked + // Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked + // Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt + // Status +#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt + // Status +#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked + // Interrupt Status +#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem + // Masked Interrupt Status +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status +#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//***************************************************************************** +#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear +#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear +#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt + // Clear +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem + // Interrupt Clear +#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Clear +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear +#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem + // Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//***************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITADDR +// register. +// +//***************************************************************************** +#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode +#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode +#define UART_9BITADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITAMASK +// register. +// +//***************************************************************************** +#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode +#define UART_9BITAMASK_MASK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//***************************************************************************** +#define UART_PP_MSE 0x00000008 // Modem Support Extended +#define UART_PP_MS 0x00000004 // Modem Support +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//***************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source +#define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock + // source and divisor factor) +#define UART_CC_CS_PIOSC 0x00000005 // PIOSC + +#endif // __HW_UART_H__ diff --git a/os/common/ext/TivaWare/inc/hw_udma.h b/os/common/ext/TivaWare/inc/hw_udma.h new file mode 100644 index 0000000..85bc014 --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_udma.h @@ -0,0 +1,414 @@ +//***************************************************************************** +// +// hw_udma.h - Macros for use in accessing the UDMA registers. +// +// Copyright (c) 2007-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// The following are defines for the Micro Direct Memory Access register +// addresses. +// +//***************************************************************************** +#define UDMA_STAT 0x400FF000 // DMA Status +#define UDMA_CFG 0x400FF004 // DMA Configuration +#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer +#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control + // Base Pointer +#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request + // Status +#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request +#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set +#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear +#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set +#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear +#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set +#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear +#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate + // Set +#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate + // Clear +#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set +#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear +#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear +#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment +#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status +#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0 +#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1 +#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2 +#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_STAT register. +// +//***************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status +#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle +#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data +#define UDMA_STAT_STATE_RD_SRCENDP \ + 0x00000020 // Reading source end pointer +#define UDMA_STAT_STATE_RD_DSTENDP \ + 0x00000030 // Reading destination end pointer +#define UDMA_STAT_STATE_RD_SRCDAT \ + 0x00000040 // Reading source data +#define UDMA_STAT_STATE_WR_DSTDAT \ + 0x00000050 // Writing destination data +#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to + // clear +#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data +#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled +#define UDMA_STAT_STATE_DONE 0x00000090 // Done +#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status +#define UDMA_STAT_DMACHANS_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CFG register. +// +//***************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CTLBASE register. +// +//***************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address +#define UDMA_CTLBASE_ADDR_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTBASE register. +// +//***************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer +#define UDMA_ALTBASE_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_WAITSTAT register. +// +//***************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_SWREQ register. +// +//***************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTSET +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTCLR +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKSET +// register. +// +//***************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKCLR +// register. +// +//***************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENASET register. +// +//***************************************************************************** +#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENACLR register. +// +//***************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTSET register. +// +//***************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTCLR register. +// +//***************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOSET register. +// +//***************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOCLR register. +// +//***************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ERRCLR register. +// +//***************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHASGN register. +// +//***************************************************************************** +#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select +#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel + // assignment +#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel + // assignment + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHIS register. +// +//***************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP0 register. +// +//***************************************************************************** +#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select +#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select +#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select +#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select +#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select +#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select +#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select +#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select +#define UDMA_CHMAP0_CH7SEL_S 28 +#define UDMA_CHMAP0_CH6SEL_S 24 +#define UDMA_CHMAP0_CH5SEL_S 20 +#define UDMA_CHMAP0_CH4SEL_S 16 +#define UDMA_CHMAP0_CH3SEL_S 12 +#define UDMA_CHMAP0_CH2SEL_S 8 +#define UDMA_CHMAP0_CH1SEL_S 4 +#define UDMA_CHMAP0_CH0SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP1 register. +// +//***************************************************************************** +#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select +#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select +#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select +#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select +#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select +#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select +#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select +#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select +#define UDMA_CHMAP1_CH15SEL_S 28 +#define UDMA_CHMAP1_CH14SEL_S 24 +#define UDMA_CHMAP1_CH13SEL_S 20 +#define UDMA_CHMAP1_CH12SEL_S 16 +#define UDMA_CHMAP1_CH11SEL_S 12 +#define UDMA_CHMAP1_CH10SEL_S 8 +#define UDMA_CHMAP1_CH9SEL_S 4 +#define UDMA_CHMAP1_CH8SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP2 register. +// +//***************************************************************************** +#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select +#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select +#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select +#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select +#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select +#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select +#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select +#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select +#define UDMA_CHMAP2_CH23SEL_S 28 +#define UDMA_CHMAP2_CH22SEL_S 24 +#define UDMA_CHMAP2_CH21SEL_S 20 +#define UDMA_CHMAP2_CH20SEL_S 16 +#define UDMA_CHMAP2_CH19SEL_S 12 +#define UDMA_CHMAP2_CH18SEL_S 8 +#define UDMA_CHMAP2_CH17SEL_S 4 +#define UDMA_CHMAP2_CH16SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP3 register. +// +//***************************************************************************** +#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select +#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select +#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select +#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select +#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select +#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select +#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select +#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select +#define UDMA_CHMAP3_CH31SEL_S 28 +#define UDMA_CHMAP3_CH30SEL_S 24 +#define UDMA_CHMAP3_CH29SEL_S 20 +#define UDMA_CHMAP3_CH28SEL_S 16 +#define UDMA_CHMAP3_CH27SEL_S 12 +#define UDMA_CHMAP3_CH26SEL_S 8 +#define UDMA_CHMAP3_CH25SEL_S 4 +#define UDMA_CHMAP3_CH24SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the Micro Direct Memory Access (uDMA) offsets. +// +//***************************************************************************** +#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End + // Pointer +#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address + // End Pointer +#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SRCENDP register. +// +//***************************************************************************** +#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer +#define UDMA_SRCENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_DSTENDP register. +// +//***************************************************************************** +#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer +#define UDMA_DSTENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHCTL register. +// +//***************************************************************************** +#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment +#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word +#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word +#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment +#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size +#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word +#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word +#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment +#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word +#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word +#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment +#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size +#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word +#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word +#define UDMA_CHCTL_DSTPROT0 0x00200000 // Destination Privilege Access +#define UDMA_CHCTL_SRCPROT0 0x00040000 // Source Privilege Access +#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size +#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer +#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers +#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers +#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers +#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers +#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers +#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers +#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers +#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers +#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers +#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers +#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) +#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst +#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_CHCTL_XFERMODE_STOP \ + 0x00000000 // Stop +#define UDMA_CHCTL_XFERMODE_BASIC \ + 0x00000001 // Basic +#define UDMA_CHCTL_XFERMODE_AUTO \ + 0x00000002 // Auto-Request +#define UDMA_CHCTL_XFERMODE_PINGPONG \ + 0x00000003 // Ping-Pong +#define UDMA_CHCTL_XFERMODE_MEM_SG \ + 0x00000004 // Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_MEM_SGA \ + 0x00000005 // Alternate Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SG \ + 0x00000006 // Peripheral Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SGA \ + 0x00000007 // Alternate Peripheral + // Scatter-Gather +#define UDMA_CHCTL_XFERSIZE_S 4 + +#endif // __HW_UDMA_H__ diff --git a/os/common/ext/TivaWare/inc/hw_usb.h b/os/common/ext/TivaWare/inc/hw_usb.h new file mode 100644 index 0000000..5d4027a --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_usb.h @@ -0,0 +1,3032 @@ +//***************************************************************************** +// +// hw_usb.h - Macros for use in accessing the USB registers. +// +// Copyright (c) 2007-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_USB_H__ +#define __HW_USB_H__ + +//***************************************************************************** +// +// The following are defines for the Univeral Serial Bus register offsets. +// +//***************************************************************************** +#define USB_O_FADDR 0x00000000 // USB Device Functional Address +#define USB_O_POWER 0x00000001 // USB Power +#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status +#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status +#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable +#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable +#define USB_O_IS 0x0000000A // USB General Interrupt Status +#define USB_O_IE 0x0000000B // USB Interrupt Enable +#define USB_O_FRAME 0x0000000C // USB Frame Value +#define USB_O_EPIDX 0x0000000E // USB Endpoint Index +#define USB_O_TEST 0x0000000F // USB Test Mode +#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 +#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 +#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 +#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 +#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4 +#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 +#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 +#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 +#define USB_O_DEVCTL 0x00000060 // USB Device Control +#define USB_O_CCONF 0x00000061 // USB Common Configuration +#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing +#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing +#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address +#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address +#define USB_O_ULPIVBUSCTL 0x00000070 // USB ULPI VBUS Control +#define USB_O_ULPIREGDATA 0x00000074 // USB ULPI Register Data +#define USB_O_ULPIREGADDR 0x00000075 // USB ULPI Register Address +#define USB_O_ULPIREGCTL 0x00000076 // USB ULPI Register Control +#define USB_O_EPINFO 0x00000078 // USB Endpoint Information +#define USB_O_RAMINFO 0x00000079 // USB RAM Information +#define USB_O_CONTIM 0x0000007A // USB Connect Timing +#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing +#define USB_O_HSEOF 0x0000007C // USB High-Speed Last Transaction + // to End of Frame Timing +#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction + // to End of Frame Timing +#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction + // to End of Frame Timing +#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address + // Endpoint 0 +#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address + // Endpoint 0 +#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 +#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address + // Endpoint 1 +#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address + // Endpoint 1 +#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 +#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address + // Endpoint 1 +#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint + // 1 +#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 +#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address + // Endpoint 2 +#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address + // Endpoint 2 +#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 +#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address + // Endpoint 2 +#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint + // 2 +#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 +#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address + // Endpoint 3 +#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address + // Endpoint 3 +#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 +#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address + // Endpoint 3 +#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint + // 3 +#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 +#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address + // Endpoint 4 +#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address + // Endpoint 4 +#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4 +#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address + // Endpoint 4 +#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint + // 4 +#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4 +#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address + // Endpoint 5 +#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address + // Endpoint 5 +#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5 +#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address + // Endpoint 5 +#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint + // 5 +#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5 +#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address + // Endpoint 6 +#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address + // Endpoint 6 +#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6 +#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address + // Endpoint 6 +#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint + // 6 +#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6 +#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address + // Endpoint 7 +#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address + // Endpoint 7 +#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7 +#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address + // Endpoint 7 +#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint + // 7 +#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 +#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint + // 0 Low +#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint + // 0 High +#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint + // 0 +#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 +#define USB_O_NAKLMT 0x0000010B // USB NAK Limit +#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data + // Endpoint 1 +#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status + // Endpoint 1 Low +#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status + // Endpoint 1 High +#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data + // Endpoint 1 +#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status + // Endpoint 1 Low +#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status + // Endpoint 1 High +#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint + // 1 +#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type + // Endpoint 1 +#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval + // Endpoint 1 +#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type + // Endpoint 1 +#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling + // Interval Endpoint 1 +#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data + // Endpoint 2 +#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status + // Endpoint 2 Low +#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status + // Endpoint 2 High +#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data + // Endpoint 2 +#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status + // Endpoint 2 Low +#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status + // Endpoint 2 High +#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint + // 2 +#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type + // Endpoint 2 +#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval + // Endpoint 2 +#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type + // Endpoint 2 +#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling + // Interval Endpoint 2 +#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data + // Endpoint 3 +#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status + // Endpoint 3 Low +#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status + // Endpoint 3 High +#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data + // Endpoint 3 +#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status + // Endpoint 3 Low +#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status + // Endpoint 3 High +#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint + // 3 +#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type + // Endpoint 3 +#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval + // Endpoint 3 +#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type + // Endpoint 3 +#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling + // Interval Endpoint 3 +#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data + // Endpoint 4 +#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status + // Endpoint 4 Low +#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status + // Endpoint 4 High +#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data + // Endpoint 4 +#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status + // Endpoint 4 Low +#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status + // Endpoint 4 High +#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint + // 4 +#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type + // Endpoint 4 +#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval + // Endpoint 4 +#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type + // Endpoint 4 +#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling + // Interval Endpoint 4 +#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data + // Endpoint 5 +#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status + // Endpoint 5 Low +#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status + // Endpoint 5 High +#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data + // Endpoint 5 +#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status + // Endpoint 5 Low +#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status + // Endpoint 5 High +#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint + // 5 +#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type + // Endpoint 5 +#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval + // Endpoint 5 +#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type + // Endpoint 5 +#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling + // Interval Endpoint 5 +#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data + // Endpoint 6 +#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status + // Endpoint 6 Low +#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status + // Endpoint 6 High +#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data + // Endpoint 6 +#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status + // Endpoint 6 Low +#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status + // Endpoint 6 High +#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint + // 6 +#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type + // Endpoint 6 +#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval + // Endpoint 6 +#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type + // Endpoint 6 +#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling + // Interval Endpoint 6 +#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data + // Endpoint 7 +#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status + // Endpoint 7 Low +#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status + // Endpoint 7 High +#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data + // Endpoint 7 +#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status + // Endpoint 7 Low +#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status + // Endpoint 7 High +#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint + // 7 +#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type + // Endpoint 7 +#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval + // Endpoint 7 +#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type + // Endpoint 7 +#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling + // Interval Endpoint 7 +#define USB_O_DMAINTR 0x00000200 // USB DMA Interrupt +#define USB_O_DMACTL0 0x00000204 // USB DMA Control 0 +#define USB_O_DMAADDR0 0x00000208 // USB DMA Address 0 +#define USB_O_DMACOUNT0 0x0000020C // USB DMA Count 0 +#define USB_O_DMACTL1 0x00000214 // USB DMA Control 1 +#define USB_O_DMAADDR1 0x00000218 // USB DMA Address 1 +#define USB_O_DMACOUNT1 0x0000021C // USB DMA Count 1 +#define USB_O_DMACTL2 0x00000224 // USB DMA Control 2 +#define USB_O_DMAADDR2 0x00000228 // USB DMA Address 2 +#define USB_O_DMACOUNT2 0x0000022C // USB DMA Count 2 +#define USB_O_DMACTL3 0x00000234 // USB DMA Control 3 +#define USB_O_DMAADDR3 0x00000238 // USB DMA Address 3 +#define USB_O_DMACOUNT3 0x0000023C // USB DMA Count 3 +#define USB_O_DMACTL4 0x00000244 // USB DMA Control 4 +#define USB_O_DMAADDR4 0x00000248 // USB DMA Address 4 +#define USB_O_DMACOUNT4 0x0000024C // USB DMA Count 4 +#define USB_O_DMACTL5 0x00000254 // USB DMA Control 5 +#define USB_O_DMAADDR5 0x00000258 // USB DMA Address 5 +#define USB_O_DMACOUNT5 0x0000025C // USB DMA Count 5 +#define USB_O_DMACTL6 0x00000264 // USB DMA Control 6 +#define USB_O_DMAADDR6 0x00000268 // USB DMA Address 6 +#define USB_O_DMACOUNT6 0x0000026C // USB DMA Count 6 +#define USB_O_DMACTL7 0x00000274 // USB DMA Control 7 +#define USB_O_DMAADDR7 0x00000278 // USB DMA Address 7 +#define USB_O_DMACOUNT7 0x0000027C // USB DMA Count 7 +#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in + // Block Transfer Endpoint 1 +#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in + // Block Transfer Endpoint 2 +#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in + // Block Transfer Endpoint 3 +#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in + // Block Transfer Endpoint 4 +#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in + // Block Transfer Endpoint 5 +#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in + // Block Transfer Endpoint 6 +#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in + // Block Transfer Endpoint 7 +#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer + // Disable +#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet + // Buffer Disable +#define USB_O_CTO 0x00000344 // USB Chirp Timeout +#define USB_O_HHSRTN 0x00000346 // USB High Speed to UTM Operating + // Delay +#define USB_O_HSBT 0x00000348 // USB High Speed Time-out Adder +#define USB_O_LPMATTR 0x00000360 // USB LPM Attributes +#define USB_O_LPMCNTRL 0x00000362 // USB LPM Control +#define USB_O_LPMIM 0x00000363 // USB LPM Interrupt Mask +#define USB_O_LPMRIS 0x00000364 // USB LPM Raw Interrupt Status +#define USB_O_LPMFADDR 0x00000365 // USB LPM Function Address +#define USB_O_EPC 0x00000400 // USB External Power Control +#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw + // Interrupt Status +#define USB_O_EPCIM 0x00000408 // USB External Power Control + // Interrupt Mask +#define USB_O_EPCISC 0x0000040C // USB External Power Control + // Interrupt Status and Clear +#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt + // Status +#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask +#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt + // Status and Clear +#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and + // Status +#define USB_O_VDC 0x00000430 // USB VBUS Droop Control +#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw + // Interrupt Status +#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt + // Mask +#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt + // Status and Clear +#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw + // Interrupt Status +#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt + // Mask +#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt + // Status and Clear +#define USB_O_DMASEL 0x00000450 // USB DMA Select +#define USB_O_PP 0x00000FC0 // USB Peripheral Properties +#define USB_O_PC 0x00000FC4 // USB Peripheral Configuration +#define USB_O_CC 0x00000FC8 // USB Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_HSENAB 0x00000020 // High Speed Enable +#define USB_POWER_HSMODE 0x00000010 // High Speed Enable +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) +#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG + // only) +#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG + // only) +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode +#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode +#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable +#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable +#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable +#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CCONF register. +// +//***************************************************************************** +#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable +#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL +// register. +// +//***************************************************************************** +#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ + 0x00000002 // Use External VBUS Indicator +#define USB_ULPIVBUSCTL_USEEXTVBUS \ + 0x00000001 // Use External VBUS + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGDATA +// register. +// +//***************************************************************************** +#define USB_ULPIREGDATA_REGDATA_M \ + 0x000000FF // Register Data +#define USB_ULPIREGDATA_REGDATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGADDR +// register. +// +//***************************************************************************** +#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address +#define USB_ULPIREGADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGCTL +// register. +// +//***************************************************************************** +#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control +#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete +#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPINFO register. +// +//***************************************************************************** +#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints +#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints +#define USB_EPINFO_RXEP_S 4 +#define USB_EPINFO_TXEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RAMINFO register. +// +//***************************************************************************** +#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels +#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width +#define USB_RAMINFO_DMACHAN_S 4 +#define USB_RAMINFO_RAMBITS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSEOF register. +// +//***************************************************************************** +#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap +#define USB_HSEOF_HSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DISPING 0x00000008 // PING Disable +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_HIGH 0x00000040 // High +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle +#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle +#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle +#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle +#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle +#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle +#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle +#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAINTR register. +// +//***************************************************************************** +#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt +#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt +#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt +#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt +#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt +#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt +#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt +#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL0 register. +// +//***************************************************************************** +#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL0_DIR 0x00000002 // DMA Direction +#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL0_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR0 register. +// +//***************************************************************************** +#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR0_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT0 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT0_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL1 register. +// +//***************************************************************************** +#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL1_DIR 0x00000002 // DMA Direction +#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL1_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR1 register. +// +//***************************************************************************** +#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR1_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT1 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT1_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL2 register. +// +//***************************************************************************** +#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL2_DIR 0x00000002 // DMA Direction +#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL2_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR2 register. +// +//***************************************************************************** +#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR2_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT2 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT2_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL3 register. +// +//***************************************************************************** +#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL3_DIR 0x00000002 // DMA Direction +#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL3_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR3 register. +// +//***************************************************************************** +#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR3_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT3 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT3_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL4 register. +// +//***************************************************************************** +#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL4_DIR 0x00000002 // DMA Direction +#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL4_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR4 register. +// +//***************************************************************************** +#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR4_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT4 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT4_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL5 register. +// +//***************************************************************************** +#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL5_DIR 0x00000002 // DMA Direction +#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL5_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR5 register. +// +//***************************************************************************** +#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR5_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT5 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT5_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL6 register. +// +//***************************************************************************** +#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL6_DIR 0x00000002 // DMA Direction +#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL6_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR6 register. +// +//***************************************************************************** +#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR6_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT6 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT6_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL7 register. +// +//***************************************************************************** +#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL7_DIR 0x00000002 // DMA Direction +#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL7_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR7 register. +// +//***************************************************************************** +#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR7_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT7 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT7_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CTO register. +// +//***************************************************************************** +#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value +#define USB_CTO_CCTV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HHSRTN register. +// +//***************************************************************************** +#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating + // Delay +#define USB_HHSRTN_HHSRTN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSBT register. +// +//***************************************************************************** +#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder +#define USB_HSBT_HSBT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMATTR register. +// +//***************************************************************************** +#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint +#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake +#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration +#define USB_LPMATTR_LS_M 0x0000000F // Link State +#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) +#define USB_LPMATTR_ENDPT_S 12 +#define USB_LPMATTR_HIRD_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMCNTRL register. +// +//***************************************************************************** +#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK +#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable +#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions + // are not supported. In this case, + // the USB does not respond to LPM + // transactions and LPM + // transactions cause a timeout +#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but + // extended transactions are + // supported. In this case, the USB + // does respond to an LPM + // transaction with a STALL +#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended + // transactions. In this case, the + // USB responds with a NYET or an + // ACK as determined by the value + // of TXLPM and other conditions +#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume +#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMIM register. +// +//***************************************************************************** +#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask +#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask +#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask +#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask +#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask +#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMRIS register. +// +//***************************************************************************** +#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status +#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status +#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status +#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status +#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status +#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMFADDR register. +// +//***************************************************************************** +#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address +#define USB_LPMFADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low + // (OTG only) +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + // (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode +#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin +#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low +#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high +#define USB_GPCS_DEVMOD_HOSTVBUS \ + 0x00000004 // Use USB0VBUS and force USB0ID + // low +#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID + // high +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select +#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select +#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select +#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select +#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select +#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 +#define USB_DMASEL_DMABTX_S 12 +#define USB_DMASEL_DMABRX_S 8 +#define USB_DMASEL_DMAATX_S 4 +#define USB_DMASEL_DMAARX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_ULPI 0x00000020 // ULPI Present +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_TYPE_1 0x00000001 // Second-generation USB + // controller.The controller + // implemented in post Icestorm + // devices that use the 3.0 version + // of the Mentor controller +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PC register. +// +//***************************************************************************** +#define USB_PC_ULPIEN 0x00010000 // ULPI Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CC register. +// +//***************************************************************************** +#define USB_CC_CLKEN 0x00000200 // USB Clock Enable +#define USB_CC_CSD 0x00000100 // Clock Source/Direction +#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor +#define USB_CC_CLKDIV_S 0 + +#endif // __HW_USB_H__ diff --git a/os/common/ext/TivaWare/inc/hw_watchdog.h b/os/common/ext/TivaWare/inc/hw_watchdog.h new file mode 100644 index 0000000..f15948b --- /dev/null +++ b/os/common/ext/TivaWare/inc/hw_watchdog.h @@ -0,0 +1,122 @@ +//***************************************************************************** +// +// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. +// +// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_WATCHDOG_H__ +#define __HW_WATCHDOG_H__ + +//***************************************************************************** +// +// The following are defines for the Watchdog Timer register offsets. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 // Watchdog Load +#define WDT_O_VALUE 0x00000004 // Watchdog Value +#define WDT_O_CTL 0x00000008 // Watchdog Control +#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear +#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status +#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status +#define WDT_O_TEST 0x00000418 // Watchdog Test +#define WDT_O_LOCK 0x00000C00 // Watchdog Lock + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//***************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value +#define WDT_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//***************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value +#define WDT_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//***************************************************************************** +#define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type +#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable +#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//***************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear +#define WDT_ICR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//***************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//***************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock +#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WDT_LOCK_LOCKED 0x00000001 // Locked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +#endif // __HW_WATCHDOG_H__ diff --git a/os/common/ports/MSP430X/chcore.c b/os/common/ports/MSP430X/chcore.c index 7a8d7f2..b9001b0 100644 --- a/os/common/ports/MSP430X/chcore.c +++ b/os/common/ports/MSP430X/chcore.c @@ -32,6 +32,8 @@ /* Module exported variables. */
/*===========================================================================*/
+bool __msp430x_in_isr;
+
/*===========================================================================*/
/* Module local types. */
/*===========================================================================*/
@@ -98,6 +100,11 @@ void _port_thread_start(void) { asm volatile ("mov R5, R12");
asm volatile ("call R4");
#endif
+#if defined(_CHIBIOS_RT_CONF_)
+ chThdExit(MSG_OK);
+#endif
+#if defined(_CHIBIOS_NIL_CONF_)
chSysHalt(0);
+#endif
}
/** @} */
diff --git a/os/common/ports/MSP430X/chcore.h b/os/common/ports/MSP430X/chcore.h index 09f87c4..9e1efa8 100644 --- a/os/common/ports/MSP430X/chcore.h +++ b/os/common/ports/MSP430X/chcore.h @@ -28,6 +28,8 @@ #include <msp430.h>
#include <in430.h>
+extern bool __msp430x_in_isr;
+
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
@@ -225,21 +227,27 @@ struct port_context { * @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
*/
-#define PORT_IRQ_PROLOGUE()
+#define PORT_IRQ_PROLOGUE() __msp430x_in_isr = true;
/**
* @brief IRQ epilogue code.
* @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
-#define PORT_IRQ_EPILOGUE() chSchRescheduleS()
+#define PORT_IRQ_EPILOGUE() { \
+ __msp430x_in_isr = false; \
+ _dbg_check_lock(); \
+ if (chSchIsPreemptionRequired()) \
+ chSchDoReschedule(); \
+ _dbg_check_unlock(); \
+}
/**
* @brief IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
-#define PORT_IRQ_HANDLER(id) __attribute__ ((interrupt(id))) \
+#define PORT_IRQ_HANDLER(id) __attribute__ ((interrupt(id))) \
void ISR_ ## id (void)
/**
@@ -293,7 +301,7 @@ extern "C" { * @brief Port-related initialization code.
*/
static inline void port_init(void) {
-
+ __msp430x_in_isr = false;
}
/**
@@ -328,9 +336,7 @@ static inline bool port_irq_enabled(syssts_t sts) { * @retval true running in ISR mode.
*/
static inline bool port_is_isr_context(void) {
- /* Efficiency would be enhanced by not doing this,
- * because of implementation details */
- return __get_SR_register() & GIE;
+ return __msp430x_in_isr;
}
/**
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk index e9c97e5..263338a 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk @@ -6,6 +6,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C123x \ - $(CHIBIOS)/os/common/ext/CMSIS/include + $(CHIBIOS)/os/common/ext/CMSIS/include \ + $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk index e151434..6cf42f7 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk @@ -6,6 +6,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C129x \ - $(CHIBIOS)/os/common/ext/CMSIS/include + $(CHIBIOS)/os/common/ext/CMSIS/include \ + $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld diff --git a/os/common/startup/ARMCMx/devices/TM4C123x/cmparams.h b/os/common/startup/ARMCMx/devices/TM4C123x/cmparams.h index 933e111..067a751 100644 --- a/os/common/startup/ARMCMx/devices/TM4C123x/cmparams.h +++ b/os/common/startup/ARMCMx/devices/TM4C123x/cmparams.h @@ -17,11 +17,26 @@ /** * @file TM4C123x/cmparams.h * @brief ARM Cortex-M4 parameters for the TM4C123x. + * + * @defgroup ARMCMx_TM4C123x TM4C123x Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * TM4C123x platform. * @{ */ -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/* Defines required for correct CMSIS header functioning */ +#define __MPU_PRESENT 1 /**< MPU present */ +#define __NVIC_PRIO_BITS 3 /**< Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 1 /**< Use different SysTick Config */ +#define __FPU_PRESENT 1 /**< FPU present */ + +/* The following two defines are needed by ChibiOS */ +#define SVCall_IRQn -5 +#define PendSV_IRQn -3 /** * @brief Cortex core model. @@ -29,11 +44,6 @@ #define CORTEX_MODEL 4 /** - * @brief Memory Protection unit presence. - */ -#define CORTEX_HAS_MPU 1 - -/** * @brief Floating Point unit presence. */ #define CORTEX_HAS_FPU 1 @@ -57,56 +67,60 @@ /* If the device type is not externally defined, for example from the Makefile, then a file named board.h is included. This file must contain a device definition compatible with the include file.*/ -#if !defined(TM4C1230C3PM) && !defined(TM4C1230D5PM) && \ - !defined(TM4C1230E6PM) && !defined(TM4C1230H6PM) && \ - !defined(TM4C1231C3PM) && !defined(TM4C1231D5PM) && \ - !defined(TM4C1231D5PZ) && !defined(TM4C1231E6PM) && \ - !defined(TM4C1231E6PZ) && !defined(TM4C1231H6PGE) && \ - !defined(TM4C1231H6PM) && !defined(TM4C1231H6PZ) && \ - !defined(TM4C1232C3PM) && !defined(TM4C1232D5PM) && \ - !defined(TM4C1232E6PM) && !defined(TM4C1232H6PM) && \ - !defined(TM4C1233C3PM) && !defined(TM4C1233D5PM) && \ - !defined(TM4C1233D5PZ) && !defined(TM4C1233E6PM) && \ - !defined(TM4C1233E6PZ) && !defined(TM4C1233H6PGE) && \ - !defined(TM4C1233H6PM) && !defined(TM4C1233H6PZ) && \ - !defined(TM4C1236D5PM) && !defined(TM4C1236E6PM) && \ - !defined(TM4C1236H6PM) && !defined(TM4C1237D5PM) && \ - !defined(TM4C1237D5PZ) && !defined(TM4C1237E6PM) && \ - !defined(TM4C1237E6PZ) && !defined(TM4C1237H6PGE) && \ - !defined(TM4C1237H6PM) && !defined(TM4C1237H6PZ) && \ - !defined(TM4C123AE6PM) && !defined(TM4C123AH6PM) && \ - !defined(TM4C123BE6PM) && !defined(TM4C123BE6PZ) && \ - !defined(TM4C123BH6PGE) && !defined(TM4C123BH6PM) && \ - !defined(TM4C123BH6PZ) && !defined(TM4C123BH6ZRB) && \ - !defined(TM4C123FE6PM) && !defined(TM4C123FH6PM) && \ - !defined(TM4C123GE6PM) && !defined(TM4C123GE6PZ) && \ - !defined(TM4C123GH6PGE) && !defined(TM4C123GH6PM) && \ - !defined(TM4C123GH6PZ) && !defined(TM4C123GH6ZRB) && \ - !defined(TM4C123GH5ZXR) +#if !defined (PART_TM4C1230C3PM) && !defined (PART_TM4C1230D5PM) && \ + !defined (PART_TM4C1230E6PM) && !defined (PART_TM4C1230H6PM) && \ + !defined (PART_TM4C1231C3PM) && !defined (PART_TM4C1231D5PM) && \ + !defined (PART_TM4C1231D5PZ) && !defined (PART_TM4C1231E6PM) && \ + !defined (PART_TM4C1231E6PZ) && !defined (PART_TM4C1231H6PGE) && \ + !defined (PART_TM4C1231H6PM) && !defined (PART_TM4C1231H6PZ) && \ + !defined (PART_TM4C1232C3PM) && !defined (PART_TM4C1232D5PM) && \ + !defined (PART_TM4C1232E6PM) && !defined (PART_TM4C1232H6PM) && \ + !defined (PART_TM4C1233C3PM) && !defined (PART_TM4C1233D5PM) && \ + !defined (PART_TM4C1233D5PZ) && !defined (PART_TM4C1233E6PM) && \ + !defined (PART_TM4C1233E6PZ) && !defined (PART_TM4C1233H6PGE) && \ + !defined (PART_TM4C1233H6PM) && !defined (PART_TM4C1233H6PZ) && \ + !defined (PART_TM4C1236D5PM) && !defined (PART_TM4C1236E6PM) && \ + !defined (PART_TM4C1236H6PM) && !defined (PART_TM4C1237D5PM) && \ + !defined (PART_TM4C1237D5PZ) && !defined (PART_TM4C1237E6PM) && \ + !defined (PART_TM4C1237E6PZ) && !defined (PART_TM4C1237H6PGE) && \ + !defined (PART_TM4C1237H6PM) && !defined (PART_TM4C1237H6PZ) && \ + !defined (PART_TM4C123AE6PM) && !defined (PART_TM4C123AH6PM) && \ + !defined (PART_TM4C123BE6PM) && !defined (PART_TM4C123BE6PZ) && \ + !defined (PART_TM4C123BH6PGE) && !defined (PART_TM4C123BH6PM) && \ + !defined (PART_TM4C123BH6PZ) && !defined (PART_TM4C123BH6ZRB) && \ + !defined (PART_TM4C123FE6PM) && !defined (PART_TM4C123FH6PM) && \ + !defined (PART_TM4C123GE6PM) && !defined (PART_TM4C123GE6PZ) && \ + !defined (PART_TM4C123GH6PGE) && !defined (PART_TM4C123GH6PM) && \ + !defined (PART_TM4C123GH6PZ) && !defined (PART_TM4C123GH6ZRB) && \ + !defined (PART_TM4C123GH5ZXR) #include "board.h" #endif -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "tm4c123x.h" - -#if !CORTEX_HAS_MPU != !__MPU_PRESENT -#error "CMSIS __MPU_PRESENT mismatch" -#endif - -#if !CORTEX_HAS_FPU != !__FPU_PRESENT -#error "CMSIS __FPU_PRESENT mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" +typedef int IRQn_Type; + +#include "core_cm4.h" + +/* Including the TivaWare peripheral headers.*/ +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_timer.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_gpio.h" +#include "inc/hw_uart.h" +#include "inc/hw_timer.h" +#include "inc/hw_i2c.h" +#include "inc/hw_watchdog.h" +#include "inc/hw_ssi.h" +#include "inc/hw_udma.h" +#include "inc/hw_pwm.h" + +#if CORTEX_NUM_VECTORS != ((((NUM_INTERRUPTS - 16) + 7) / 8) * 8) +#error "TivaWare NUM_INTERRUPTS mismatch" #endif #endif /* !defined(_FROM_ASM_) */ -#endif /* _CMPARAMS_H_ */ +#endif /* CMPARAMS_H */ -/** - * @} - */ +/** @} */ diff --git a/os/common/startup/ARMCMx/devices/TM4C129x/cmparams.h b/os/common/startup/ARMCMx/devices/TM4C129x/cmparams.h index 1d2661d..69d1e01 100644 --- a/os/common/startup/ARMCMx/devices/TM4C129x/cmparams.h +++ b/os/common/startup/ARMCMx/devices/TM4C129x/cmparams.h @@ -17,11 +17,26 @@ /** * @file TM4C129x/cmparams.h * @brief ARM Cortex-M4 parameters for the TM4C129x. + * + * @defgroup ARMCMx_TM4C129x TM4C129x Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * TM4C129x platform. * @{ */ -#ifndef _CMPARAMS_H_ -#define _CMPARAMS_H_ +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/* Defines required for correct CMSIS header functioning */ +#define __MPU_PRESENT 1 /**< MPU present */ +#define __NVIC_PRIO_BITS 3 /**< Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 1 /**< Use different SysTick Config */ +#define __FPU_PRESENT 1 /**< FPU present */ + +/* The following two defines are needed by ChibiOS */ +#define SVCall_IRQn -5 +#define PendSV_IRQn -3 /** * @brief Cortex core model. @@ -29,11 +44,6 @@ #define CORTEX_MODEL 4 /** - * @brief Memory Protection unit presence. - */ -#define CORTEX_HAS_MPU 1 - -/** * @brief Floating Point unit presence. */ #define CORTEX_HAS_FPU 1 @@ -48,7 +58,7 @@ * @note This number does not include the 16 system vectors and must be * rounded to a multiple of 8. */ -#define CORTEX_NUM_VECTORS 112 +#define CORTEX_NUM_VECTORS 120 /* The following code is not processed when the file is included from an asm module.*/ @@ -57,40 +67,45 @@ /* If the device type is not externally defined, for example from the Makefile, then a file named board.h is included. This file must contain a device definition compatible with the include file.*/ -#if !defined(TM4C1290NCPDT) && !defined(TM4C1290NCZAD) \ - && !defined(TM4C1292NCPDT) && !defined(TM4C1292NCZAD) \ - && !defined(TM4C1294KCPDT) && !defined(TM4C1294NCPDT) \ - && !defined(TM4C1294NCZAD) && !defined(TM4C1297NCZAD) \ - && !defined(TM4C1299KCZAD) && !defined(TM4C1299NCZAD) \ - && !defined(TM4C129CNCPDT) && !defined(TM4C129CNCZAD) \ - && !defined(TM4C129DNCPDT) && !defined(TM4C129DNCZAD) \ - && !defined(TM4C129EKCPDT) && !defined(TM4C129ENCPDT) \ - && !defined(TM4C129ENCZAD) && !defined(TM4C129LNCZAD) \ - && !defined(TM4C129XKCZAD) && !defined(TM4C129XNCZAD) +#if !defined (PART_TM4C1290NCPDT) && !defined (PART_TM4C1290NCZAD) && \ + !defined (PART_TM4C1292NCPDT) && !defined (PART_TM4C1292NCZAD) && \ + !defined (PART_TM4C1294KCPDT) && !defined (PART_TM4C1294NCPDT) && \ + !defined (PART_TM4C1294NCZAD) && !defined (PART_TM4C1297NCZAD) && \ + !defined (PART_TM4C1299KCZAD) && !defined (PART_TM4C1299NCZAD) && \ + !defined (PART_TM4C129CNCPDT) && !defined (PART_TM4C129CNCZAD) && \ + !defined (PART_TM4C129DNCPDT) && !defined (PART_TM4C129DNCZAD) && \ + !defined (PART_TM4C129EKCPDT) && !defined (PART_TM4C129ENCPDT) && \ + !defined (PART_TM4C129ENCZAD) && !defined (PART_TM4C129LNCZAD) && \ + !defined (PART_TM4C129XKCZAD) && !defined (PART_TM4C129XNCZAD) #include "board.h" #endif -/* Including the device CMSIS header. Note, we are not using the definitions - from this header because we need this file to be usable also from - assembler source files. We verify that the info matches instead.*/ -#include "tm4c129x.h" - -#if !CORTEX_HAS_MPU != !__MPU_PRESENT -#error "CMSIS __MPU_PRESENT mismatch" -#endif - -#if !CORTEX_HAS_FPU != !__FPU_PRESENT -#error "CMSIS __FPU_PRESENT mismatch" -#endif - -#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS -#error "CMSIS __NVIC_PRIO_BITS mismatch" +typedef int IRQn_Type; + +#include "core_cm4.h" + +/* Including the TivaWare peripheral headers.*/ +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_timer.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_gpio.h" +#include "inc/hw_uart.h" +#include "inc/hw_timer.h" +#include "inc/hw_emac.h" +#include "inc/hw_i2c.h" +#include "inc/hw_watchdog.h" +#include "inc/hw_ssi.h" +#include "inc/hw_udma.h" +#include "inc/hw_pwm.h" + +#if CORTEX_NUM_VECTORS != ((((NUM_INTERRUPTS - 16) + 7) / 8) * 8) +#error "TivaWare NUM_INTERRUPTS mismatch" #endif #endif /* !defined(_FROM_ASM_) */ -#endif /* _CMPARAMS_H_ */ +#endif /* CMPARAMS_H */ -/** - * @} - */ +/** @} */ diff --git a/os/hal/boards/EXP430FR5969/board.c b/os/hal/boards/EXP430FR5969/board.c index ac48ba0..0643cce 100644 --- a/os/hal/boards/EXP430FR5969/board.c +++ b/os/hal/boards/EXP430FR5969/board.c @@ -25,11 +25,11 @@ const PALConfig pal_default_config =
{
{VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0,
- VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE},
+ VAL_IOPORT1_SEL1},
{VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0,
- VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE},
+ VAL_IOPORT2_SEL1},
{VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0,
- VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE}
+ VAL_IOPORT0_SEL1}
}; /* Set UART TX pin correctly */
#endif /* HAL_USE_PAL */
diff --git a/os/hal/boards/EXP430FR5969/board.h b/os/hal/boards/EXP430FR5969/board.h index 97103d3..3abe1cc 100644 --- a/os/hal/boards/EXP430FR5969/board.h +++ b/os/hal/boards/EXP430FR5969/board.h @@ -65,8 +65,6 @@ #define VAL_IOPORT1_REN 0xFCFE
#define VAL_IOPORT1_SEL0 0x0000
#define VAL_IOPORT1_SEL1 0x0300
-#define VAL_IOPORT1_IES 0x0000
-#define VAL_IOPORT1_IE 0x0000
/*
* Port B setup:
@@ -93,8 +91,6 @@ #define VAL_IOPORT2_REN 0xBDFF
#define VAL_IOPORT2_SEL0 0x0000
#define VAL_IOPORT2_SEL1 0x0000
-#define VAL_IOPORT2_IES 0x0000
-#define VAL_IOPORT2_IE 0x0000
/*
* Port J setup:
@@ -113,8 +109,6 @@ #define VAL_IOPORT0_REN 0x00CF
#define VAL_IOPORT0_SEL0 0x0030
#define VAL_IOPORT0_SEL1 0x0000
-#define VAL_IOPORT0_IES 0x0000
-#define VAL_IOPORT0_IE 0x0000
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
diff --git a/os/hal/boards/EXP430FR6989/board.c b/os/hal/boards/EXP430FR6989/board.c index a6836cf..475a2ea 100644 --- a/os/hal/boards/EXP430FR6989/board.c +++ b/os/hal/boards/EXP430FR6989/board.c @@ -25,17 +25,17 @@ const PALConfig pal_default_config =
{
{VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0,
- VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE},
+ VAL_IOPORT1_SEL1},
{VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0,
- VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE},
+ VAL_IOPORT2_SEL1},
{VAL_IOPORT3_OUT, VAL_IOPORT3_DIR, VAL_IOPORT3_REN, VAL_IOPORT3_SEL0,
- VAL_IOPORT3_SEL1, VAL_IOPORT3_IES, VAL_IOPORT3_IE},
+ VAL_IOPORT3_SEL1},
{VAL_IOPORT4_OUT, VAL_IOPORT4_DIR, VAL_IOPORT4_REN, VAL_IOPORT4_SEL0,
- VAL_IOPORT4_SEL1, VAL_IOPORT4_IES, VAL_IOPORT4_IE},
+ VAL_IOPORT4_SEL1},
{VAL_IOPORT5_OUT, VAL_IOPORT5_DIR, VAL_IOPORT5_REN, VAL_IOPORT5_SEL0,
- VAL_IOPORT5_SEL1, VAL_IOPORT5_IES, VAL_IOPORT5_IE},
+ VAL_IOPORT5_SEL1},
{VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0,
- VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE}
+ VAL_IOPORT0_SEL1}
}; /* Set UART TX pin correctly */
#endif /* HAL_USE_PAL */
diff --git a/os/hal/boards/EXP430FR6989/board.h b/os/hal/boards/EXP430FR6989/board.h index 83b8fbb..d5afe29 100644 --- a/os/hal/boards/EXP430FR6989/board.h +++ b/os/hal/boards/EXP430FR6989/board.h @@ -69,8 +69,6 @@ #define VAL_IOPORT1_REN 0xFFFE
#define VAL_IOPORT1_SEL0 0x0000
#define VAL_IOPORT1_SEL1 0x0000
-#define VAL_IOPORT1_IES 0x0006
-#define VAL_IOPORT1_IE 0x0006
/*
* Port B setup:
@@ -97,8 +95,6 @@ #define VAL_IOPORT2_REN 0xFFCF
#define VAL_IOPORT2_SEL0 0x0030
#define VAL_IOPORT2_SEL1 0x0000
-#define VAL_IOPORT2_IES 0x0000
-#define VAL_IOPORT2_IE 0x0000
/*
* Port C setup:
@@ -125,8 +121,6 @@ #define VAL_IOPORT3_REN 0xFFFF
#define VAL_IOPORT3_SEL0 0x0000
#define VAL_IOPORT3_SEL1 0x0000
-#define VAL_IOPORT3_IES 0x0000
-#define VAL_IOPORT3_IE 0x0000
/*
* Port D setup:
@@ -153,11 +147,9 @@ #define VAL_IOPORT4_REN 0xFFFF
#define VAL_IOPORT4_SEL0 0x0000
#define VAL_IOPORT4_SEL1 0x0000
-#define VAL_IOPORT4_IES 0x0000
-#define VAL_IOPORT4_IE 0x0000
/*
- * Port D setup:
+ * Port E setup:
*
* P9.0 - BoosterPack BP27 (input pullup)
* P9.1 - BoosterPack BP28 (input pullup)
@@ -181,8 +173,6 @@ #define VAL_IOPORT5_REN 0xFF7F
#define VAL_IOPORT5_SEL0 0x0000
#define VAL_IOPORT5_SEL1 0x0000
-#define VAL_IOPORT5_IES 0x0000
-#define VAL_IOPORT5_IE 0x0000
/*
* Port J setup:
@@ -201,8 +191,6 @@ #define VAL_IOPORT0_REN 0x00CF
#define VAL_IOPORT0_SEL0 0x0030
#define VAL_IOPORT0_SEL1 0x0000
-#define VAL_IOPORT0_IES 0x0000
-#define VAL_IOPORT0_IE 0x0000
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h index 05aeceb..0788eb7 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h @@ -587,19 +587,14 @@ PIN_OSPEED_100M(GPIOD_MEM_D0) | \ PIN_OSPEED_100M(GPIOD_MEM_D1)) -#if STM32_NAND_USE_EXT_INT -#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) -#else -#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) -#endif #define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_MEM_D2) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D3) | \ PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_OE) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_WE) | \ - NAND_RB_NWAIT_PUPDR(GPIOD_NAND_RB_NWAIT) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \ + PIN_PUPDR_FLOATING(GPIOD_NAND_RB_NWAIT) |\ + PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D13) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D14) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D15) | \ @@ -893,21 +888,16 @@ PIN_OSPEED_100M(GPIOG_PIN14) | \ PIN_OSPEED_100M(GPIOG_PIN15)) -#if STM32_NAND_USE_EXT_INT -#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) -#else -#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) -#endif #define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_MEM_A10) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A11) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A12) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A13) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A14) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A15) | \ - NAND_RB1_PUPDR(GPIOG_NAND_RB1) | \ + PIN_PUPDR_PULLUP(GPIOG_NAND_RB1) | \ PIN_PUPDR_FLOATING(GPIOG_NAND_RB2) | \ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \ + PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ PIN_PUPDR_FLOATING(GPIOG_SRAM_CS1) | \ diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h index 367dce1..a59235a 100644 --- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h +++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef _BOARD_H_ -#define _BOARD_H_ +#ifndef BOARD_H +#define BOARD_H /* * Setup for Texas Instruments TM4C123G Launchpad Board. @@ -28,59 +28,9 @@ #define BOARD_NAME "Texas Instruments TM4C123G Launchpad" /* - * MCU type + * MCU type as defined in the TI header. */ -//#define TM4C1230C3PM -//#define TM4C1230D5PM -//#define TM4C1230E6PM -//#define TM4C1230H6PM -//#define TM4C1231C3PM -//#define TM4C1231D5PM -//#define TM4C1231D5PZ -//#define TM4C1231E6PM -//#define TM4C1231E6PZ -//#define TM4C1231H6PGE -//#define TM4C1231H6PM -//#define TM4C1231H6PZ -//#define TM4C1232C3PM -//#define TM4C1232D5PM -//#define TM4C1232E6PM -//#define TM4C1232H6PM -//#define TM4C1233C3PM -//#define TM4C1233D5PM -//#define TM4C1233D5PZ -//#define TM4C1233E6PM -//#define TM4C1233E6PZ -//#define TM4C1233H6PGE -//#define TM4C1233H6PM -//#define TM4C1233H6PZ -//#define TM4C1236D5PM -//#define TM4C1236E6PM -//#define TM4C1236H6PM -//#define TM4C1237D5PM -//#define TM4C1237D5PZ -//#define TM4C1237E6PM -//#define TM4C1237E6PZ -//#define TM4C1237H6PGE -//#define TM4C1237H6PM -//#define TM4C1237H6PZ -//#define TM4C123AE6PM -//#define TM4C123AH6PM -//#define TM4C123BE6PM -//#define TM4C123BE6PZ -//#define TM4C123BH6PGE -//#define TM4C123BH6PM -//#define TM4C123BH6PZ -//#define TM4C123BH6ZRB -//#define TM4C123FE6PM -//#define TM4C123FH6PM -//#define TM4C123GE6PM -//#define TM4C123GE6PZ -//#define TM4C123GH6PGE -#define TM4C123GH6PM -//#define TM4C123GH6PZ -//#define TM4C123GH6ZRB -//#define TM4C123GH5ZXR +#define PART_TM4C123GH6PM /* * Board oscillators-related settings. @@ -940,4 +890,4 @@ extern "C" { #endif #endif /* _FROM_ASM_ */ -#endif /* _BOARD_H_ */ +#endif /* BOARD_H */ diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h index 08bb36f..9012f7c 100644 --- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h +++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef _BOARD_H_ -#define _BOARD_H_ +#ifndef BOARD_H +#define BOARD_H /* * Setup for Texas Instruments TM4C1294 Launchpad Board. @@ -36,28 +36,9 @@ //#define BOARD_PHY_RMII /* - * MCU type + * MCU type as defined in the TI header. */ -//#define TM4C1290NCPDT -//#define TM4C1290NCZAD -//#define TM4C1292NCPDT -//#define TM4C1292NCZAD -//#define TM4C1294KCPDT -#define TM4C1294NCPDT -//#define TM4C1294NCZAD -//#define TM4C1297NCZAD -//#define TM4C1299KCZAD -//#define TM4C1299NCZAD -//#define TM4C129CNCPDT -//#define TM4C129CNCZAD -//#define TM4C129DNCPDT -//#define TM4C129DNCZAD -//#define TM4C129EKCPDT -//#define TM4C129ENCPDT -//#define TM4C129ENCZAD -//#define TM4C129LNCZAD -//#define TM4C129XKCZAD -//#define TM4C129XNCZAD +#define PART_TM4C1294NCPDT /* * Board oscillators-related settings. @@ -426,4 +407,4 @@ extern "C" { #endif #endif /* _FROM_ASM_ */ -#endif /* _BOARD_H_ */ +#endif /* BOARD_H */ diff --git a/os/hal/hal.mk b/os/hal/hal.mk index ce74620..f05ddbc 100644 --- a/os/hal/hal.mk +++ b/os/hal/hal.mk @@ -18,6 +18,7 @@ HALSRC += ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_eeprom.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_timcap.c \
${CHIBIOS_CONTRIB}/os/hal/src/hal_qei.c \
- ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_hid.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_usb_msd.c
HALINC += ${CHIBIOS_CONTRIB}/os/hal/include
diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index 1518c7e..430df7c 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -67,6 +67,10 @@ #define HAL_USE_USB_HID FALSE
#endif
+#if !defined(HAL_USE_USB_MSD)
+#define HAL_USE_USB_MSD FALSE
+#endif
+
/* Abstract interfaces.*/
/* Shared headers.*/
@@ -84,6 +88,7 @@ #include "hal_crc.h"
#include "hal_eeprom.h"
#include "hal_usb_hid.h"
+#include "hal_usb_msd.h"
/*===========================================================================*/
/* Driver constants. */
diff --git a/os/hal/include/hal_crc.h b/os/hal/include/hal_crc.h index 8c4c895..d7ef10f 100644 --- a/os/hal/include/hal_crc.h +++ b/os/hal/include/hal_crc.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef _CRC_H_ -#define _CRC_H_ +#ifndef HAL_CRC_H_ +#define HAL_CRC_H_ #if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) @@ -153,6 +153,6 @@ extern "C" { #endif /* HAL_USE_CRC */ -#endif /* _CRC_H_ */ +#endif /* HAL_CRC_H_ */ /** @} */ diff --git a/os/hal/include/hal_ee24xx.h b/os/hal/include/hal_ee24xx.h index ab12fd1..00cdc95 100644 --- a/os/hal/include/hal_ee24xx.h +++ b/os/hal/include/hal_ee24xx.h @@ -4,8 +4,8 @@ The work is provided "as is" without warranty of any kind, neither express nor implied. */ -#ifndef EE24XX_H -#define EE24XX_H +#ifndef HAL_EE24XX_H +#define HAL_EE24XX_H #include "hal.h" @@ -61,4 +61,4 @@ typedef struct { #endif /* #if defined(EEPROM_USE_EE24XX) && EEPROM_USE_EE24XX */ -#endif // EE24XX_H +#endif // HAL_EE24XX_H diff --git a/os/hal/include/hal_ee25xx.h b/os/hal/include/hal_ee25xx.h index fc2ad6f..e520bd6 100644 --- a/os/hal/include/hal_ee25xx.h +++ b/os/hal/include/hal_ee25xx.h @@ -4,8 +4,8 @@ The work is provided "as is" without warranty of any kind, neither express nor implied. */ -#ifndef EE25XX_H -#define EE25XX_H +#ifndef HAL_EE25XX_H +#define HAL_EE25XX_H #include "hal.h" @@ -60,4 +60,4 @@ EepromFileStream *SPIEepromFileOpen(SPIEepromFileStream *efs, #endif /* #if defined(EEPROM_USE_EE25XX) && EEPROM_USE_EE25XX */ -#endif // EE25XX_H +#endif // HAL_EE25XX_H diff --git a/os/hal/include/hal_eeprom.h b/os/hal/include/hal_eeprom.h index cd05e14..6f53fb9 100644 --- a/os/hal/include/hal_eeprom.h +++ b/os/hal/include/hal_eeprom.h @@ -26,8 +26,8 @@ The work is provided "as is" without warranty of any kind, neither express nor implied. */ -#ifndef __EEPROM_H__ -#define __EEPROM_H__ +#ifndef HAL_EEPROM_H_ +#define HAL_EEPROM_H_ #include "ch.h" #include "hal.h" @@ -140,4 +140,4 @@ msg_t eepfs_get(void *ip); #include "hal_ee25xx.h" #endif /* #if defined(HAL_USE_EEPROM) && HAL_USE_EEPROM */ -#endif /* __EEPROM_H__ */ +#endif /* HAL_EEPROM_H_ */ diff --git a/os/hal/include/hal_eicu.h b/os/hal/include/hal_eicu.h index d4b0ed2..8b4b07d 100644 --- a/os/hal/include/hal_eicu.h +++ b/os/hal/include/hal_eicu.h @@ -22,8 +22,8 @@ 32-bit timers and timers with single capture/compare channels. */ -#ifndef _EICU_H_ -#define _EICU_H_ +#ifndef HAL_EICU_H_ +#define HAL_EICU_H_ #if (HAL_USE_EICU == TRUE) || defined(__DOXYGEN__) @@ -186,6 +186,6 @@ extern "C" { #endif /* HAL_USE_EICU */ -#endif /* _EICU_H_ */ +#endif /* HAL_EICU_H_ */ /** @} */ diff --git a/os/hal/include/hal_nand.h b/os/hal/include/hal_nand.h index d5a1c04..ace3e5d 100644 --- a/os/hal/include/hal_nand.h +++ b/os/hal/include/hal_nand.h @@ -15,15 +15,15 @@ */ /** - * @file nand.h + * @file hal_nand.h * @brief NAND Driver macros and structures. * * @addtogroup NAND * @{ */ -#ifndef _NAND_H_ -#define _NAND_H_ +#ifndef HAL_NAND_H_ +#define HAL_NAND_H_ #if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) diff --git a/os/hal/include/hal_onewire.h b/os/hal/include/hal_onewire.h index 9fb5be2..bbaf77b 100644 --- a/os/hal/include/hal_onewire.h +++ b/os/hal/include/hal_onewire.h @@ -15,15 +15,15 @@ */ /** - * @file onewire.h + * @file hal_onewire.h * @brief 1-wire Driver macros and structures. * * @addtogroup onewire * @{ */ -#ifndef _ONEWIRE_H_ -#define _ONEWIRE_H_ +#ifndef HAL_ONEWIRE_H_ +#define HAL_ONEWIRE_H_ #if (HAL_USE_ONEWIRE == TRUE) || defined(__DOXYGEN__) @@ -59,11 +59,13 @@ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ +#if ONEWIRE_SYNTH_SEARCH_TEST && !ONEWIRE_USE_SEARCH_ROM +#error "Synthetic search rom test needs ONEWIRE_USE_SEARCH_ROM" +#endif /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ - #if !HAL_USE_PWM #error "1-wire Driver requires HAL_USE_PWM" #endif @@ -328,7 +330,6 @@ extern onewireDriver OWD1; #ifdef __cplusplus extern "C" { #endif - void onewireInit(void); void onewireObjectInit(onewireDriver *owp); void onewireStart(onewireDriver *owp, const onewireConfig *config); void onewireStop(onewireDriver *owp); @@ -352,7 +353,7 @@ extern "C" { #endif /* HAL_USE_ONEWIRE */ -#endif /* _ONEWIRE_H_ */ +#endif /* HAL_ONEWIRE_H_ */ /** @} */ diff --git a/os/hal/include/hal_rng.h b/os/hal/include/hal_rng.h index 0e3c484..dc146c7 100644 --- a/os/hal/include/hal_rng.h +++ b/os/hal/include/hal_rng.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef _RNG_H_ -#define _RNG_H_ +#ifndef HAL_RNG_H_ +#define HAL_RNG_H_ #if (HAL_USE_RNG == TRUE) || defined(__DOXYGEN__) @@ -131,6 +131,6 @@ extern "C" { #endif /* HAL_USE_RNG */ -#endif /* _RNG_H_ */ +#endif /* HAL_RNG_H_ */ /** @} */ diff --git a/os/hal/include/hal_timcap.h b/os/hal/include/hal_timcap.h index bd43dd1..61c7fc5 100644 --- a/os/hal/include/hal_timcap.h +++ b/os/hal/include/hal_timcap.h @@ -19,15 +19,15 @@ */ /** - * @file timcap.h + * @file hal_timcap.h * @brief TIMCAP Driver macros and structures. * * @addtogroup TIMCAP * @{ */ -#ifndef _TIMCAP_H_ -#define _TIMCAP_H_ +#ifndef HAL_TIMCAP_H_ +#define HAL_TIMCAP_H_ #include "ch.h" #include "hal.h" @@ -201,6 +201,6 @@ extern "C" { #endif /* HAL_USE_TIMCAP */ -#endif /* _TIMCAP_H_ */ +#endif /* HAL_TIMCAP_H_ */ /** @} */ diff --git a/os/hal/include/hal_usb_msd.h b/os/hal/include/hal_usb_msd.h new file mode 100644 index 0000000..08241df --- /dev/null +++ b/os/hal/include/hal_usb_msd.h @@ -0,0 +1,192 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_usb_msd.h + * @brief USM mass storage device driver macros and structures. + * + * @addtogroup usb_msd + * @{ + */ + +#ifndef HAL_USB_MSD_H +#define HAL_USB_MSD_H + +#if (HAL_USE_USB_MSD == TRUE) || defined(__DOXYGEN__) + +#include "lib_scsi.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define USB_MSD_DATA_EP 0x01 +#define USB_MSD_EP_SIZE 0x40 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !HAL_USE_USB +#error "Mass storage Driver requires HAL_USE_USB" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an USB mass storage driver. + */ +typedef struct USBMassStorageDriver USBMassStorageDriver; + +/** + * @brief Type of a driver state machine possible states. + */ +typedef enum { + USB_MSD_UNINIT = 0, + USB_MSD_STOP, + USB_MSD_READY, +} usbmsdstate_t; + +/** + * @brief Represents command block wrapper structure. + * @details See USB Mass Storage Class Specification. + */ +typedef struct PACKED_VAR { + uint32_t signature; + uint32_t tag; + uint32_t data_len; + uint8_t flags; + uint8_t lun; + uint8_t cmd_len; + uint8_t cmd_data[16]; +} msd_cbw_t; + +/** + * @brief Represents command status wrapper structure. + * @details See USB Mass Storage Class Specification. + */ +typedef struct PACKED_VAR { + uint32_t signature; + uint32_t tag; + uint32_t data_residue; + uint8_t status; +} msd_csw_t; + +/** + * @brief Transport handler passed to SCSI layer. + */ +typedef struct { + /** + * @brief Pointer to the @p USBDriver object. + */ + USBDriver *usbp; + /** + * @brief USB endpoint number. + */ + usbep_t ep; +} usb_scsi_transport_handler_t; + + +/** + * @brief Structure representing an USB mass storage driver. + */ +struct USBMassStorageDriver { + /** + * @brief Pointer to the @p USBDriver object. + */ + USBDriver *usbp; + /** + * @brief Driver state. + */ + usbmsdstate_t state; + /** + * @brief CBW structure. + */ + msd_cbw_t cbw; + /** + * @brief CSW structure. + */ + msd_csw_t csw; + /** + * @brief Thread working area. + */ + THD_WORKING_AREA( waMSDWorker, 512); + /** + * @brief Worker thread handler. + */ + thread_reference_t worker; + /** + * @brief SCSI target driver structure. + */ + SCSITarget scsi_target; + /** + * @brief SCSI target configuration structure. + */ + SCSITargetConfig scsi_config; + /** + * @brief SCSI transport structure. + */ + SCSITransport scsi_transport; + /** + * @brief SCSI over USB transport handler structure. + */ + usb_scsi_transport_handler_t usb_scsi_transport_handler; +}; + + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern USBMassStorageDriver USBMSD1; + +#ifdef __cplusplus +extern "C" { +#endif + void msdObjectInit(USBMassStorageDriver *msdp); + void msdStart(USBMassStorageDriver *msdp, USBDriver *usbp, + BaseBlockDevice *blkdev, uint8_t *blkbuf, + const scsi_inquiry_response_t *scsi_inquiry_response); + void msdStop(USBMassStorageDriver *msdp); + bool msd_request_hook(USBDriver *usbp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB_MSD */ + +#endif /* HAL_USB_MSD_H */ + +/** @} */ + + + + + + + + + diff --git a/os/hal/include/hal_usbh.h b/os/hal/include/hal_usbh.h index 5fd0047..63be93e 100644 --- a/os/hal/include/hal_usbh.h +++ b/os/hal/include/hal_usbh.h @@ -15,8 +15,8 @@ limitations under the License. */ -#ifndef USBH_H_ -#define USBH_H_ +#ifndef HAL_USBH_H_ +#define HAL_USBH_H_ #include "hal.h" @@ -433,4 +433,4 @@ struct usbh_baseclassdriver { #endif -#endif /* USBH_H_ */ +#endif /* HAL_USBH_H_ */ diff --git a/os/hal/ports/MSP430X/hal_adc_lld.c b/os/hal/ports/MSP430X/hal_adc_lld.c new file mode 100644 index 0000000..42d3cbe --- /dev/null +++ b/os/hal/ports/MSP430X/hal_adc_lld.c @@ -0,0 +1,354 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_adc_lld.c
+ * @brief MSP430X ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC1 driver identifier.
+ */
+#if (MSP430X_ADC_USE_ADC1 == TRUE) || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void restart_dma(ADCDriver * adcp) {
+ /* TODO timeouts? */
+ /* Restart DMA transfer */
+ if (adcp->dma.registers == NULL) {
+ /* Acquire a DMA stream because dmaTransfer can be called from ISRs */
+ osalSysLockFromISR();
+ dmaAcquireI(&(adcp->dma), adcp->dma.index);
+ osalSysUnlockFromISR();
+ dmaTransfer(&(adcp->dma), &(adcp->req));
+ }
+ else {
+ dmaTransfer(&(adcp->dma), &(adcp->req));
+ }
+}
+
+static void dma_callback(void * args) {
+ ADCDriver * adcp = (ADCDriver *)args;
+
+ if (adcp->grpp == NULL)
+ return;
+
+ adcp->count++;
+
+ if (adcp->count == adcp->depth / 2) {
+ /* half-full interrupt */
+ _adc_isr_half_code(adcp);
+ }
+
+ if (adcp->count == adcp->depth) {
+ /* full interrupt */
+
+ /* adc_lld_stop_conversion is called automatically here if needed */
+ _adc_isr_full_code(adcp);
+ /* after isr_full, adcp->grpp is only non-NULL if it's a circular group */
+ if (adcp->grpp) {
+ /* Reset the buffer pointer */
+ adcp->req.dest_addr = adcp->samples;
+
+ restart_dma(adcp);
+
+ /* Reset the count */
+ adcp->count = 0;
+
+ /* Start next sequence */
+ adcp->regs->ctl[0] |= ADC12SC;
+ }
+ }
+ else {
+ /* Advance the buffer pointer */
+ adcp->req.dest_addr = adcp->samples + (adcp->req.size * adcp->count);
+
+ restart_dma(adcp);
+
+ /* Start next sequence */
+ adcp->regs->ctl[0] |= ADC12SC;
+ }
+}
+
+static void populate_tlv(ADCDriver * adcp) {
+ uint8_t * tlv_addr = (uint8_t *)TLV_START;
+
+ while (*tlv_addr != TLV_TAGEND && tlv_addr < (uint8_t *)TLV_END) {
+ if (*tlv_addr == TLV_ADC12CAL) {
+ adcp->adc_cal = (msp430x_adc_cal_t *)(tlv_addr + 2);
+ }
+ else if (*tlv_addr == TLV_REFCAL) {
+ adcp->ref_cal = (msp430x_ref_cal_t *)(tlv_addr + 2);
+ }
+ tlv_addr += (tlv_addr[1] + 2);
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+PORT_IRQ_HANDLER(ADC12_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ switch (__even_in_range(ADC12IV, ADC12IV_ADC12TOVIFG)) {
+
+ case ADC12IV_ADC12OVIFG: {
+ if (ADCD1.grpp == NULL)
+ break;
+ _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
+ break;
+ }
+ case ADC12IV_ADC12TOVIFG: {
+ if (ADCD1.grpp == NULL)
+ break;
+ _adc_isr_error_code(&ADCD1, ADC_ERR_AWD);
+ break;
+ }
+ default:
+ osalDbgAssert(false, "unhandled ADC exception");
+ _adc_isr_error_code(&ADCD1, ADC_ERR_UNKNOWN);
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if MSP430X_ADC_USE_ADC1 == TRUE
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD1);
+ ADCD1.regs = (msp430x_adc_reg_t *)(&ADC12CTL0);
+ populate_tlv(&ADCD1);
+#endif
+}
+
+/**
+ * @brief Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver * adcp) {
+
+ if (adcp->state == ADC_STOP) {
+ /* Enables the peripheral.*/
+ adcp->regs->ctl[0] = ADC12ON | ADC12MSC;
+ adcp->regs->ctl[1] =
+ MSP430X_ADC1_PDIV | MSP430X_ADC1_DIV | MSP430X_ADC1_SSEL | ADC12SHP;
+ adcp->regs->ctl[3] = ADC12ICH3MAP | ADC12ICH2MAP | ADC12ICH1MAP |
+ ADC12ICH0MAP | ADC12TCMAP | ADC12BATMAP;
+ adcp->regs->ier[2] = ADC12TOVIE | ADC12OVIE;
+ adcp->req.trigger = DMA_TRIGGER_MNEM(ADC12IFG);
+#if MSP430X_ADC_COMPACT_SAMPLES == TRUE
+ adcp->req.data_mode = MSP430X_DMA_SRCWORD | MSP430X_DMA_DSTBYTE;
+#else
+ adcp->req.data_mode = MSP430X_DMA_SRCWORD | MSP430X_DMA_DSTWORD;
+#endif
+ adcp->req.addr_mode = MSP430X_DMA_SRCINCR | MSP430X_DMA_DSTINCR;
+ adcp->req.transfer_mode = MSP430X_DMA_SINGLE;
+ adcp->req.callback.callback = dma_callback;
+ adcp->req.callback.args = adcp;
+
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ bool b;
+ if (adcp->config->dma_index < MSP430X_DMA_CHANNELS) {
+ b = dmaAcquireI(&adcp->dma, adcp->config->dma_index);
+ osalDbgAssert(!b, "stream already allocated");
+ }
+ else {
+#endif
+ adcp->dma.registers = NULL;
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ }
+#endif
+ }
+ /* Configures the peripheral.*/
+}
+
+/**
+ * @brief Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver * adcp) {
+
+ if (adcp->state == ADC_READY) {
+/* Resets the peripheral.*/
+
+/* Disables the peripheral.*/
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ if (adcp->config->dma_index < MSP430X_DMA_CHANNELS) {
+ dmaRelease(&(adcp->dma));
+ }
+#endif
+ adcp->regs->ctl[0] = 0;
+ }
+}
+
+/**
+ * @brief Starts an ADC conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver * adcp) {
+
+ /* always use sequential transfer mode - this is fine */
+ adcp->regs->ctl[1] |= ADC12CONSEQ0;
+
+ /* set resolution */
+ adcp->regs->ctl[2] |= adcp->grpp->res;
+ /* start from MEM0 */
+ adcp->regs->ctl[3] &= ~(ADC12CSTARTADD_31);
+
+ /* Configure voltage reference */
+ while (REFCTL0 & REFGENBUSY)
+ ;
+ REFCTL0 = adcp->grpp->vref_src;
+
+ for (int i = 0; i < adcp->grpp->num_channels; i++) {
+ osalDbgAssert(adcp->grpp->channels[i] < 32, "invalid channel number");
+ adcp->regs->mctl[i] = adcp->grpp->ref | adcp->grpp->channels[i];
+ }
+
+ adcp->regs->mctl[adcp->grpp->num_channels - 1] |= ADC12EOS;
+
+ adcp->req.source_addr = adcp->regs->mem;
+ adcp->req.dest_addr = adcp->samples;
+ adcp->req.size = adcp->grpp->num_channels;
+ adcp->count = 0;
+
+/* TODO timeouts? */
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ if (adcp->config->dma_index >= MSP430X_DMA_CHANNELS) {
+ adcp->dma.index = dmaRequestS(&(adcp->req), TIME_INFINITE);
+ }
+ else {
+ dmaTransfer(&(adcp->dma), &(adcp->req));
+ }
+#else
+ adcp->dma.index = dmaRequestS(&(adcp->req), TIME_INFINITE);
+#endif
+
+ adcp->regs->ctl[0] |= adcp->grpp->rate | ADC12MSC | ADC12ENC | ADC12SC;
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver * adcp) {
+
+ /* TODO stop DMA transfers here */
+ adcp->regs->ctl[0] &= ~(ADC12ENC | ADC12SC);
+
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ if (adcp->config->dma_index >= MSP430X_DMA_CHANNELS) {
+#endif
+ if (adcp->dma.registers != NULL) {
+ dmaRelease(&(adcp->dma));
+ adcp->dma.registers = NULL;
+ }
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE
+ }
+#endif
+}
+
+adcsample_t adcMSP430XAdjustResult(ADCConversionGroup * grpp,
+ adcsample_t sample) {
+ uint32_t tmp;
+ uint16_t fact;
+ if (grpp->ref == MSP430X_ADC_VSS_VREF_BUF ||
+ grpp->ref == MSP430X_ADC_VEREF_P_VREF_BUF ||
+ grpp->ref == MSP430X_ADC_VREF_BUF_VCC ||
+ grpp->ref == MSP430X_ADC_VREF_BUF_VEREF_P ||
+ grpp->ref == MSP430X_ADC_VEREF_N_VREF_BUF) {
+ /* Retrieve proper reference correction factor from TLV */
+ fact = (&(ADCD1.ref_cal->CAL_ADC_12VREF_FACTOR))[grpp->vref_src >> 4];
+ /* Calculate corrected value */
+ tmp = (uint32_t)(sample << 1) * (uint32_t)fact;
+ sample = tmp >> 16;
+ }
+
+ /* Gain correction */
+ fact = ADCD1.adc_cal->CAL_ADC_GAIN_FACTOR;
+ tmp = (uint32_t)(sample << 1) * (uint32_t)fact;
+ sample = tmp >> 16;
+
+ /* Offset correction */
+ sample += ADCD1.adc_cal->CAL_ADC_OFFSET;
+
+ return sample;
+}
+
+adcsample_t adcMSP430XAdjustTemp(ADCConversionGroup * grpp,
+ adcsample_t sample) {
+ uint16_t t30;
+ uint16_t t85;
+
+ /* Retrieve proper T = 30 correction value from TLV */
+ t30 = (&(ADCD1.adc_cal->CAL_ADC_12T30))[grpp->vref_src >> 3];
+ /* Retrieve proper T = 85 correction value from TLV */
+ t85 = (&(ADCD1.adc_cal->CAL_ADC_12T30))[(grpp->vref_src >> 3) + 1];
+
+ return ((((int32_t)sample - (int32_t)t30) * (85 - 30)) / (t85 - t30)) + 30;
+}
+
+#endif /* HAL_USE_ADC == TRUE */
+
+/** @} */
diff --git a/os/hal/ports/MSP430X/hal_adc_lld.h b/os/hal/ports/MSP430X/hal_adc_lld.h new file mode 100644 index 0000000..1cca36b --- /dev/null +++ b/os/hal/ports/MSP430X/hal_adc_lld.h @@ -0,0 +1,516 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_adc_lld.h
+ * @brief MSP430X ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef HAL_ADC_LLD_H
+#define HAL_ADC_LLD_H
+
+#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Sampling rates
+ * @{
+ */
+typedef enum {
+ MSP430X_ADC_SHT_4 = 0x0000,
+ MSP430X_ADC_SHT_8 = 0x1100,
+ MSP430X_ADC_SHT_16 = 0x2200,
+ MSP430X_ADC_SHT_32 = 0x3300,
+ MSP430X_ADC_SHT_64 = 0x4400,
+ MSP430X_ADC_SHT_96 = 0x5500,
+ MSP430X_ADC_SHT_128 = 0x6600,
+ MSP430X_ADC_SHT_192 = 0x7700,
+ MSP430X_ADC_SHT_256 = 0x8800,
+ MSP430X_ADC_SHT_384 = 0x9900,
+ MSP430X_ADC_SHT_512 = 0xAA00
+} MSP430XADCSampleRates;
+/** @} */
+
+/**
+ * @name Resolution
+ * @{
+ */
+typedef enum {
+ MSP430X_ADC_RES_8BIT = 0x0000,
+ MSP430X_ADC_RES_10BIT = 0x0010,
+ MSP430X_ADC_RES_12BIT = 0x0020
+} MSP430XADCResolution;
+/** @} */
+
+/**
+ * @name References
+ * @{
+ */
+typedef enum {
+ MSP430X_ADC_VSS_VCC = 0x0000,
+ MSP430X_ADC_VSS_VREF_BUF = 0x0100,
+ MSP430X_ADC_VSS_VEREF_N = 0x0200,
+ MSP430X_ADC_VSS_VEREF_P_BUF = 0x0300,
+ MSP430X_ADC_VSS_VEREF_P = 0x0400,
+ MSP430X_ADC_VEREF_P_BUF_VCC = 0x0500,
+ MSP430X_ADC_VEREF_P_VCC = 0x0600,
+ MSP430X_ADC_VEREF_P_VREF_BUF = 0x0700,
+ MSP430X_ADC_VREF_BUF_VCC = 0x0900,
+ MSP430X_ADC_VREF_BUF_VEREF_P = 0x0B00,
+ MSP430X_ADC_VEREF_N_VCC = 0x0C00,
+ MSP430X_ADC_VEREF_N_VREF_BUF = 0x0D00,
+ MSP430X_ADC_VEREF_N_VEREF_P = 0x0E00,
+ MSP430X_ADC_VEREF_N_VEREF_P_BUF = 0x0F00
+} MSP430XADCReferences;
+
+typedef enum {
+ MSP430X_REF_1V2 = 0x0000,
+ MSP430X_REF_2V0 = 0x0010,
+ MSP430X_REF_2V5 = 0x0020,
+ MSP430X_REF_1V2_EXT = 0x0002,
+ MSP430X_REF_2V0_EXT = 0x0012,
+ MSP430X_REF_2V5_EXT = 0x0022
+} MSP430XREFSources;
+
+#define MSP430X_REF_NONE MSP430X_REF_1V2
+
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name MSP430X configuration options
+ * @{
+ */
+/**
+ * @brief Stores ADC samples in an 8 bit integer.
+ * @note 10 and 12 bit sampling modes must not be used when this option is
+ * enabled.
+ */
+#if !defined(MSP430X_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)
+#define MSP430X_ADC_COMPACT_SAMPLES FALSE
+#endif
+
+/**
+ * @brief ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(MSP430X_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define MSP430X_ADC_USE_ADC1 TRUE
+#endif
+
+/**]
+ * @brief Exclusive DMA enable switch.
+ * @details If set to @p TRUE the support for exclusive DMA is included.
+ * @note This increases the size of the compiled executable somewhat.
+ * @note The default is @p FALSE.
+ */
+#if !defined(MSP430X_ADC_EXCLUSIVE_DMA) || defined(__DOXYGEN__)
+#define MSP430X_ADC_EXCLUSIVE_DMA FALSE
+#endif
+
+#if MSP430X_ADC_USE_ADC1
+
+/**
+ * @brief ADC1 clock source configuration
+ */
+#if !defined(MSP430X_ADC1_CLK_SRC)
+#define MSP430X_ADC1_CLK_SRC MSP430X_MODCLK
+#endif
+
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if MSP430X_ADC_USE_ADC1
+
+#if !defined(__MSP430_HAS_ADC12_B__)
+#error "No ADC present or ADC version not supported"
+#endif
+
+#if (MSP430X_ADC1_CLK_SRC == MSP430X_MODCLK)
+#define MSP430X_ADC1_CLK_FREQ MSP430X_MODCLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_0
+#elif (MSP430X_ADC1_CLK_SRC == MSP430X_ACLK)
+#define MSP430X_ADC1_CLK_FREQ MSP430X_ACLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_1
+#elif (MSP430X_ADC1_CLK_SRC == MSP430X_MCLK)
+#define MSP$30X_ADC1_CLK_FREQ MSP430X_MCLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_2
+#elif (MSP430X_ADC1_CLK_SRC == MSP430SMCLK)
+#define MSP430X_ADC1_CLK_FREQ MSP430X_SMCLK_FREQ
+#define MSP430X_ADC1_SSEL ADC12SSEL_3
+#else
+#error "Invalid ADC1 clock source requested!"
+#endif
+
+#if !defined(MSP430X_ADC1_FREQ)
+#warning "ADC clock frequency not defined - assuming 1 for all dividers"
+#define MSP430X_ADC1_DIV_CALC(x) (x == 1)
+#else
+#define MSP430X_ADC1_DIV_CALC(x) \
+ ((MSP430X_ADC1_CLK_FREQ / x) == MSP430X_ADC1_FREQ)
+#endif
+
+/**
+ * @brief ADC1 prescaler calculations
+ */
+#if MSP430X_ADC1_DIV_CALC(1)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(2)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_1
+#elif MSP430X_ADC1_DIV_CALC(3)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(4)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(5)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(6)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_5
+#elif MSP430X_ADC1_DIV_CALC(7)
+#define MSP430X_ADC1_PDIV ADC12PDIV__1
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(8)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(12)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(16)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_3
+#elif MSP430X_ADC1_DIV_CALC(20)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(24)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_5
+#elif MSP430X_ADC1_DIV_CALC(28)
+#define MSP430X_ADC1_PDIV ADC12PDIV__4
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(32)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(64)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_0
+#elif MSP430X_ADC1_DIV_CALC(96)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(128)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_1
+#elif MSP430X_ADC1_DIV_CALC(160)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(192)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_2
+#elif MSP430X_ADC1_DIV_CALC(224)
+#define MSP430X_ADC1_PDIV ADC12PDIV__32
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(256)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_3
+#elif MSP430X_ADC1_DIV_CALC(320)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_4
+#elif MSP430X_ADC1_DIV_CALC(384)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_5
+#elif MSP430X_ADC1_DIV_CALC(448)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_6
+#elif MSP430X_ADC1_DIV_CALC(512)
+#define MSP430X_ADC1_PDIV ADC12PDIV__64
+#define MSP430X_ADC1_DIV ADC12DIV_7
+#else
+#error "MSP430X_ADC1_FREQ not achievable with MSP430X_ADC1_CLK_SRC"
+#endif
+
+#endif /* MSP430X_ADC_USE_ADC1 */
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC sample data type.
+ */
+#if !MSP430X_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__)
+typedef uint16_t adcsample_t;
+#else
+typedef uint8_t adcsample_t;
+#endif
+
+/**
+ * @brief Channels number in a conversion group.
+ */
+typedef uint8_t adc_channels_num_t;
+
+/**
+ * @brief Possible ADC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ ADC_ERR_UNKNOWN = 0, /**< Unknown error has occurred */
+ ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
+ ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */
+} adcerror_t;
+
+/**
+ * @brief Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief ADC notification callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] buffer pointer to the most recent samples data
+ * @param[in] n number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver * adcp, adcsample_t * buffer, size_t n);
+
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver * adcp, adcerror_t err);
+
+/**
+ * @brief MSP430X ADC register structure.
+ */
+typedef struct {
+ uint16_t ctl[4];
+ uint16_t lo;
+ uint16_t hi;
+ uint16_t ifgr[3];
+ uint16_t ier[3];
+ uint16_t iv;
+ uint16_t padding[3];
+ uint16_t mctl[32];
+ uint16_t mem[32];
+} msp430x_adc_reg_t;
+
+/**
+ * @brief MSP430X ADC calibration structure.
+ */
+typedef struct {
+ uint16_t CAL_ADC_GAIN_FACTOR;
+ uint16_t CAL_ADC_OFFSET;
+ uint16_t CAL_ADC_12T30;
+ uint16_t CAL_ADC_12T85;
+ uint16_t CAL_ADC_20T30;
+ uint16_t CAL_ADC_20T85;
+ uint16_t CAL_ADC_25T30;
+ uint16_t CAL_ADC_25T85;
+} msp430x_adc_cal_t;
+
+/**
+ * @brief MSP430X REF calibration structure.
+ */
+typedef struct {
+ uint16_t CAL_ADC_12VREF_FACTOR;
+ uint16_t CAL_ADC_20VREF_FACTOR;
+ uint16_t CAL_ADC_25VREF_FACTOR;
+} msp430x_ref_cal_t;
+
+/**
+ * @brief Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ * operation.
+ * @note The use of this configuration structure requires knowledge of
+ * MSP430X ADC cell registers interface, please refer to the MSP430X
+ * reference manual for details.
+ */
+typedef struct {
+ /**
+ * @brief Enables the circular buffer mode for the group.
+ */
+ bool circular;
+ /**
+ * @brief Number of the analog channels belonging to the conversion group.
+ */
+ adc_channels_num_t num_channels;
+ /**
+ * @brief Callback function associated to the group or @p NULL.
+ */
+ adccallback_t end_cb;
+ /**
+ * @brief Error callback or @p NULL.
+ */
+ adcerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Sequence of analog channels belonging to the conversion group.
+ * @note Only the first num_channels are valid.
+ */
+ uint8_t channels[32];
+ /**
+ * @brief Sample resolution
+ */
+ MSP430XADCResolution res;
+ /**
+ * @brief Sampling time in clock cycles
+ */
+ MSP430XADCSampleRates rate;
+ /**
+ * @brief Voltage references to use
+ */
+ MSP430XADCReferences ref;
+ /**
+ * @brief VREF source
+ */
+ MSP430XREFSources vref_src;
+} ADCConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+#if MSP430X_ADC_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)
+ /**
+ * @brief The index of the DMA channel.
+ * @note This may be >MSP430X_DMA_CHANNELS to indicate that exclusive DMA
+ * is not used.
+ */
+ uint8_t dma_index;
+#endif
+} ADCConfig;
+
+/**
+ * @brief Structure representing an ADC driver.
+ */
+struct ADCDriver {
+ /**
+ * @brief Driver state.
+ */
+ adcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const ADCConfig * config;
+ /**
+ * @brief Current samples buffer pointer or @p NULL.
+ */
+ adcsample_t * samples;
+ /**
+ * @brief Current samples buffer depth or @p 0.
+ */
+ size_t depth;
+ /**
+ * @brief Current conversion group pointer or @p NULL.
+ */
+ const ADCConversionGroup * grpp;
+#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+#if (ADC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif
+#if defined(ADC_DRIVER_EXT_FIELDS)
+ ADC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Base address of ADC12_B registers
+ */
+ msp430x_adc_reg_t * regs;
+ /**
+ * @brief DMA request structure
+ */
+ msp430x_dma_req_t req;
+ /**
+ * @brief ADC calibration structure from TLV
+ */
+ msp430x_adc_cal_t * adc_cal;
+ /**
+ * @brief REF calibration structure from TLV
+ */
+ msp430x_ref_cal_t * ref_cal;
+ /**
+ * @brief Count of times DMA callback has been called
+ */
+ uint8_t count;
+ /**
+ * @brief DMA stream
+ */
+ msp430x_dma_ch_t dma;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if (MSP430X_ADC_USE_ADC1 == TRUE) && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void adc_lld_init(void);
+void adc_lld_start(ADCDriver * adcp);
+void adc_lld_stop(ADCDriver * adcp);
+void adc_lld_start_conversion(ADCDriver * adcp);
+void adc_lld_stop_conversion(ADCDriver * adcp);
+adcsample_t adcMSP430XAdjustResult(ADCConversionGroup * grpp,
+ adcsample_t sample);
+adcsample_t adcMSP430XAdjustTemp(ADCConversionGroup * grpp, adcsample_t sample);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC == TRUE */
+
+#endif /* HAL_ADC_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/MSP430X/hal_dma_lld.c b/os/hal/ports/MSP430X/hal_dma_lld.c index 43e1d6c..82bf39f 100644 --- a/os/hal/ports/MSP430X/hal_dma_lld.c +++ b/os/hal/ports/MSP430X/hal_dma_lld.c @@ -44,9 +44,8 @@ static msp430x_dma_ch_reg_t * const dma_channels = (msp430x_dma_ch_reg_t *)&DMA0CTL;
static msp430x_dma_cb_t callbacks[MSP430X_DMA_CHANNELS];
-#if CH_CFG_USE_SEMAPHORES
-static semaphore_t dma_lock;
-#endif
+static threads_queue_t dma_queue;
+static unsigned int queue_length;
/*===========================================================================*/
/* Driver local functions. */
@@ -88,9 +87,9 @@ PORT_IRQ_HANDLER(DMA_VECTOR) { index = (DMAIV >> 1) - 1;
if (index < MSP430X_DMA_CHANNELS) {
-#if CH_CFG_USE_SEMAPHORES
- chSemSignalI(&dma_lock);
-#endif
+ osalSysLockFromISR();
+ osalThreadDequeueNextI(&dma_queue, MSG_OK);
+ osalSysUnlockFromISR();
msp430x_dma_cb_t * cb = &callbacks[index];
@@ -113,9 +112,7 @@ PORT_IRQ_HANDLER(DMA_VECTOR) { * @init
*/
void dmaInit(void) {
-#if CH_CFG_USE_SEMAPHORES
- chSemObjectInit(&dma_lock, MSP430X_DMA_CHANNELS);
-#endif
+ osalThreadQueueObjectInit(&dma_queue);
}
/**
@@ -125,134 +122,124 @@ void dmaInit(void) { * semaphores are enabled, the calling thread will sleep until a
* channel is available or the request times out. If semaphores are
* disabled, the calling thread will busy-wait instead of sleeping.
+ *
+ * @sclass
*/
-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout) {
-/* Check if a DMA channel is available */
-#if CH_CFG_USE_SEMAPHORES
- msg_t semresult = chSemWaitTimeout(&dma_lock, timeout);
- if (semresult != MSG_OK)
- return true;
-#endif
-
-#if !(CH_CFG_USE_SEMAPHORES)
- systime_t start = chVTGetSystemTimeX();
-
- do {
-#endif
- /* Grab the correct DMA channel to use */
- int i = 0;
- for (i = 0; i < MSP430X_DMA_CHANNELS; i++) {
- if (!(dma_channels[i].ctl & DMAEN)) {
- break;
- }
- }
-#if !(CH_CFG_USE_SEMAPHORES)
- while (chVTTimeElapsedSinceX(start) < timeout)
- ;
-#endif
-
-#if !(CH_CFG_USE_SEMAPHORES)
- if (i == MSP430X_DMA_CHANNELS) {
- return true;
+int dmaRequestS(msp430x_dma_req_t * request, systime_t timeout) {
+
+ osalDbgCheckClassS();
+
+ /* Check if a DMA channel is available */
+ if (queue_length >= MSP430X_DMA_CHANNELS) {
+ msg_t queueresult = osalThreadEnqueueTimeoutS(&dma_queue, timeout);
+ if (queueresult != MSG_OK)
+ return -1;
+ }
+
+ /* Grab the correct DMA channel to use */
+ int i = 0;
+ for (i = 0; i < MSP430X_DMA_CHANNELS; i++) {
+ if (!(dma_channels[i].ctl & DMAEN)) {
+ break;
}
-#endif
+ }
+
+ /* Make the request */
+ init_request(request, i);
+
+ return i;
+}
- /* Make the request */
- init_request(request, i);
+/**
+ * @brief Acquires exclusive control of a DMA channel.
+ * @pre The channel must not be already acquired or an error is returned.
+ * @note If the channel is in use by the DMA engine, blocks until acquired.
+ * @post This channel must be interacted with using only the functions
+ * defined in this module.
+ *
+ * @param[out] channel The channel handle. Must be pre-allocated.
+ * @param[in] index The index of the channel (< MSP430X_DMA_CHANNELS).
+ * @return The operation status.
+ * @retval false no error, channel acquired.
+ * @retval true error, channel already acquired.
+ *
+ * @iclass
+ */
+bool dmaAcquireI(msp430x_dma_ch_t * channel, uint8_t index) {
+
+ osalDbgCheckClassI();
- return false;
+ /* Is the channel already acquired? */
+ osalDbgAssert(index < MSP430X_DMA_CHANNELS, "invalid channel index");
+ if (dma_channels[index].ctl & DMADT_4) {
+ return true;
}
- /**
- * @brief Acquires exclusive control of a DMA channel.
- * @pre The channel must not be already acquired or an error is returned.
- * @note If the channel is in use by the DMA engine, blocks until acquired.
- * @post This channel must be interacted with using only the functions
- * defined in this module.
- *
- * @param[out] channel The channel handle. Must be pre-allocated.
- * @param[in] index The index of the channel (< MSP430X_DMA_CHANNELS).
- * @return The operation status.
- * @retval false no error, channel acquired.
- * @retval true error, channel already acquired.
- */
- bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index) {
- /* Acquire the channel in an idle mode */
-
- /* Is the channel already acquired? */
- osalDbgAssert(index < MSP430X_DMA_CHANNELS, "invalid channel index");
- if (dma_channels[index].ctl & DMADT_4) {
- return true;
- }
+ /* Increment the DMA counter */
+ queue_length++;
-/* Increment the DMA counter */
-#if CH_CFG_USE_SEMAPHORES
- msg_t semresult = chSemWait(&dma_lock);
- if (semresult != MSG_OK)
- return true;
-#endif
+ while (dma_channels[index].ctl & DMAEN)
+ ;
- while (dma_channels[index].ctl & DMAEN)
- ;
+ /* Acquire the channel in an idle mode */
+ dma_trigger_set(index, DMA_TRIGGER_MNEM(DMAREQ));
+ dma_channels[index].sz = 0;
+ dma_channels[index].ctl = DMAEN | DMAABORT | DMADT_4;
- dma_trigger_set(index, DMA_TRIGGER_MNEM(DMAREQ));
- dma_channels[index].sz = 0;
- dma_channels[index].ctl = DMAEN | DMAABORT | DMADT_4;
+ channel->registers = dma_channels + index;
+ channel->index = index;
+ channel->cb = callbacks + index;
+
+ return false;
+}
- channel->registers = dma_channels + index;
- channel->index = index;
- channel->cb = callbacks + index;
+/**
+ * @brief Initiates a DMA transfer operation using an acquired channel.
+ * @pre The channel must have been acquired using @p dmaAcquire().
+ *
+ * @param[in] channel pointer to a DMA channel from @p dmaAcquire().
+ * @param[in] request pointer to a DMA request object.
+ */
+void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request) {
- return false;
- }
+ dma_trigger_set(channel->index, request->trigger);
+ /**(channel->ctl) = request->trigger;*/
- /**
- * @brief Initiates a DMA transfer operation using an acquired channel.
- * @pre The channel must have been acquired using @p dmaAcquire().
- *
- * @param[in] channel pointer to a DMA channel from @p dmaAcquire().
- * @param[in] request pointer to a DMA request object.
- */
- void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request) {
-
- dma_trigger_set(channel->index, request->trigger);
- /**(channel->ctl) = request->trigger;*/
-
- channel->cb->callback = request->callback.callback;
- channel->cb->args = request->callback.args;
-
- chSysLock();
- channel->registers->ctl &= (~DMAEN);
- channel->registers->sa = (uintptr_t)request->source_addr;
- channel->registers->da = (uintptr_t)request->dest_addr;
- channel->registers->sz = request->size;
- channel->registers->ctl = DMAIE | request->data_mode | request->addr_mode |
- request->transfer_mode | DMADT_4 | DMAEN |
- DMAREQ; /* repeated transfers */
- chSysUnlock();
- }
+ channel->cb->callback = request->callback.callback;
+ channel->cb->args = request->callback.args;
- /**
- * @brief Releases exclusive control of a DMA channel.
- * @details The channel is released from control and returned to the DMA
- * engine
- * pool. Trying to release an unallocated channel is an illegal
- * operation and is trapped if assertions are enabled.
- * @pre The channel must have been acquired using @p dmaAcquire().
- * @post The channel is returned to the DMA engine pool.
- */
- void dmaRelease(msp430x_dma_ch_t * channel) {
-
- osalDbgCheck(channel != NULL);
-
- /* Release the channel in an idle mode */
- channel->registers->ctl = DMAABORT;
-
-/* release the DMA counter */
-#if CH_CFG_USE_SEMAPHORES
- chSemSignal(&dma_lock);
-#endif
- }
+ channel->registers->ctl &= (~DMAEN);
+ channel->registers->sa = (uintptr_t)request->source_addr;
+ channel->registers->da = (uintptr_t)request->dest_addr;
+ channel->registers->sz = request->size;
+ channel->registers->ctl = DMAIE | request->data_mode | request->addr_mode |
+ request->transfer_mode | DMADT_4 | DMAEN |
+ DMAREQ; /* repeated transfers */
+}
+
+/**
+ * @brief Releases exclusive control of a DMA channel.
+ * @details The channel is released from control and returned to the DMA
+ * engine
+ * pool. Trying to release an unallocated channel is an illegal
+ * operation and is trapped if assertions are enabled.
+ * @pre The channel must have been acquired using @p dmaAcquire().
+ * @post The channel is returned to the DMA engine pool.
+ */
+void dmaRelease(msp430x_dma_ch_t * channel) {
+ syssts_t sts;
+
+ sts = osalSysGetStatusAndLockX();
+ osalDbgCheck(channel != NULL);
+
+ /* Release the channel in an idle mode */
+ channel->registers->ctl = DMAABORT;
+
+ /* release the DMA counter */
+ osalThreadDequeueAllI(&dma_queue, MSG_RESET);
+ queue_length = 0;
+ osalSysRestoreStatusX(sts);
+}
#endif /* HAL_USE_DMA == TRUE */
diff --git a/os/hal/ports/MSP430X/hal_dma_lld.h b/os/hal/ports/MSP430X/hal_dma_lld.h index d1495d2..f558e78 100644 --- a/os/hal/ports/MSP430X/hal_dma_lld.h +++ b/os/hal/ports/MSP430X/hal_dma_lld.h @@ -159,8 +159,8 @@ typedef struct { extern "C" {
#endif
void dmaInit(void);
-bool dmaRequest(msp430x_dma_req_t * request, systime_t timeout);
-bool dmaAcquire(msp430x_dma_ch_t * channel, uint8_t index);
+int dmaRequestS(msp430x_dma_req_t * request, systime_t timeout);
+bool dmaAcquireI(msp430x_dma_ch_t * channel, uint8_t index);
void dmaTransfer(msp430x_dma_ch_t * channel, msp430x_dma_req_t * request);
void dmaRelease(msp430x_dma_ch_t * channel);
diff --git a/os/hal/ports/MSP430X/hal_lld.c b/os/hal/ports/MSP430X/hal_lld.c index 872fe97..812a0cf 100644 --- a/os/hal/ports/MSP430X/hal_lld.c +++ b/os/hal/ports/MSP430X/hal_lld.c @@ -82,6 +82,10 @@ void hal_lld_init(void) { } while (SFRIFG1 & OFIFG);
#endif
CSCTL0_H = 0xFF; /* Lock clock system */
+
+#if (HAL_USE_DMA == TRUE)
+ dmaInit();
+#endif
}
/** @} */
diff --git a/os/hal/ports/MSP430X/hal_lld.h b/os/hal/ports/MSP430X/hal_lld.h index 9549453..62f07e9 100644 --- a/os/hal/ports/MSP430X/hal_lld.h +++ b/os/hal/ports/MSP430X/hal_lld.h @@ -25,6 +25,8 @@ #ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
+#include "hal_dma_lld.h"
+
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
diff --git a/os/hal/ports/MSP430X/hal_serial_lld.c b/os/hal/ports/MSP430X/hal_serial_lld.c index 0d9aa1c..feb00ac 100644 --- a/os/hal/ports/MSP430X/hal_serial_lld.c +++ b/os/hal/ports/MSP430X/hal_serial_lld.c @@ -374,11 +374,11 @@ PORT_IRQ_HANDLER(USCI_A0_VECTOR) { if (oqIsEmptyI(&SD0.oqueue))
chnAddFlagsI(&SD0, CHN_TRANSMISSION_END);
UCA0IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
@@ -432,11 +432,11 @@ PORT_IRQ_HANDLER(USCI_A1_VECTOR) { if (oqIsEmptyI(&SD1.oqueue))
chnAddFlagsI(&SD1, CHN_TRANSMISSION_END);
UCA1IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
@@ -490,11 +490,11 @@ PORT_IRQ_HANDLER(USCI_A2_VECTOR) { if (oqIsEmptyI(&SD2.oqueue))
chnAddFlagsI(&SD2, CHN_TRANSMISSION_END);
UCA2IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
@@ -548,11 +548,11 @@ PORT_IRQ_HANDLER(USCI_A3_VECTOR) { if (oqIsEmptyI(&SD3.oqueue))
chnAddFlagsI(&SD3, CHN_TRANSMISSION_END);
UCA3IE &= ~UCTXCPTIE;
+ osalSysUnlockFromISR();
break;
default: /* other interrupts */
- while (1)
- ;
+ osalDbgAssert(false, "unhandled serial interrupt");
break;
}
diff --git a/os/hal/ports/MSP430X/hal_spi_lld.c b/os/hal/ports/MSP430X/hal_spi_lld.c index 70a357e..3a54b1e 100644 --- a/os/hal/ports/MSP430X/hal_spi_lld.c +++ b/os/hal/ports/MSP430X/hal_spi_lld.c @@ -104,21 +104,21 @@ static uint16_t dummyrx; static void init_transfer(SPIDriver * spip) {
#if MSP430X_SPI_EXCLUSIVE_DMA == TRUE || defined(__DOXYGEN__)
- if (spip->config->dmarx_index > MSP430X_DMA_CHANNELS) {
- dmaRequest(&(spip->rx_req), TIME_INFINITE);
+ if (spip->config->dmarx_index >= MSP430X_DMA_CHANNELS) {
+ dmaRequestS(&(spip->rx_req), TIME_INFINITE);
}
else {
dmaTransfer(&(spip->dmarx), &(spip->rx_req));
}
- if (spip->config->dmatx_index > MSP430X_DMA_CHANNELS) {
- dmaRequest(&(spip->tx_req), TIME_INFINITE);
+ if (spip->config->dmatx_index >= MSP430X_DMA_CHANNELS) {
+ dmaRequestS(&(spip->tx_req), TIME_INFINITE);
}
else {
dmaTransfer(&(spip->dmatx), &(spip->tx_req));
}
#else
- dmaRequest(&(spip->rx_req), TIME_INFINITE);
- dmaRequest(&(spip->tx_req), TIME_INFINITE);
+ dmaRequestS(&(spip->rx_req), TIME_INFINITE);
+ dmaRequestS(&(spip->tx_req), TIME_INFINITE);
#endif
*(spip->ifg) |= UCTXIFG;
@@ -325,11 +325,11 @@ void spi_lld_start(SPIDriver * spip) { /* Claim DMA streams here */
bool b;
if (spip->config->dmatx_index < MSP430X_DMA_CHANNELS) {
- b = dmaAcquire(&(spip->dmatx), spip->config->dmatx_index);
+ b = dmaAcquireI(&(spip->dmatx), spip->config->dmatx_index);
osalDbgAssert(!b, "stream already allocated");
}
if (spip->config->dmarx_index < MSP430X_DMA_CHANNELS) {
- b = dmaAcquire(&(spip->dmarx), spip->config->dmarx_index);
+ b = dmaAcquireI(&(spip->dmarx), spip->config->dmarx_index);
osalDbgAssert(!b, "stream already allocated");
}
#endif /* MSP430X_SPI_EXCLUSIVE_DMA */
@@ -388,10 +388,11 @@ void spi_lld_start(SPIDriver * spip) { spip->regs->ctlw0 = UCSWRST;
spip->regs->brw = brw;
spip->regs->ctlw0 =
- (spip->config->spi_mode << 14) | (spip->config->bit_order << 13) |
+ ((spip->config->spi_mode ^ 0x02) << 14) | (spip->config->bit_order << 13) |
(spip->config->data_size << 12) | (UCMST) |
((spip->config->ss_line ? 0 : 2) << 9) | (UCSYNC) | (ssel) | (UCSTEM);
*(spip->ifg) = 0;
+ spi_lld_unselect(spip);
}
/**
@@ -406,8 +407,12 @@ void spi_lld_stop(SPIDriver * spip) { if (spip->state == SPI_READY) {
/* Disables the peripheral.*/
#if MSP430X_SPI_EXCLUSIVE_DMA == TRUE
- dmaRelease(&(spip->dmatx));
- dmaRelease(&(spip->dmarx));
+ if (spip->config->dmatx_index < MSP430X_DMA_CHANNELS) {
+ dmaRelease(&(spip->dmatx));
+ }
+ if (spip->config->dmarx_index < MSP430X_DMA_CHANNELS) {
+ dmaRelease(&(spip->dmarx));
+ }
#endif
spip->regs->ctlw0 = UCSWRST;
}
@@ -561,15 +566,12 @@ void spi_lld_receive(SPIDriver * spip, size_t n, void * rxbuf) { * @param[in] frame the data frame to send over the SPI bus
* @return The received data frame from the SPI bus.
*/
-uint16_t spi_lld_polled_exchange(SPIDriver * spip, uint16_t frame) {
-
- osalDbgAssert(!(frame & 0xFF00U), "16-bit transfers not supported");
+uint8_t spi_lld_polled_exchange(SPIDriver * spip, uint8_t frame) {
- while (!(*(spip->ifg) & UCTXIFG))
- ;
spip->regs->txbuf = frame;
while (!(*(spip->ifg) & UCRXIFG))
;
+ *(spip->ifg) &= ~(UCRXIFG | UCTXIFG);
return spip->regs->rxbuf;
}
diff --git a/os/hal/ports/MSP430X/hal_spi_lld.h b/os/hal/ports/MSP430X/hal_spi_lld.h index ebf14c8..949a8a0 100644 --- a/os/hal/ports/MSP430X/hal_spi_lld.h +++ b/os/hal/ports/MSP430X/hal_spi_lld.h @@ -118,7 +118,7 @@ * @note This increases the size of the compiled executable somewhat.
* @note The default is @p FALSE.
*/
-#if !defined(MSP430X_SPI_EXCLUSIVE_DMA) | defined(__DOXYGEN__)
+#if !defined(MSP430X_SPI_EXCLUSIVE_DMA) || defined(__DOXYGEN__)
#define MSP430X_SPI_EXCLUSIVE_DMA FALSE
#endif
@@ -630,7 +630,7 @@ extern "C" { const void *txbuf, void *rxbuf);
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
- uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
+ uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame);
#ifdef __cplusplus
}
#endif
diff --git a/os/hal/ports/MSP430X/platform.mk b/os/hal/ports/MSP430X/platform.mk index 832814b..627a2f0 100644 --- a/os/hal/ports/MSP430X/platform.mk +++ b/os/hal/ports/MSP430X/platform.mk @@ -4,7 +4,8 @@ PLATFORMSRC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_serial_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_pal_lld.c \
${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_dma_lld.c \
- ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_spi_lld.c
+ ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_spi_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X/hal_adc_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS_CONTRIB}/os/hal/ports/MSP430X
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c index 601deca..a2cf026 100644..100755 --- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c +++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c @@ -15,7 +15,7 @@ */ /** - * @file STM32/CRCv1/crc_lld.c + * @file STM32/CRCv1/hal_crc_lld.c * @brief STM32 CRC subsystem low level driver source. * * @addtogroup CRC @@ -185,15 +185,15 @@ void crc_lld_start(CRCDriver *crcp) { crcp->crc->CR |= CRC_CR_REV_OUT; } #else - osalDbgAssert(crcp->config->initial_val != default_config.initial_val, + osalDbgAssert(crcp->config->initial_val == default_config.initial_val, "hardware doesn't support programmable initial value"); - osalDbgAssert(crcp->config->poly_size != default_config.poly_size, + osalDbgAssert(crcp->config->poly_size == default_config.poly_size, "hardware doesn't support programmable polynomial size"); - osalDbgAssert(crcp->config->poly != default_config.poly, + osalDbgAssert(crcp->config->poly == default_config.poly, "hardware doesn't support programmable polynomial"); - osalDbgAssert(crcp->config->reflect_data != default_config.reflect_data, + osalDbgAssert(crcp->config->reflect_data == default_config.reflect_data, "hardware doesn't support reflect of input data"); - osalDbgAssert(crcp->config->reflect_remainder != default_config.reflect_remainder, + osalDbgAssert(crcp->config->reflect_remainder == default_config.reflect_remainder, "hardware doesn't support reflect of output remainder"); #endif @@ -299,7 +299,7 @@ uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) { n--; } #else - osalDbgAssert(n != 0, "STM32 CRC Unit only supports WORD accesses"); + osalDbgAssert(n == 0, "STM32 CRC Unit only supports WORD accesses"); #endif #endif diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h index ecdaf81..213d346 100644 --- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h +++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h @@ -15,15 +15,15 @@ */ /** - * @file STM32/CRCv1/crc_lld.h + * @file STM32/CRCv1/hal_crc_lld.h * @brief STM32 CRC subsystem low level driver header. * * @addtogroup CRC * @{ */ -#ifndef _CRC_LLD_H_ -#define _CRC_LLD_H_ +#ifndef HAL_CRC_LLD_H_ +#define HAL_CRC_LLD_H_ #if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__) @@ -244,6 +244,6 @@ extern "C" { #endif /* HAL_USE_CRC */ -#endif /* _CRC_LLD_H_ */ +#endif /* HAL_CRC_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c index aba029f..6751202 100644 --- a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c +++ b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c @@ -15,7 +15,7 @@ */ /** - * @file stm32_dma2d.c + * @file hal_stm32_dma2d.c * @brief DMA2D/Chrom-ART driver. */ diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h index 01f0941..c06ab62 100644 --- a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h +++ b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.h @@ -15,15 +15,15 @@ */ /** - * @file stm32_dma2d.h + * @file hal_stm32_dma2d.h * @brief DMA2D/Chrom-ART driver. * * @addtogroup dma2d * @{ */ -#ifndef _STM32_DMA2D_H_ -#define _STM32_DMA2D_H_ +#ifndef HAL_STM32_DMA2D_H_ +#define HAL_STM32_DMA2D_H_ /** * @brief Using the DMA2D driver. @@ -659,6 +659,6 @@ extern "C" { #endif /* STM32_DMA2D_USE_DMA2D */ -#endif /* _STM32_DMA2D_H_ */ +#endif /* HAL_STM32_DMA2D_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c index 40ad05c..b4c2938 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c @@ -15,7 +15,7 @@ */ /** - * @file fsmc.c + * @file hal_fsmc.c * @brief FSMC Driver subsystem low level driver source template. * * @addtogroup FSMC @@ -125,7 +125,7 @@ void fsmc_start(FSMCDriver *fsmcp) { rccResetFSMC(); #endif rccEnableFSMC(FALSE); -#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND) +#if HAL_USE_NAND nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY); #endif } @@ -153,7 +153,7 @@ void fsmc_stop(FSMCDriver *fsmcp) { /* Disables the peripheral.*/ #if STM32_FSMC_USE_FSMC1 if (&FSMCD1 == fsmcp) { -#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND) +#if HAL_USE_NAND nvicDisableVector(STM32_FSMC_NUMBER); #endif rccDisableFSMC(FALSE); @@ -164,7 +164,6 @@ void fsmc_stop(FSMCDriver *fsmcp) { } } -#if !STM32_NAND_USE_EXT_INT /** * @brief FSMC shared interrupt handler. * @@ -185,7 +184,6 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { #endif CH_IRQ_EPILOGUE(); } -#endif /* !STM32_NAND_USE_EXT_INT */ #endif /* HAL_USE_FSMC */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h index f9d8a60..f4837f5 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h @@ -15,15 +15,15 @@ */ /** - * @file fsmc.h + * @file hal_fsmc.h * @brief FSMC Driver subsystem low level driver header. * * @addtogroup FSMC * @{ */ -#ifndef _FSMC_H_ -#define _FSMC_H_ +#ifndef HAL_FSMC_H_ +#define HAL_FSMC_H_ #if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) @@ -230,6 +230,9 @@ typedef struct { defined(STM32F7)) #define FSMC_BCR_CCLKEN ((uint32_t)1 << 20) #endif +#if (defined(STM32F7)) +#define FSMC_BCR_WFDIS ((uint32_t)1 << 21) +#endif /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -247,15 +250,6 @@ typedef struct { #define STM32_FSMC_USE_FSMC1 FALSE #endif -/** - * @brief Internal FSMC interrupt enable switch - * @details MCUs in 100-pin package has no dedicated interrupt pin for FSMC. - * You have to use EXTI module instead to workaround this issue. - */ -#if !defined(STM32_NAND_USE_EXT_INT) || defined(__DOXYGEN__) -#define STM32_NAND_USE_EXT_INT FALSE -#endif - /** @} */ /*===========================================================================*/ @@ -344,6 +338,6 @@ extern "C" { #endif /* HAL_USE_FSMC */ -#endif /* _FSMC_H_ */ +#endif /* HAL_FSMC_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c index 95f47d5..ac83477 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c @@ -18,7 +18,7 @@ */ /** - * @file fsmc_sdram.c + * @file hal_fsmc_sdram.c * @brief SDRAM Driver subsystem low level driver source. * * @addtogroup SDRAM diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h index cef6772..b419168 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h @@ -18,15 +18,15 @@ */ /** - * @file fsmc_sdram.h + * @file hal_fsmc_sdram.h * @brief SDRAM Driver subsystem low level driver header. * * @addtogroup SDRAM * @{ */ -#ifndef _FMC_SDRAM_H_ -#define _FMC_SDRAM_H_ +#ifndef HAL_FMC_SDRAM_H_ +#define HAL_FMC_SDRAM_H_ #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx)) @@ -166,6 +166,6 @@ extern "C" { #endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ -#endif /* _FMC_SDRAM_H_ */ +#endif /* HAL_FMC_SDRAM_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c index 6f710d4..333362f 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c @@ -15,7 +15,7 @@ */ /** - * @file fsmc_sram.c + * @file hal_fsmc_sram.c * @brief SRAM Driver subsystem low level driver source. * * @addtogroup SRAM diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h index 529bdc7..5e749a8 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h @@ -15,15 +15,15 @@ */ /** - * @file fsmc_sram.h + * @file hal_fsmc_sram.h * @brief SRAM Driver subsystem low level driver header. * * @addtogroup SRAM * @{ */ -#ifndef _FSMC_SRAM_H_ -#define _FSMC_SRAM_H_ +#ifndef HAL_FSMC_SRAM_H_ +#define HAL_FSMC_SRAM_H_ #include "hal_fsmc.h" @@ -167,6 +167,6 @@ extern "C" { #endif /* STM32_USE_FSMC_SRAM */ -#endif /* _FSMC_SRAM_H_ */ +#endif /* HAL_FSMC_SRAM_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c index b37c026..f39ff35 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c @@ -15,7 +15,7 @@ */ /** - * @file nand_lld.c + * @file hal_nand_lld.c * @brief NAND Driver subsystem low level driver source. * * @addtogroup NAND @@ -117,13 +117,10 @@ static uint32_t calc_eccps(NANDDriver *nandp) { * @notapi */ static void nand_ready_isr_enable(NANDDriver *nandp) { -#if STM32_NAND_USE_EXT_INT - nandp->config->ext_nand_isr_enable(); -#else + nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | - FSMC_SR_ILEN | FSMC_SR_IFEN); + FSMC_SR_ILEN | FSMC_SR_IFEN); nandp->nand->SR |= FSMC_SR_IREN; -#endif } /** @@ -134,11 +131,8 @@ static void nand_ready_isr_enable(NANDDriver *nandp) { * @notapi */ static void nand_ready_isr_disable(NANDDriver *nandp) { -#if STM32_NAND_USE_EXT_INT - nandp->config->ext_nand_isr_disable(); -#else + nandp->nand->SR &= ~FSMC_SR_IREN; -#endif } /** @@ -152,10 +146,8 @@ static void nand_isr_handler (NANDDriver *nandp) { osalSysLockFromISR(); -#if !STM32_NAND_USE_EXT_INT osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */ nandp->nand->SR &= ~FSMC_SR_IRS; -#endif switch (nandp->state){ case NAND_READ: @@ -501,12 +493,13 @@ void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { */ uint8_t nand_lld_read_status(NANDDriver *nandp) { - uint8_t status[1] = {0x01}; /* presume worse */ + uint8_t status; + status = 1; /* presume worse */ nand_lld_write_cmd(nandp, NAND_CMD_STATUS); - nand_lld_polled_read_data(nandp, status, 1); + nand_lld_polled_read_data(nandp, &status, 1); - return status[0]; + return status; } #endif /* HAL_USE_NAND */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h index 8dca42f..de7a0c4 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h @@ -15,15 +15,15 @@ */ /** - * @file nand_lld.h + * @file hal_nand_lld.h * @brief NAND Driver subsystem low level driver header. * * @addtogroup NAND * @{ */ -#ifndef _NAND_LLD_H_ -#define _NAND_LLD_H_ +#ifndef HAL_NAND_LLD_H_ +#define HAL_NAND_LLD_H_ #include "hal_fsmc.h" #include "bitmap.h" @@ -120,10 +120,6 @@ #error "FSMC not present in the selected device" #endif -#if STM32_NAND_USE_EXT_INT && !HAL_USE_EXT -#error "External interrupt controller must be enabled to use this feature" -#endif - #if !defined(STM32_DMA_REQUIRED) #define STM32_DMA_REQUIRED #endif @@ -133,11 +129,6 @@ /*===========================================================================*/ /** - * @brief NAND driver condition flags type. - */ -typedef uint32_t nandflags_t; - -/** * @brief Type of a structure representing an NAND driver. */ typedef struct NANDDriver NANDDriver; @@ -147,23 +138,12 @@ typedef struct NANDDriver NANDDriver; */ typedef void (*nandisrhandler_t)(NANDDriver *nandp); -#if STM32_NAND_USE_EXT_INT -/** - * @brief Type of function switching external interrupts on and off. - */ -typedef void (*nandisrswitch_t)(void); -#endif /* STM32_NAND_USE_EXT_INT */ - /** * @brief Driver configuration structure. * @note It could be empty on some architectures. */ typedef struct { /** - * @brief Pointer to lower level driver. - */ - //const FSMCDriver *fsmcp; - /** * @brief Number of erase blocks in NAND device. */ uint32_t blocks; @@ -197,16 +177,6 @@ typedef struct { * from STMicroelectronics. */ uint32_t pmem; -#if STM32_NAND_USE_EXT_INT - /** - * @brief Function enabling interrupts from EXTI - */ - nandisrswitch_t ext_nand_isr_enable; - /** - * @brief Function disabling interrupts from EXTI - */ - nandisrswitch_t ext_nand_isr_disable; -#endif /* STM32_NAND_USE_EXT_INT */ } NANDConfig; /** @@ -319,6 +289,6 @@ extern "C" { #endif /* HAL_USE_NAND */ -#endif /* _NAND_LLD_H_ */ +#endif /* HAL_NAND_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c index e5f9a09..f0fd289 100644 --- a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c +++ b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c @@ -15,7 +15,7 @@ */ /** - * @file stm32_ltdc.c + * @file hal_stm32_ltdc.c * @brief LCD-TFT Controller Driver. */ diff --git a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h index 16b38ca..5db89e2 100644 --- a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h +++ b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.h @@ -15,15 +15,15 @@ */ /** - * @file stm32_ltdc.h + * @file hal_stm32_ltdc.h * @brief LCD-TFT Controller Driver. * * @addtogroup ltdc * @{ */ -#ifndef _STM32_LTDC_H_ -#define _STM32_LTDC_H_ +#ifndef HAL_STM32_LTDC_H_ +#define HAL_STM32_LTDC_H_ /** * @brief Using the LTDC driver. @@ -731,6 +731,6 @@ extern "C" { #endif /* STM32_LTDC_USE_LTDC */ -#endif /* _STM32_LTDC_H_ */ +#endif /* HAL_STM32_LTDC_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h index 927eb6f..e72098e 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h @@ -22,8 +22,8 @@ 32-bit timers and timers with single capture/compare channels. */ -#ifndef __EICU_LLD_H -#define __EICU_LLD_H +#ifndef HAL_EICU_LLD_H +#define HAL_EICU_LLD_H #include "stm32_tim.h" @@ -551,4 +551,4 @@ extern "C" { #endif /* HAL_USE_EICU */ -#endif /* __EICU_LLD_H */ +#endif /* HAL_EICU_LLD_H */ diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c index ffc4992..6138481 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c @@ -194,24 +194,24 @@ void qei_lld_start(QEIDriver *qeip) { #endif
}
/* Timer configuration.*/
- qeip->tim->CR1 = 0; /* Initially stopped. */
+ qeip->tim->CR1 = 0; /* Initially stopped. */
qeip->tim->CR2 = 0;
qeip->tim->PSC = 0;
qeip->tim->DIER = 0;
- qeip->tim->ARR = 0xFFFF;
+ qeip->tim->ARR = 0xFFFF;
/* Set Capture Compare 1 and Capture Compare 2 as input. */
qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
if (qeip->config->mode == QEI_MODE_QUADRATURE) {
if (qeip->config->resolution == QEI_BOTH_EDGES)
- qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
else
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
} else {
/* Direction/Clock mode.
* Direction input on TI1, Clock input on TI2. */
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
}
if (qeip->config->dirinv == QEI_DIRINV_TRUE)
@@ -230,7 +230,7 @@ void qei_lld_start(QEIDriver *qeip) { void qei_lld_stop(QEIDriver *qeip) {
if (qeip->state == QEI_READY) {
- qeip->tim->CR1 = 0; /* Timer disabled. */
+ qeip->tim->CR1 = 0; /* Timer disabled. */
/* Clock deactivation.*/
#if STM32_QEI_USE_TIM1
@@ -275,7 +275,7 @@ void qei_lld_stop(QEIDriver *qeip) { */
void qei_lld_enable(QEIDriver *qeip) {
- qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
+ qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
}
/**
@@ -287,7 +287,7 @@ void qei_lld_enable(QEIDriver *qeip) { */
void qei_lld_disable(QEIDriver *qeip) {
- qeip->tim->CR1 = 0; /* Timer disabled. */
+ qeip->tim->CR1 = 0; /* Timer disabled. */
}
#endif /* HAL_USE_QEI */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c index 8ab6176..c55fae2 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c @@ -24,7 +24,7 @@ /** - * @file STM32/timcap_lld.c + * @file STM32/hal_timcap_lld.c * @brief STM32 TIMCAP subsystem low level driver header. * * @addtogroup TIMCAP diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h index d39c438..643798a 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h @@ -22,8 +22,8 @@ * @{ */ -#ifndef _TIMCAP_LLD_H_ -#define _TIMCAP_LLD_H_ +#ifndef HAL_TIMCAP_LLD_H_ +#define HAL_TIMCAP_LLD_H_ #include "ch.h" #include "hal.h" diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h b/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h index ca2dc49..b88e620 100644 --- a/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h +++ b/os/hal/ports/STM32/LLD/USBHv1/hal_stm32_otg.h @@ -15,7 +15,7 @@ */ /** - * @file stm32_otg.h + * @file hal_stm32_otg.h * @brief STM32 OTG registers layout header. * * @addtogroup USB @@ -23,8 +23,8 @@ */ -#ifndef _STM32_OTG_H_ -#define _STM32_OTG_H_ +#ifndef HAL_STM32_OTG_H_ +#define HAL_STM32_OTG_H_ /** * @brief Number of the implemented endpoints in OTG_FS. diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h index e8df749..5c0ac40 100644 --- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h +++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.h @@ -15,8 +15,8 @@ limitations under the License. */ -#ifndef USBH_LLD_H_ -#define USBH_LLD_H_ +#ifndef HAL_USBH_LLD_H_ +#define HAL_USBH_LLD_H_ #include "hal.h" @@ -150,4 +150,4 @@ uint8_t usbh_lld_roothub_get_statuschange_bitmap(USBHDriver *usbh); #endif -#endif /* USBH_LLD_H_ */ +#endif /* HAL_USBH_LLD_H_ */ diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c index efe6421..d0788f4 100644 --- a/os/hal/ports/TIVA/LLD/hal_ext_lld.c +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c @@ -34,11 +34,11 @@ * @brief Generic interrupt serving code for multiple pins per interrupt * handler. */ -#define ext_lld_serve_port_interrupt(gpiop, start) \ +#define ext_lld_serve_port_interrupt(gpio, start) \ do { \ - uint32_t mis = gpiop->MIS; \ + uint32_t mis = HWREG(gpio + GPIO_O_MIS); \ \ - gpiop->ICR = mis; \ + HWREG(gpio + GPIO_O_ICR) = mis; \ \ if (mis & (1 << 0)) { \ EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0); \ @@ -89,7 +89,7 @@ EXTDriver EXTD1; /* Driver local variables and types. */ /*===========================================================================*/ -const ioportid_t gpio[] = +const ioportid_t gpio_table[] = { #if TIVA_HAS_GPIOA GPIOA, @@ -847,58 +847,58 @@ void ext_lld_stop(EXTDriver *extp) } #if TIVA_HAS_GPIOA - GPIOA->IM = 0; + HWREG(GPIOA + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOB - GPIOB->IM = 0; + HWREG(GPIOB + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOC - GPIOC->IM = 0; + HWREG(GPIOC + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOD - GPIOD->IM = 0; + HWREG(GPIOD + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOE - GPIOE->IM = 0; + HWREG(GPIOE + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOF - GPIOF->IM = 0; + HWREG(GPIOF + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOG - GPIOG->IM = 0; + HWREG(GPIOG + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOH - GPIOH->IM = 0; + HWREG(GPIOH + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOJ - GPIOJ->IM = 0; + HWREG(GPIOJ + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOK - GPIOK->IM = 0; + HWREG(GPIOK + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOL - GPIOL->IM = 0; + HWREG(GPIOL + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOM - GPIOM->IM = 0; + HWREG(GPIOM + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPION - GPION->IM = 0; + HWREG(GPION + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOP - GPIOP->IM = 0; + HWREG(GPIOP + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOQ - GPIOQ->IM = 0; + HWREG(GPIOQ + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOR - GPIOR->IM = 0; + HWREG(GPIOR + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOS - GPIOS->IM = 0; + HWREG(GPIOS + GPIO_O_IM) = 0; #endif #if TIVA_HAS_GPIOT - GPIOT->IM = 0; + HWREG(GPIOT + GPIO_O_IM) = 0; #endif } @@ -912,34 +912,34 @@ void ext_lld_stop(EXTDriver *extp) */ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { - GPIO_TypeDef *gpiop; + uint32_t gpio; uint8_t pin; uint32_t im; pin = channel & 0x07; - gpiop = gpio[channel >> 3]; + gpio = gpio_table[channel >> 3]; /* Disable interrupts */ - im = gpiop->IM; - gpiop->IM = 0; + im = HWREG(gpio + GPIO_O_IM); + HWREG(gpio + GPIO_O_IM) = 0; /* Configure pin to be edge-sensitive.*/ - gpiop->IS &= ~(1 << pin); + HWREG(gpio + GPIO_O_IS) &= ~(1 << pin); /* Programming edge registers.*/ if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == EXT_CH_MODE_BOTH_EDGES) { - gpiop->IBE |= (1 << pin); + HWREG(gpio + GPIO_O_IBE) |= (1 << pin); } else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == EXT_CH_MODE_FALLING_EDGE) { - gpiop->IBE &= ~(1 << pin); - gpiop->IEV &= ~(1 << pin); + HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin); + HWREG(gpio + GPIO_O_IEV) &= ~(1 << pin); } else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == EXT_CH_MODE_RISING_EDGE) { - gpiop->IBE &= ~(1 << pin); - gpiop->IEV |= (1 << pin); + HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin); + HWREG(gpio + GPIO_O_IEV) |= (1 << pin); } /* Programming interrupt and event registers.*/ @@ -953,7 +953,7 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) } /* Restore interrupts */ - gpiop->IM = im; + HWREG(gpio + GPIO_O_IM) = im; } /** @@ -967,13 +967,13 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { (void)extp; - GPIO_TypeDef *gpiop; + uint32_t gpio; uint8_t pin; pin = channel & 0x07; - gpiop = gpio[channel >> 3]; + gpio = gpio_table[channel >> 3]; - gpiop->IM &= ~(1 << pin); + HWREG(gpio + GPIO_O_IM) &= ~(1 << pin); } #endif /* HAL_USE_EXT */ diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h index 08accb2..08accb2 100644 --- a/os/hal/ports/TIVA/LLD/hal_ext_lld.h +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c index 5460fd4..4df6665 100644 --- a/os/hal/ports/TIVA/LLD/hal_pal_lld.c +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c @@ -250,19 +250,19 @@ */ static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config) { - port->DATA = config->data; - port->DIR = config->dir; - port->AFSEL = config->afsel; - port->DR2R = config->dr2r; - port->DR4R = config->dr4r; - port->DR8R = config->dr8r; - port->ODR = config->odr; - port->PUR = config->pur; - port->PDR = config->pdr; - port->SLR = config->slr; - port->DEN = config->den; - port->AMSEL = config->amsel; - port->PCTL = config->pctl; + HWREG((port) + GPIO_O_DATA) = config->data; + HWREG((port) + GPIO_O_DIR) = config->dir; + HWREG((port) + GPIO_O_AFSEL) = config->afsel; + HWREG((port) + GPIO_O_DR2R) = config->dr2r; + HWREG((port) + GPIO_O_DR4R) = config->dr4r; + HWREG((port) + GPIO_O_DR8R) = config->dr8r; + HWREG((port) + GPIO_O_ODR) = config->odr; + HWREG((port) + GPIO_O_PUR) = config->pur; + HWREG((port) + GPIO_O_PDR) = config->pdr; + HWREG((port) + GPIO_O_SLR) = config->slr; + HWREG((port) + GPIO_O_DEN) = config->den; + HWREG((port) + GPIO_O_AMSEL) = config->amsel; + HWREG((port) + GPIO_O_PCTL) = config->pctl; } /** @@ -274,8 +274,9 @@ static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config) */ static void gpio_unlock(ioportid_t port, ioportmask_t mask) { - port->LOCK = TIVA_GPIO_LOCK_PWD; - port->CR = mask; + + HWREG((port) + GPIO_O_LOCK) = TIVA_GPIO_LOCK_PWD; + HWREG((port) + GPIO_O_CR) = mask; } /*===========================================================================*/ @@ -299,13 +300,13 @@ void _pal_lld_init(const PALConfig *config) /* * Enables all GPIO clocks. */ - SYSCTL->RCGCGPIO = RCGCGPIO_MASK; + HWREG(SYSCTL_RCGCGPIO) = RCGCGPIO_MASK; #if defined(TM4C123x) - SYSCTL->GPIOHBCTL = GPIOHBCTL_MASK; + HWREG(SYSCTL_GPIOHBCTL) = GPIOHBCTL_MASK; #endif /* Wait until all GPIO modules are ready */ - while (!((SYSCTL->PRGPIO & RCGCGPIO_MASK) == RCGCGPIO_MASK)) + while (!((HWREG(SYSCTL_PRGPIO) & RCGCGPIO_MASK) == RCGCGPIO_MASK)) ; #if TIVA_HAS_GPIOA @@ -402,18 +403,18 @@ void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) uint32_t bit_mask = (1 << bit); if ((mask & 1) != 0) { - port->DIR = (port->DIR & ~bit_mask) | dir; - port->AFSEL = (port->AFSEL & ~bit_mask) | afsel; - port->DR2R = (port->DR2R & ~bit_mask) | dr2r; - port->DR4R = (port->DR4R & ~bit_mask) | dr4r; - port->DR8R = (port->DR8R & ~bit_mask) | dr8r; - port->ODR = (port->ODR & ~bit_mask) | odr; - port->PUR = (port->PUR & ~bit_mask) | pur; - port->PDR = (port->PDR & ~bit_mask) | pdr; - port->SLR = (port->SLR & ~bit_mask) | slr; - port->DEN = (port->DEN & ~bit_mask) | den; - port->AMSEL = (port->AMSEL & ~bit_mask) | amsel; - port->PCTL = (port->PCTL & ~pctl_mask) | pctl; + HWREG((port) + GPIO_O_DIR) = (HWREG((port) + GPIO_O_DIR) & ~bit_mask) | dir; + HWREG((port) + GPIO_O_AFSEL) = (HWREG((port) + GPIO_O_AFSEL) & ~bit_mask) | afsel; + HWREG((port) + GPIO_O_DR2R) = (HWREG((port) + GPIO_O_DR2R) & ~bit_mask) | dr2r; + HWREG((port) + GPIO_O_DR4R) = (HWREG((port) + GPIO_O_DR4R) & ~bit_mask) | dr4r; + HWREG((port) + GPIO_O_DR8R) = (HWREG((port) + GPIO_O_DR8R) & ~bit_mask) | dr8r; + HWREG((port) + GPIO_O_ODR) = (HWREG((port) + GPIO_O_ODR) & ~bit_mask) | odr; + HWREG((port) + GPIO_O_PUR) = (HWREG((port) + GPIO_O_PUR) & ~bit_mask) | pur; + HWREG((port) + GPIO_O_PDR) = (HWREG((port) + GPIO_O_PDR) & ~bit_mask) | pdr; + HWREG((port) + GPIO_O_SLR) = (HWREG((port) + GPIO_O_SLR) & ~bit_mask) | slr; + HWREG((port) + GPIO_O_DEN) = (HWREG((port) + GPIO_O_DEN) & ~bit_mask) | den; + HWREG((port) + GPIO_O_AMSEL) = (HWREG((port) + GPIO_O_AMSEL) & ~bit_mask) | amsel; + HWREG((port) + GPIO_O_PCTL) = (HWREG((port) + GPIO_O_PCTL) & ~pctl_mask) | pctl; } mask >>= 1; diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h index c0cd82b..4e7005b 100644 --- a/os/hal/ports/TIVA/LLD/hal_pal_lld.h +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h @@ -352,70 +352,70 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if defined(TM4C123x) +//#if defined(TM4C123x) #if TIVA_GPIO_GPIOA_USE_AHB -#define GPIOA GPIOA_AHB +#define GPIOA GPIO_PORTA_AHB_BASE #else -#define GPIOA GPIOA_APB +#define GPIOA GPIO_PORTA_BASE #endif #if TIVA_GPIO_GPIOB_USE_AHB -#define GPIOB GPIOB_AHB +#define GPIOB GPIO_PORTB_AHB_BASE #else -#define GPIOB GPIOB_APB +#define GPIOB GPIO_PORTB_BASE #endif #if TIVA_GPIO_GPIOC_USE_AHB -#define GPIOC GPIOC_AHB +#define GPIOC GPIO_PORTC_AHB_BASE #else -#define GPIOC GPIOC_APB +#define GPIOC GPIO_PORTC_BASE #endif #if TIVA_GPIO_GPIOD_USE_AHB -#define GPIOD GPIOD_AHB +#define GPIOD GPIO_PORTD_AHB_BASE #else -#define GPIOD GPIOD_APB +#define GPIOD GPIO_PORTD_BASE #endif #if TIVA_GPIO_GPIOE_USE_AHB -#define GPIOE GPIOE_AHB +#define GPIOE GPIO_PORTE_AHB_BASE #else -#define GPIOE GPIOE_APB +#define GPIOE GPIO_PORTE_BASE #endif #if TIVA_GPIO_GPIOF_USE_AHB -#define GPIOF GPIOF_AHB +#define GPIOF GPIO_PORTF_AHB_BASE #else -#define GPIOF GPIOF_APB +#define GPIOF GPIO_PORTF_BASE #endif #if TIVA_GPIO_GPIOG_USE_AHB -#define GPIOG GPIOG_AHB +#define GPIOG GPIO_PORTG_AHB_BASE #else -#define GPIOG GPIOG_APB +#define GPIOG GPIO_PORTG_BASE #endif #if TIVA_GPIO_GPIOH_USE_AHB -#define GPIOH GPIOH_AHB +#define GPIOH GPIO_PORTH_AHB_BASE #else -#define GPIOH GPIOH_APB +#define GPIOH GPIO_PORTH_BASE #endif #if TIVA_GPIO_GPIOJ_USE_AHB -#define GPIOJ GPIOJ_AHB +#define GPIOJ GPIO_PORTJ_AHB_BASE #else -#define GPIOJ GPIOJ_APB +#define GPIOJ GPIO_PORTJ_BASE #endif -#define GPIOK GPIOK_AHB -#define GPIOL GPIOL_AHB -#define GPIOM GPIOM_AHB -#define GPION GPION_AHB -#define GPIOP GPIOP_AHB -#define GPIOQ GPIOQ_AHB +#define GPIOK GPIO_PORTK_BASE +#define GPIOL GPIO_PORTL_BASE +#define GPIOM GPIO_PORTM_BASE +#define GPION GPIO_PORTN_BASE +#define GPIOP GPIO_PORTP_BASE +#define GPIOQ GPIO_PORTQ_BASE -#endif +//#endif /*===========================================================================*/ /* Driver data structures and types. */ @@ -550,7 +550,7 @@ typedef uint32_t iomode_t; /** * @brief Port Identifier. */ -typedef GPIO_TypeDef *ioportid_t; +typedef uint32_t ioportid_t; /*===========================================================================*/ /* Driver macros. */ @@ -573,7 +573,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_readport(port) ((port)->DATA) +#define pal_lld_readport(port) (HWREG((port) + GPIO_O_DATA + (0xff << 2))) /** * @brief Reads the output latch. @@ -585,7 +585,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_readlatch(port) ((port)->DATA) +#define pal_lld_readlatch(port) pal_lld_readport(port) /** * @brief Writes a bits mask on a I/O port. @@ -595,7 +595,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) +#define pal_lld_writeport(port, bits) (HWREG((port) + GPIO_O_DATA + (0xff << 2)) = (bits)) /** * @brief Sets a bits mask on a I/O port. @@ -608,7 +608,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFF) +#define pal_lld_setport(port, bits) (HWREG((port) + (GPIO_O_DATA + (bits << 2))) = 0xFF) /** * @brief Clears a bits mask on a I/O port. @@ -621,7 +621,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) +#define pal_lld_clearport(port, bits) (HWREG((port) + (GPIO_O_DATA + (bits << 2))) = 0) /** * @brief Reads a group of bits. @@ -637,7 +637,7 @@ typedef GPIO_TypeDef *ioportid_t; * @notapi */ #define pal_lld_readgroup(port, mask, offset) \ - ((port)->MASKED_ACCESS[(mask) << (offset)]) + (HWREG((port) + (GPIO_O_DATA + (((mask) << (offset)) << 2)))) /** * @brief Writes a group of bits. @@ -654,7 +654,7 @@ typedef GPIO_TypeDef *ioportid_t; * @notapi */ #define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) + (HWREG((port) + (GPIO_O_DATA + (((mask) << (offset)) << 2))) = (bits)) /** * @brief Pads group mode setup. @@ -686,7 +686,7 @@ typedef GPIO_TypeDef *ioportid_t; * * @notapi */ -#define pal_lld_readpad(port, pad) ((port)->MASKED_ACCESS[1 << (pad)]) +#define pal_lld_readpad(port, pad) (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2)))) /** * @brief Writes a logical state on an output pad. @@ -704,7 +704,7 @@ typedef GPIO_TypeDef *ioportid_t; * @notapi */ #define pal_lld_writepad(port, pad, bit) \ - ((port)->MASKED_ACCESS[1 << (pad)] = (bit)) + (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = (bit)) /** * @brief Sets a pad logical state to @p PAL_HIGH. @@ -718,7 +718,7 @@ typedef GPIO_TypeDef *ioportid_t; * @notapi */ #define pal_lld_setpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) + (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 1 << (pad)) /** * @brief Clears a pad logical state to @p PAL_LOW. @@ -732,7 +732,7 @@ typedef GPIO_TypeDef *ioportid_t; * @notapi */ #define pal_lld_clearpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 0) + (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 0) /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c index 870ba12..60d2b82 100644 --- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c @@ -133,7 +133,7 @@ GPTDriver GPTD12; */ static void gpt_lld_serve_interrupt(GPTDriver *gptp) { - gptp->gpt->ICR = 0xffffffff; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff; if (gptp->state == GPT_ONESHOT) { gptp->state = GPT_READY; @@ -388,62 +388,62 @@ void gpt_lld_init(void) { /* Driver initialization.*/ #if TIVA_GPT_USE_GPT0 - GPTD1.gpt = GPT0; + GPTD1.gpt = TIMER0_BASE; gptObjectInit(&GPTD1); #endif #if TIVA_GPT_USE_GPT1 - GPTD2.gpt = GPT1; + GPTD2.gpt = TIMER1_BASE; gptObjectInit(&GPTD2); #endif #if TIVA_GPT_USE_GPT2 - GPTD3.gpt = GPT2; + GPTD3.gpt = TIMER2_BASE; gptObjectInit(&GPTD3); #endif #if TIVA_GPT_USE_GPT3 - GPTD4.gpt = GPT3; + GPTD4.gpt = TIMER3_BASE; gptObjectInit(&GPTD4); #endif #if TIVA_GPT_USE_GPT4 - GPTD5.gpt = GPT4; + GPTD5.gpt = TIMER4_BASE; gptObjectInit(&GPTD5); #endif #if TIVA_GPT_USE_GPT5 - GPTD6.gpt = GPT5; + GPTD6.gpt = TIMER5_BASE; gptObjectInit(&GPTD6); #endif #if TIVA_GPT_USE_WGPT0 - GPTD7.gpt = WGPT0; + GPTD7.gpt = WTIMER0_BASE; gptObjectInit(&GPTD7); #endif #if TIVA_GPT_USE_WGPT1 - GPTD8.gpt = WGPT1; + GPTD8.gpt = WTIMER1_BASE; gptObjectInit(&GPTD8); #endif #if TIVA_GPT_USE_WGPT2 - GPTD9.gpt = WGPT2; + GPTD9.gpt = WTIMER2_BASE; gptObjectInit(&GPTD9); #endif #if TIVA_GPT_USE_WGPT3 - GPTD10.gpt = WGPT3; + GPTD10.gpt = WTIMER3_BASE; gptObjectInit(&GPTD10); #endif #if TIVA_GPT_USE_WGPT4 - GPTD11.gpt = WGPT4; + GPTD11.gpt = WTIMER4_BASE; gptObjectInit(&GPTD11); #endif #if TIVA_GPT_USE_WGPT5 - GPTD12.gpt = WGPT5; + GPTD12.gpt = WTIMER5_BASE; gptObjectInit(&GPTD12); #endif } @@ -461,9 +461,9 @@ void gpt_lld_start(GPTDriver *gptp) /* Clock activation.*/ #if TIVA_GPT_USE_GPT0 if (&GPTD1 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 0); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 0); - while (!(SYSCTL->PRTIMER & (1 << 0))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 0))) ; nvicEnableVector(TIVA_GPT0A_NUMBER, TIVA_GPT_GPT0A_IRQ_PRIORITY); @@ -472,9 +472,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_GPT1 if (&GPTD2 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 1); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 1); - while (!(SYSCTL->PRTIMER & (1 << 1))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 1))) ; nvicEnableVector(TIVA_GPT1A_NUMBER, TIVA_GPT_GPT1A_IRQ_PRIORITY); @@ -483,9 +483,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_GPT2 if (&GPTD3 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 2); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 2); - while (!(SYSCTL->PRTIMER & (1 << 2))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 2))) ; nvicEnableVector(TIVA_GPT2A_NUMBER, TIVA_GPT_GPT2A_IRQ_PRIORITY); @@ -494,9 +494,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_GPT3 if (&GPTD4 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 3); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 3); - while (!(SYSCTL->PRTIMER & (1 << 3))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 3))) ; nvicEnableVector(TIVA_GPT3A_NUMBER, TIVA_GPT_GPT3A_IRQ_PRIORITY); @@ -505,9 +505,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_GPT4 if (&GPTD5 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 4); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 4); - while (!(SYSCTL->PRTIMER & (1 << 4))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 4))) ; nvicEnableVector(TIVA_GPT4A_NUMBER, TIVA_GPT_GPT4A_IRQ_PRIORITY); @@ -516,9 +516,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_GPT5 if (&GPTD6 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 5); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 5); - while (!(SYSCTL->PRTIMER & (1 << 5))) + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 5))) ; nvicEnableVector(TIVA_GPT5A_NUMBER, TIVA_GPT_GPT5A_IRQ_PRIORITY); @@ -527,9 +527,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT0 if (&GPTD7 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 0); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 0); - while (!(SYSCTL->PRWTIMER & (1 << 0))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 0))) ; nvicEnableVector(TIVA_WGPT0A_NUMBER, TIVA_GPT_WGPT0A_IRQ_PRIORITY); @@ -538,9 +538,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT1 if (&GPTD8 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 1); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 1); - while (!(SYSCTL->PRWTIMER & (1 << 1))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 1))) ; nvicEnableVector(TIVA_WGPT1A_NUMBER, TIVA_GPT_WGPT1A_IRQ_PRIORITY); @@ -549,9 +549,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT2 if (&GPTD9 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 2); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 2); - while (!(SYSCTL->PRWTIMER & (1 << 2))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 2))) ; nvicEnableVector(TIVA_WGPT2A_NUMBER, TIVA_GPT_WGPT2A_IRQ_PRIORITY); @@ -560,9 +560,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT3 if (&GPTD10 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 3); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 3); - while (!(SYSCTL->PRWTIMER & (1 << 3))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 3))) ; nvicEnableVector(TIVA_WGPT3A_NUMBER, TIVA_GPT_WGPT3A_IRQ_PRIORITY); @@ -571,9 +571,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT4 if (&GPTD11 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 4); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 4); - while (!(SYSCTL->PRWTIMER & (1 << 4))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 4))) ; nvicEnableVector(TIVA_WGPT4A_NUMBER, TIVA_GPT_WGPT4A_IRQ_PRIORITY); @@ -582,9 +582,9 @@ void gpt_lld_start(GPTDriver *gptp) #if TIVA_GPT_USE_WGPT5 if (&GPTD12 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 5); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5); - while (!(SYSCTL->PRWTIMER & (1 << 5))) + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5))) ; nvicEnableVector(TIVA_WGPT5A_NUMBER, TIVA_GPT_WGPT5A_IRQ_PRIORITY); @@ -593,9 +593,9 @@ void gpt_lld_start(GPTDriver *gptp) } /* Timer configuration.*/ - gptp->gpt->CTL = 0; - gptp->gpt->CFG = GPTM_CFG_CFG_SPLIT; - gptp->gpt->TAPR = ((TIVA_SYSCLK / gptp->config->frequency) - 1); + HWREG(gptp->gpt + TIMER_O_CTL) = 0; + HWREG(gptp->gpt + TIMER_O_CFG) = TIMER_CFG_16_BIT; + HWREG(gptp->gpt + TIMER_O_TAPR) = ((TIVA_SYSCLK / gptp->config->frequency) - 1); } /** @@ -608,91 +608,91 @@ void gpt_lld_start(GPTDriver *gptp) void gpt_lld_stop(GPTDriver *gptp) { if (gptp->state == GPT_READY) { - gptp->gpt->IMR = 0; - gptp->gpt->TAILR = 0; - gptp->gpt->CTL = 0; + HWREG(gptp->gpt + TIMER_O_IMR) = 0; + HWREG(gptp->gpt + TIMER_O_TAILR) = 0; + HWREG(gptp->gpt + TIMER_O_CTL) = 0; #if TIVA_GPT_USE_GPT0 if (&GPTD1 == gptp) { nvicDisableVector(TIVA_GPT0A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 0); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 0); } #endif #if TIVA_GPT_USE_GPT1 if (&GPTD2 == gptp) { nvicDisableVector(TIVA_GPT1A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 1); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 1); } #endif #if TIVA_GPT_USE_GPT2 if (&GPTD3 == gptp) { nvicDisableVector(TIVA_GPT2A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 2); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 2); } #endif #if TIVA_GPT_USE_GPT3 if (&GPTD4 == gptp) { nvicDisableVector(TIVA_GPT3A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 3); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 3); } #endif #if TIVA_GPT_USE_GPT4 if (&GPTD5 == gptp) { nvicDisableVector(TIVA_GPT4A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 4); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 4); } #endif #if TIVA_GPT_USE_GPT5 if (&GPTD6 == gptp) { nvicDisableVector(TIVA_GPT5A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 5); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 5); } #endif #if TIVA_GPT_USE_WGPT0 if (&GPTD7 == gptp) { nvicDisableVector(TIVA_WGPT0A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 0); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 0); } #endif #if TIVA_GPT_USE_WGPT1 if (&GPTD8 == gptp) { nvicDisableVector(TIVA_WGPT1A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 1); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 1); } #endif #if TIVA_GPT_USE_WGPT2 if (&GPTD9 == gptp) { nvicDisableVector(TIVA_WGPT2A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 2); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 2); } #endif #if TIVA_GPT_USE_WGPT3 if (&GPTD10 == gptp) { nvicDisableVector(TIVA_WGPT3A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 3); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 3); } #endif #if TIVA_GPT_USE_WGPT4 if (&GPTD11 == gptp) { nvicDisableVector(TIVA_WGPT4A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 4); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 4); } #endif #if TIVA_GPT_USE_WGPT5 if (&GPTD12 == gptp) { nvicDisableVector(TIVA_WGPT5A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 5); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 5); } #endif } @@ -708,11 +708,11 @@ void gpt_lld_stop(GPTDriver *gptp) */ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { - gptp->gpt->TAILR = interval - 1; - gptp->gpt->ICR = 0xfffffff; - gptp->gpt->IMR = GPTM_IMR_TATOIM; - gptp->gpt->TAMR = GPTM_TAMR_TAMR_PERIODIC | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; - gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; + HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xfffffff; + HWREG(gptp->gpt + TIMER_O_IMR) = TIMER_IMR_TATOIM; + HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_PERIOD | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS; + HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL; } /** @@ -724,9 +724,9 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) */ void gpt_lld_stop_timer(GPTDriver *gptp) { - gptp->gpt->IMR = 0; - gptp->gpt->TAILR = 0; - gptp->gpt->CTL &= ~GPTM_CTL_TAEN; + HWREG(gptp->gpt + TIMER_O_IMR) = 0; + HWREG(gptp->gpt + TIMER_O_TAILR) = 0; + HWREG(gptp->gpt + TIMER_O_CTL) &= ~TIMER_CTL_TAEN; } /** @@ -742,13 +742,13 @@ void gpt_lld_stop_timer(GPTDriver *gptp) */ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { - gptp->gpt->TAMR = GPTM_TAMR_TAMR_ONESHOT | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; - gptp->gpt->TAILR = interval - 1; - gptp->gpt->ICR = 0xffffffff; - gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; - while (!(gptp->gpt->RIS & GPTM_IMR_TATOIM)) + HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_1_SHOT | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS; + HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff; + HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL; + while (!(HWREG(gptp->gpt + TIMER_O_RIS) & TIMER_IMR_TATOIM)) ; - gptp->gpt->ICR = 0xffffffff; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff; } #endif /* HAL_USE_GPT */ diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h index e518e58..88a6809 100644 --- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h @@ -405,7 +405,7 @@ struct GPTDriver { /** * @brief Pointer to the GPT registers block. */ - GPT_TypeDef *gpt; + uint32_t gpt; }; /*===========================================================================*/ @@ -426,7 +426,7 @@ struct GPTDriver { * @notapi */ #define gpt_lld_change_interval(gptp, interval) { \ - gptp->gpt->TAILR = interval - 1; \ + HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; \ } /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c index 30fdb8a..d87652b 100644 --- a/os/hal/ports/TIVA/LLD/hal_st_lld.c +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c @@ -67,8 +67,8 @@ #elif TIVA_ST_TIMER_NUMBER == 5 #define ST_HANDLER TIVA_WGPT5A_HANDLER #define ST_NUMBER TIVA_WGPT5A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 5)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 5))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5))) #else #error "TIVA_ST_USE_TIMER specifies an unsupported timer" @@ -184,10 +184,10 @@ OSAL_IRQ_HANDLER(ST_HANDLER) OSAL_IRQ_PROLOGUE(); - mis = TIVA_ST_TIM->MIS; - TIVA_ST_TIM->ICR = mis; + mis = HWREG(TIVA_ST_TIM + TIMER_O_MIS); + HWREG(TIVA_ST_TIM + TIMER_O_ICR) = mis; - if (mis & GPTM_IMR_TAMIM) { + if (mis & TIMER_IMR_TAMIM) { osalSysLockFromISR(); osalOsTimerHandlerI(); osalSysUnlockFromISR(); @@ -218,15 +218,17 @@ void st_lld_init(void) ST_WAIT_CLOCK(); /* Initializing the counter in free running down mode.*/ - TIVA_ST_TIM->CTL = 0; - TIVA_ST_TIM->CFG = GPTM_CFG_CFG_SPLIT; /* Timer split mode */ - TIVA_ST_TIM->TAMR = (GPTM_TAMR_TAMR_PERIODIC |/* Periodic mode */ - GPTM_TAMR_TAMIE | /* Match interrupt enable */ - GPTM_TAMR_TASNAPS); /* Snapshot mode */ - - TIVA_ST_TIM->TAPR = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; - TIVA_ST_TIM->CTL = (GPTM_CTL_TAEN | /* Timer A enable */ - GPTM_CTL_TASTALL); /* Timer A stall when paused */ + HWREG(TIVA_ST_TIM + TIMER_O_CTL) = 0; + HWREG(TIVA_ST_TIM + TIMER_O_CFG) = TIMER_CFG_16_BIT; /* Timer split mode */ + HWREG(TIVA_ST_TIM + TIMER_O_TAMR) = ( + TIMER_TAMR_TAMR_PERIOD | /* Periodic mode */ + TIMER_TAMR_TAMIE | /* Match interrupt enable */ + TIMER_TAMR_TASNAPS); /* Snapshot mode */ + + HWREG(TIVA_ST_TIM + TIMER_O_TAPR) = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; + HWREG(TIVA_ST_TIM + TIMER_O_CTL) = ( + TIMER_CTL_TAEN | /* Timer A enable */ + TIMER_CTL_TASTALL); /* Timer A stall when paused */ /* IRQ enabled.*/ nvicEnableVector(ST_NUMBER, TIVA_ST_IRQ_PRIORITY); diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h index 35bf008..cd076d6 100644 --- a/os/hal/ports/TIVA/LLD/hal_st_lld.h +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h @@ -29,7 +29,6 @@ #include "mcuconf.h" #include "tiva_registry.h" -#include "tiva_gpt.h" /*===========================================================================*/ /* Driver constants. */ @@ -82,37 +81,37 @@ #if !TIVA_HAS_WGPT0 #error "WGPT0 not present" #endif -#define TIVA_ST_TIM WGPT0 +#define TIVA_ST_TIM WTIMER0_BASE #elif TIVA_ST_TIMER_NUMBER == 1 #if !TIVA_HAS_WGPT1 #error "WGPT1 not present" #endif -#define TIVA_ST_TIM WGPT1 +#define TIVA_ST_TIM WTIMER1_BASE #elif TIVA_ST_TIMER_NUMBER == 2 #if !TIVA_HAS_WGPT2 #error "WGPT2 not present" #endif -#define TIVA_ST_TIM WGPT2 +#define TIVA_ST_TIM WTIMER2_BASE #elif TIVA_ST_TIMER_NUMBER == 3 #if !TIVA_HAS_WGPT3 #error "WGPT3 not present" #endif -#define TIVA_ST_TIM WGPT3 +#define TIVA_ST_TIM WTIMER3_BASE #elif TIVA_ST_TIMER_NUMBER == 4 #if !TIVA_HAS_WGPT4 #error "WGPT4 not present" #endif -#define TIVA_ST_TIM WGPT4 +#define TIVA_ST_TIM WTIMER4_BASE #elif TIVA_ST_TIMER_NUMBER == 5 #if !TIVA_HAS_WGPT5 #error "WGPT5 not present" #endif -#define TIVA_ST_TIM WGPT5 +#define TIVA_ST_TIM WTIMER5_BASE #else #error "TIVA_ST_USE_TIMER specifies an unsupported timer" @@ -124,37 +123,37 @@ #if !TIVA_HAS_GPT0 #error "GPT0 not present" #endif -#define TIVA_ST_TIM GPT0 +#define TIVA_ST_TIM TIMER0_BASE #elif TIVA_ST_TIMER_NUMBER == 1 #if !TIVA_HAS_GPT1 #error "GPT1 not present" #endif -#define TIVA_ST_TIM GPT1 +#define TIVA_ST_TIM TIMER1_BASE #elif TIVA_ST_TIMER_NUMBER == 2 #if !TIVA_HAS_GPT2 #error "GPT2 not present" #endif -#define TIVA_ST_TIM GPT2 +#define TIVA_ST_TIM TIMER2_BASE #elif TIVA_ST_TIMER_NUMBER == 3 #if !TIVA_HAS_GPT3 #error "GPT3 not present" #endif -#define TIVA_ST_TIM GPT3 +#define TIVA_ST_TIM TIMER3_BASE #elif TIVA_ST_TIMER_NUMBER == 4 #if !TIVA_HAS_GPT4 #error "GPT4 not present" #endif -#define TIVA_ST_TIM GPT4 +#define TIVA_ST_TIM TIMER4_BASE #elif TIVA_ST_TIMER_NUMBER == 5 #if !TIVA_HAS_GPT5 #error "GPT5 not present" #endif -#define TIVA_ST_TIM GPT5 +#define TIVA_ST_TIM TIMER5_BASE #else #error "TIVA_ST_TIMER_NUMBER specifies an unsupported timer" @@ -164,11 +163,6 @@ #error "wrong value defined for TIVA_ST_USE_WIDE_TIMER" #endif -#if OSAL_ST_MODE != OSAL_ST_MODE_NONE && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ST" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -202,7 +196,7 @@ extern "C" { */ static inline systime_t st_lld_get_counter(void) { - return (systime_t) (((systime_t) 0xffffffff) - TIVA_ST_TIM->TAR); + return (systime_t) (((systime_t) 0xffffffff) - HWREG(TIVA_ST_TIM + TIMER_O_TAV)); } /** @@ -216,9 +210,9 @@ static inline systime_t st_lld_get_counter(void) */ static inline void st_lld_start_alarm(systime_t time) { - TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); - TIVA_ST_TIM->ICR = TIVA_ST_TIM->MIS; - TIVA_ST_TIM->IMR = GPTM_IMR_TAMIM; + HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time); + HWREG(TIVA_ST_TIM + TIMER_O_ICR) = HWREG(TIVA_ST_TIM + TIMER_O_MIS); + HWREG(TIVA_ST_TIM + TIMER_O_IMR) = TIMER_IMR_TAMIM; } /** @@ -228,7 +222,7 @@ static inline void st_lld_start_alarm(systime_t time) */ static inline void st_lld_stop_alarm(void) { - TIVA_ST_TIM->IMR = 0; + HWREG(TIVA_ST_TIM + TIMER_O_IMR) = 0; } /** @@ -240,7 +234,7 @@ static inline void st_lld_stop_alarm(void) */ static inline void st_lld_set_alarm(systime_t time) { - TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); + HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time); } /** @@ -252,7 +246,7 @@ static inline void st_lld_set_alarm(systime_t time) */ static inline systime_t st_lld_get_alarm(void) { - return (systime_t) (((systime_t)0xffffffff) - TIVA_ST_TIM->TAMATCHR); + return (systime_t) (((systime_t)0xffffffff) - HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR)); } /** @@ -266,7 +260,7 @@ static inline systime_t st_lld_get_alarm(void) */ static inline bool st_lld_is_alarm_active(void) { - return (bool) ((TIVA_ST_TIM->IMR & GPTM_IMR_TAMIM) !=0); + return (bool) ((HWREG(TIVA_ST_TIM + TIMER_O_IMR) & TIMER_IMR_TAMIM) !=0); } #endif /* HAL_ST_LLD_H */ diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c index cb69861..cf70dca 100644 --- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c @@ -30,6 +30,33 @@ /* Driver local definitions. */ /*===========================================================================*/ +// interrupt states +#define STATE_IDLE 0 +#define STATE_WRITE_NEXT 1 +#define STATE_WRITE_FINAL 2 +#define STATE_WAIT_ACK 3 +#define STATE_SEND_ACK 4 +#define STATE_READ_ONE 5 +#define STATE_READ_FIRST 6 +#define STATE_READ_NEXT 7 +#define STATE_READ_FINAL 8 +#define STATE_READ_WAIT 9 + +#define TIVA_I2C_SIGNLE_SEND (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_START (I2C_MCS_RUN | I2C_MCS_START) +#define TIVA_I2C_BURST_SEND_CONTINUE (I2C_MCS_RUN) +#define TIVA_I2C_BURST_SEND_FINISH (I2C_MCS_RUN | I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_STOP (I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_ERROR_STOP (I2C_MCS_STOP) + +#define TIVA_I2C_SINGLE_RECEIVE (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP) +#define TIVA_I2C_BURST_RECEIVE_START (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_ACK) +#define TIVA_I2C_BURST_RECEIVE_CONTINUE (I2C_MCS_RUN | I2C_MCS_ACK) +#define TIVA_I2C_BURST_RECEIVE_FINISH (I2C_MCS_RUN | I2C_MCS_STOP) +#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (I2C_MCS_STOP) + +#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1) + /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -125,19 +152,19 @@ I2CDriver I2CD10; */ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; uint32_t status; // clear MIS bit in MICR by writing 1 - dp->MICR = 1; + HWREG(i2c + I2C_O_MICR) = 1; // read interrupt status - status = dp->MCS; + status = HWREG(i2c + I2C_O_MCS); - if (status & TIVA_MCS_ERROR) { + if (status & I2C_MCS_ERROR) { i2cp->errors |= I2C_BUS_ERROR; } - if (status & TIVA_MCS_ARBLST) { + if (status & I2C_MCS_ARBLST) { i2cp->errors |= I2C_ARBITRATION_LOST; } @@ -152,11 +179,11 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) if (i2cp->txbytes == 1) { i2cp->intstate = STATE_WRITE_FINAL; } - dp->MDR = *(i2cp->txbuf); + HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf); i2cp->txbuf++; i2cp->txbytes--; // start transmission - dp->MCS = TIVA_I2C_BURST_SEND_CONTINUE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_CONTINUE; break; } case STATE_WRITE_FINAL: { @@ -169,12 +196,12 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) else { i2cp->intstate = STATE_READ_FIRST; } - dp->MDR = *(i2cp->txbuf); + HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf); i2cp->txbuf++; // txbytes - 1 i2cp->txbytes--; // start transmission - dp->MCS = TIVA_I2C_BURST_SEND_FINISH; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_FINISH; break; } case STATE_WAIT_ACK: { @@ -189,10 +216,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) i2cp->addr |= 1; // set slave address - dp->MSA = i2cp->addr; - i2cp->rxbytes--; + HWREG(i2c + I2C_O_MSA) = i2cp->addr; + i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_SINGLE_RECEIVE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE; break; } @@ -208,10 +235,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) i2cp->addr |= 1; // set slave address - dp->MSA = i2cp->addr; - i2cp->rxbytes--; + HWREG(i2c + I2C_O_MSA) = i2cp->addr; + i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_START; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_START; break; } @@ -219,27 +246,27 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) if(i2cp->rxbytes == 2) { i2cp->intstate = STATE_READ_FINAL; } - *(i2cp->rxbuf) = dp->MDR; + *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR); i2cp->rxbuf++; i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_CONTINUE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_CONTINUE; break; } case STATE_READ_FINAL: { i2cp->intstate = STATE_READ_WAIT; - *(i2cp->rxbuf) = dp->MDR; + *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR); i2cp->rxbuf++; - i2cp->rxbytes--; + i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_FINISH; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_FINISH; break; } case STATE_READ_WAIT: { i2cp->intstate = STATE_IDLE; - *(i2cp->rxbuf) = dp->MDR; + *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR); i2cp->rxbuf++; _i2c_wakeup_isr(i2cp); break; @@ -430,61 +457,61 @@ void i2c_lld_init(void) { #if TIVA_I2C_USE_I2C0 i2cObjectInit(&I2CD1); I2CD1.thread = NULL; - I2CD1.i2c = I2C0; + I2CD1.i2c = I2C0_BASE; #endif /* TIVA_I2C_USE_I2C0 */ #if TIVA_I2C_USE_I2C1 i2cObjectInit(&I2CD2); I2CD2.thread = NULL; - I2CD2.i2c = I2C1; + I2CD2.i2c = I2C1_BASE; #endif /* TIVA_I2C_USE_I2C1 */ #if TIVA_I2C_USE_I2C2 i2cObjectInit(&I2CD3); I2CD3.thread = NULL; - I2CD3.i2c = I2C2; + I2CD3.i2c = I2C2_BASE; #endif /* TIVA_I2C_USE_I2C2 */ #if TIVA_I2C_USE_I2C3 i2cObjectInit(&I2CD4); I2CD4.thread = NULL; - I2CD4.i2c = I2C3; + I2CD4.i2c = I2C3_BASE; #endif /* TIVA_I2C_USE_I2C3 */ #if TIVA_I2C_USE_I2C4 i2cObjectInit(&I2CD5); I2CD5.thread = NULL; - I2CD5.i2c = I2C4; + I2CD5.i2c = I2C4_BASE; #endif /* TIVA_I2C_USE_I2C4 */ #if TIVA_I2C_USE_I2C5 i2cObjectInit(&I2CD6); I2CD6.thread = NULL; - I2CD6.i2c = I2C5; + I2CD6.i2c = I2C5_BASE; #endif /* TIVA_I2C_USE_I2C5 */ #if TIVA_I2C_USE_I2C6 i2cObjectInit(&I2CD7); I2CD7.thread = NULL; - I2CD7.i2c = I2C6; + I2CD7.i2c = I2C6_BASE; #endif /* TIVA_I2C_USE_I2C6 */ #if TIVA_I2C_USE_I2C7 i2cObjectInit(&I2CD8); I2CD8.thread = NULL; - I2CD8.i2c = I2C7; + I2CD8.i2c = I2C7_BASE; #endif /* TIVA_I2C_USE_I2C7 */ #if TIVA_I2C_USE_I2C8 i2cObjectInit(&I2CD9); I2CD9.thread = NULL; - I2CD9.i2c = I2C8; + I2CD9.i2c = I2C8_BASE; #endif /* TIVA_I2C_USE_I2C8 */ #if TIVA_I2C_USE_I2C9 i2cObjectInit(&I2CD10); I2CD10.thread = NULL; - I2CD10.i2c = I2C9; + I2CD10.i2c = I2C9_BASE; #endif /* TIVA_I2C_USE_I2C9 */ } @@ -497,15 +524,15 @@ void i2c_lld_init(void) { */ void i2c_lld_start(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; /* If in stopped state then enables the I2C clocks.*/ if (i2cp->state == I2C_STOP) { #if TIVA_I2C_USE_I2C0 if (&I2CD1 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 0); + HWREG(SYSCTL_RCGCI2C) |= (1 << 0); - while (!(SYSCTL->PRI2C & (1 << 0))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 0))) ; nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY); @@ -514,9 +541,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C1 if (&I2CD2 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 1); + HWREG(SYSCTL_RCGCI2C) |= (1 << 1); - while (!(SYSCTL->PRI2C & (1 << 1))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 1))) ; nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY); @@ -525,9 +552,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C2 if (&I2CD3 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 2); + HWREG(SYSCTL_RCGCI2C) |= (1 << 2); - while (!(SYSCTL->PRI2C & (1 << 2))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 2))) ; nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY); @@ -536,9 +563,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C3 if (&I2CD4 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 3); + HWREG(SYSCTL_RCGCI2C) |= (1 << 3); - while (!(SYSCTL->PRI2C & (1 << 3))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 3))) ; nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY); @@ -547,9 +574,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C4 if (&I2CD5 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 4); + HWREG(SYSCTL_RCGCI2C) |= (1 << 4); - while (!(SYSCTL->PRI2C & (1 << 4))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 4))) ; nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY); @@ -558,9 +585,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C5 if (&I2CD6 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 5); + HWREG(SYSCTL_RCGCI2C) |= (1 << 5); - while (!(SYSCTL->PRI2C & (1 << 5))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 5))) ; nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY); @@ -569,9 +596,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C6 if (&I2CD7 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 6); + HWREG(SYSCTL_RCGCI2C) |= (1 << 6); - while (!(SYSCTL->PRI2C & (1 << 6))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 6))) ; nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY); @@ -580,9 +607,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C7 if (&I2CD8 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 7); + HWREG(SYSCTL_RCGCI2C) |= (1 << 7); - while (!(SYSCTL->PRI2C & (1 << 7))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 7))) ; nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY); @@ -591,9 +618,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C8 if (&I2CD9 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 8); + HWREG(SYSCTL_RCGCI2C) |= (1 << 8); - while (!(SYSCTL->PRI2C & (1 << 8))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 8))) ; nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY); @@ -602,9 +629,9 @@ void i2c_lld_start(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C9 if (&I2CD10 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 9); + HWREG(SYSCTL_RCGCI2C) |= (1 << 9); - while (!(SYSCTL->PRI2C & (1 << 9))) + while (!(HWREG(SYSCTL_PRI2C) & (1 << 9))) ; nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY); @@ -612,8 +639,8 @@ void i2c_lld_start(I2CDriver *i2cp) #endif /* TIVA_I2C_USE_I2C7 */ } - dp->MCR = 0x10; - dp->MTPR = MTPR_VALUE; + HWREG(i2c + I2C_O_MCR) = 0x10; + HWREG(i2c + I2C_O_MTPR) = MTPR_VALUE; } /** @@ -625,7 +652,8 @@ void i2c_lld_start(I2CDriver *i2cp) */ void i2c_lld_stop(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; + /* If not in stopped state then disables the I2C clock.*/ if (i2cp->state != I2C_STOP) { @@ -635,76 +663,76 @@ void i2c_lld_stop(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C0 if (&I2CD1 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 0); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 0); nvicDisableVector(TIVA_I2C0_NUMBER); } #endif /* TIVA_I2C_USE_I2C0 */ #if TIVA_I2C_USE_I2C1 if (&I2CD2 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 1); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 1); nvicDisableVector(TIVA_I2C1_NUMBER); } #endif /* TIVA_I2C_USE_I2C1 */ #if TIVA_I2C_USE_I2C2 if (&I2CD3 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 2); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 2); nvicDisableVector(TIVA_I2C2_NUMBER); } #endif /* TIVA_I2C_USE_I2C2 */ #if TIVA_I2C_USE_I2C3 if (&I2CD4 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 3); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 3); nvicDisableVector(TIVA_I2C3_NUMBER); } #endif /* TIVA_I2C_USE_I2C3 */ #if TIVA_I2C_USE_I2C4 if (&I2CD5 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 4); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 4); nvicDisableVector(TIVA_I2C4_NUMBER); } #endif /* TIVA_I2C_USE_I2C4 */ #if TIVA_I2C_USE_I2C5 if (&I2CD6 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 5); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 5); nvicDisableVector(TIVA_I2C5_NUMBER); } #endif /* TIVA_I2C_USE_I2C5 */ #if TIVA_I2C_USE_I2C6 if (&I2CD7 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 6); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 6); nvicDisableVector(TIVA_I2C6_NUMBER); } #endif /* TIVA_I2C_USE_I2C6 */ #if TIVA_I2C_USE_I2C7 if (&I2CD8 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 7); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 7); nvicDisableVector(TIVA_I2C7_NUMBER); } #endif /* TIVA_I2C_USE_I2C7 */ #if TIVA_I2C_USE_I2C8 if (&I2CD9 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 8); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 8); nvicDisableVector(TIVA_I2C8_NUMBER); } #endif /* TIVA_I2C_USE_I2C8 */ #if TIVA_I2C_USE_I2C9 if (&I2CD10 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 9); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 9); nvicDisableVector(TIVA_I2C9_NUMBER); } #endif /* TIVA_I2C_USE_I2C9 */ - dp->MCR = 0; - dp->MTPR = 0; + HWREG(i2c + I2C_O_MCR) = 0; + HWREG(i2c + I2C_O_MTPR) = 0; } } @@ -733,7 +761,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; systime_t start, end; i2cp->rxbuf = rxbuf; @@ -759,7 +787,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if ((dp->MCS & TIVA_MCS_BUSY) == 0) + if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0) break; /* If the system time went outside the allowed window then a timeout @@ -771,10 +799,10 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, } /* set slave address */ - dp->MSA = addr; + HWREG(i2c + I2C_O_MSA) = addr; /* Starts the operation.*/ - dp->MCS = TIVA_I2C_SINGLE_RECEIVE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE; /* Waits for the operation completion or a timeout.*/ return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); @@ -808,7 +836,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; systime_t start, end; i2cp->rxbuf = rxbuf; @@ -833,7 +861,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if ((dp->MCS & TIVA_MCS_BUSY) == 0) + if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0) break; /* If the system time went outside the allowed window then a timeout @@ -848,13 +876,13 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->addr = addr << 1 | 0; /* set slave address */ - dp->MSA = i2cp->addr; + HWREG(i2c + I2C_O_MSA) = i2cp->addr; /* enable interrupts */ - dp->MIMR = TIVA_MIMR_IM; + HWREG(i2c + I2C_O_MIMR) = I2C_MIMR_IM; /* put data in register */ - dp->MDR = *(i2cp->txbuf); + HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf); /* check if 1 or more bytes */ if (i2cp->txbytes == 1) { @@ -867,7 +895,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->intstate = STATE_READ_FIRST; } // single byte send - dp->MCS = TIVA_I2C_SIGNLE_SEND; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SIGNLE_SEND; } else { if (i2cp->txbytes == 2) { @@ -879,7 +907,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->intstate = STATE_WRITE_NEXT; } // multiple bytes start send - dp->MCS = TIVA_I2C_BURST_SEND_START; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_START; } i2cp->txbuf++; diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h index 460d231..4eabda8 100644 --- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h @@ -31,80 +31,6 @@ /* Driver constants. */ /*===========================================================================*/ -#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1) - -#define TIVA_MSA_RS (1 << 0) -#define TIVA_MSA_SA (127 << 1) - -#define TIVA_MCS_BUSY (1 << 0) -#define TIVA_MCS_ERROR (1 << 1) -#define TIVA_MCS_ADRACK (1 << 2) -#define TIVA_MCS_DATACK (1 << 3) -#define TIVA_MCS_ARBLST (1 << 4) -#define TIVA_MCS_IDLE (1 << 5) -#define TIVA_MCS_BUSBSY (1 << 6) -#define TIVA_MCS_CLKTO (1 << 7) - -#define TIVA_MCS_RUN (1 << 0) -#define TIVA_MCS_START (1 << 1) -#define TIVA_MCS_STOP (1 << 2) -#define TIVA_MCS_ACK (1 << 3) -#define TIVA_MCS_HS (1 << 4) - -#define TIVA_I2C_SIGNLE_SEND (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_START (TIVA_MCS_RUN | TIVA_MCS_START) -#define TIVA_I2C_BURST_SEND_CONTINUE (TIVA_MCS_RUN) -#define TIVA_I2C_BURST_SEND_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_STOP (TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_I2C_SINGLE_RECEIVE (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_START (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_CONTINUE (TIVA_MCS_RUN | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_MDR_DATA (255 << 0) - -#define TIVA_MTPR_TPR (127 << 0) -#define TIVA_MTPR_HS (1 << 7) - -#define TIVA_MIMR_IM (1 << 0) -#define TIVA_MIMR_CLKIM (1 << 1) - -#define TIVA_MRIS_RIS (1 << 0) -#define TIVA_MRIS_CLKRIS (1 << 1) - -#define TIVA_MMIS_MIS (1 << 0) -#define TIVA_MMIS_CLKMIS (1 << 1) - -#define TIVA_MICR_IC (1 << 0) -#define TIVA_MICR_CLKIC (1 << 1) - -#define TIVA_MCR_LPBK (1 << 0) -#define TIVA_MCR_MFE (1 << 4) -#define TIVA_MCR_SFE (1 << 5) -#define TIVA_MCR_GFE (1 << 6) - -#define TIVA_MCLKOCNT_CNTL (255 << 0) - -#define TIVA_MBMON_SCL (1 << 0) -#define TIVA_MBMON_SDA (1 << 1) - -#define TIVA_MCR2_GFPW (7 << 4) - -// interrupt states -#define STATE_IDLE 0 -#define STATE_WRITE_NEXT 1 -#define STATE_WRITE_FINAL 2 -#define STATE_WAIT_ACK 3 -#define STATE_SEND_ACK 4 -#define STATE_READ_ONE 5 -#define STATE_READ_FIRST 6 -#define STATE_READ_NEXT 7 -#define STATE_READ_FINAL 8 -#define STATE_READ_WAIT 9 - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -440,7 +366,7 @@ struct I2CDriver { /** * @brief Pointer to the I2Cx registers block. */ - I2C_TypeDef *i2c; + uint32_t i2c; }; /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.c b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c index 04177b6..cf64bbb 100644 --- a/os/hal/ports/TIVA/LLD/hal_mac_lld.c +++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c @@ -89,10 +89,10 @@ static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]; */ static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) { - ETH->MIIDATA = value; - ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB; + HWREG(EMAC_O_MIIDATA) = value; + HWREG(EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB; - while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) + while ((HWREG(EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0) ; } @@ -126,12 +126,12 @@ static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value) */ static uint32_t mii_read(MACDriver *macp, uint32_t reg) { - ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB; + HWREG(EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB; - while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) + while ((HWREG(EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0) ; - return ETH->MIIDATA; + return HWREG(EMAC_O_MIIDATA); } /** @@ -171,7 +171,7 @@ static void mii_find_phy(MACDriver *macp) #endif for (i = 0; i < 31; i++) { macp->phyaddr = i << 11; - ETH->MIIDATA = (i << 6) | MACMIIADDR_CR; + HWREG(EMAC_O_MIIDATA) = (i << 6) | MACMIIADDR_CR; if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) && ((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { return; @@ -196,20 +196,20 @@ static void mac_lld_set_address(const uint8_t *p) { /* MAC address configuration, only a single address comparator is used, hash table not used.*/ - ETH->ADDR0H = ((uint32_t)p[5] << 8) | + HWREG(EMAC_O_ADDR0H) = ((uint32_t)p[5] << 8) | ((uint32_t)p[4] << 0); - ETH->ADDR0L = ((uint32_t)p[3] << 24) | + HWREG(EMAC_O_ADDR0L) = ((uint32_t)p[3] << 24) | ((uint32_t)p[2] << 16) | ((uint32_t)p[1] << 8) | ((uint32_t)p[0] << 0); - ETH->ADDR1H = 0x0000FFFF; - ETH->ADDR1L = 0xFFFFFFFF; - ETH->ADDR2H = 0x0000FFFF; - ETH->ADDR2L = 0xFFFFFFFF; - ETH->ADDR3H = 0x0000FFFF; - ETH->ADDR3L = 0xFFFFFFFF; - ETH->HASHTBLH = 0; - ETH->HASHTBLL = 0; + HWREG(EMAC_O_ADDR1H) = 0x0000FFFF; + HWREG(EMAC_O_ADDR1L) = 0xFFFFFFFF; + HWREG(EMAC_O_ADDR2H) = 0x0000FFFF; + HWREG(EMAC_O_ADDR2L) = 0xFFFFFFFF; + HWREG(EMAC_O_ADDR3H) = 0x0000FFFF; + HWREG(EMAC_O_ADDR3L) = 0xFFFFFFFF; + HWREG(EMAC_O_HASHTBLH) = 0; + HWREG(EMAC_O_HASHTBLL) = 0; } /*===========================================================================*/ @@ -222,8 +222,8 @@ CH_IRQ_HANDLER(TIVA_MAC_HANDLER) CH_IRQ_PROLOGUE(); - dmaris = ETH->DMARIS; - ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/ + dmaris = HWREG(EMAC_O_DMARIS); + HWREG(EMAC_O_DMARIS) = dmaris & 0x0001FFFF; /* Clear status bits.*/ if (dmaris & (1 << 6)) { /* Data Received.*/ @@ -275,26 +275,26 @@ void mac_lld_init(void) } /* Enable MAC clock */ - SYSCTL->RCGCEMAC = 1; - while (SYSCTL->PREMAC != 0x01) + HWREG(SYSCTL_RCGCEMAC) = 1; + while (HWREG(SYSCTL_PREMAC) != 0x01) ; /* Set PHYHOLD bit */ - ETH->PC |= 1; + HWREG(EMAC_O_PC) |= 1; /* Enable PHY clock */ - SYSCTL->RCGCEPHY = 1; - while (SYSCTL->PREPHY != 0x01) + HWREG(SYSCTL_RCGCEPHY) = 1; + while (HWREG(SYSCTL_PREPHY) != 0x01) ; /* Enable power to PHY */ - SYSCTL->PCEPHY |= 1; - while (SYSCTL->PREPHY != 0x01) + HWREG(SYSCTL_PCEPHY) |= 1; + while (HWREG(SYSCTL_PREPHY) != 0x01) ; #if BOARD_PHY_RMII - ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28); + HWREG(EMAC_O_PC) = EMAC_PHY_CONFIG | (0x04 << 28); #else - ETH->PC = EMAC_PHY_CONFIG; + HWREG(EMAC_O_PC) = EMAC_PHY_CONFIG; #endif /* @@ -310,12 +310,12 @@ void mac_lld_init(void) /* Set done bit after writing EMACPC register */ mii_write(ÐD1, TIVA_CFG1, (1 << 15) | mii_read(ÐD1, TIVA_CFG1)); - while(ETH->DMABUSMOD & 1) + while(HWREG(EMAC_O_DMABUSMOD) & 1) ; /* Reset MAC */ - ETH->DMABUSMOD |= 1; - while (ETH->DMABUSMOD & 1) + HWREG(EMAC_O_DMABUSMOD) |= 1; + while (HWREG(EMAC_O_DMABUSMOD) & 1) ; /* PHY address setup.*/ @@ -344,10 +344,10 @@ void mac_lld_init(void) #endif /* Disable MAC clock */ - SYSCTL->RCGCEMAC = 0; + HWREG(SYSCTL_RCGCEMAC) = 0; /* Disable PHY clock */ - SYSCTL->RCGCEPHY = 0; + HWREG(SYSCTL_RCGCEPHY) = 0; } /** @@ -374,13 +374,13 @@ void mac_lld_start(MACDriver *macp) macp->txptr = (tiva_eth_tx_descriptor_t *)td; /* Enable MAC clock */ - SYSCTL->RCGCEMAC = 1; - while (SYSCTL->PREMAC != 0x01) + HWREG(SYSCTL_RCGCEMAC) = 1; + while (HWREG(SYSCTL_PREMAC) != 0x01) ; /* Enable PHY clock */ - SYSCTL->RCGCEPHY = 1; - while (!SYSCTL->PREPHY) + HWREG(SYSCTL_RCGCEPHY) = 1; + while (!HWREG(SYSCTL_PREPHY)) ; /* ISR vector enabled.*/ @@ -392,9 +392,9 @@ void mac_lld_start(MACDriver *macp) #endif /* MAC configuration.*/ - ETH->FRAMEFLTR = 0; - ETH->FLOWCTL = 0; - ETH->VLANTG = 0; + HWREG(EMAC_O_FRAMEFLTR) = 0; + HWREG(EMAC_O_FLOWCTL) = 0; + HWREG(EMAC_O_VLANTG) = 0; /* MAC address setup.*/ if (macp->config->mac_address == NULL) @@ -406,30 +406,30 @@ void mac_lld_start(MACDriver *macp) Note that the complete setup of the MAC is performed when the link status is detected.*/ #if TIVA_MAC_IP_CHECKSUM_OFFLOAD - ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2); + HWREG(EMAC_O_CFG) = (1 << 10) | (1 << 3) | (1 << 2); #else - ETH->CFG = (1 << 3) | (1 << 2); + HWREG(EMAC_O_CFG) = (1 << 3) | (1 << 2); #endif /* DMA configuration: Descriptor chains pointers.*/ - ETH->RXDLADDR = (uint32_t)rd; - ETH->TXDLADDR = (uint32_t)td; + HWREG(EMAC_O_RXDLADDR) = (uint32_t)rd; + HWREG(EMAC_O_TXDLADDR) = (uint32_t)td; /* Enabling required interrupt sources.*/ - ETH->DMARIS &= 0xFFFF; - ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0); + HWREG(EMAC_O_DMARIS) &= 0xFFFF; + HWREG(EMAC_O_DMAIM) = (1 << 16) | (1 << 6) | (1 << 0); /* DMA general settings.*/ - ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8); + HWREG(EMAC_O_DMABUSMOD) = (1 << 25) | (1 << 17) | (1 << 8); /* Transmit FIFO flush.*/ - ETH->DMAOPMODE = (1 << 20); - while (ETH->DMAOPMODE & (1 << 20)) + HWREG(EMAC_O_DMAOPMODE) = (1 << 20); + while (HWREG(EMAC_O_DMAOPMODE) & (1 << 20)) ; /* DMA final configuration and start.*/ - ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) | + HWREG(EMAC_O_DMAOPMODE) = (1 << 26) | (1 << 25) | (1 << 21) | (1 << 13) | (1 << 1); } @@ -449,16 +449,16 @@ void mac_lld_stop(MACDriver *macp) #endif /* MAC and DMA stopped.*/ - ETH->CFG = 0; - ETH->DMAOPMODE = 0; - ETH->DMAIM = 0; - ETH->DMARIS &= 0xFFFF; + HWREG(EMAC_O_CFG) = 0; + HWREG(EMAC_O_DMAOPMODE) = 0; + HWREG(EMAC_O_DMAIM) = 0; + HWREG(EMAC_O_DMARIS) &= 0xFFFF; /* MAC clocks stopped.*/ - SYSCTL->RCGCEMAC = 0; + HWREG(SYSCTL_RCGCEMAC) = 0; /* PHY clock stopped.*/ - SYSCTL->RCGCEPHY = 0; + HWREG(SYSCTL_RCGCEPHY) = 0; /* ISR vector disabled.*/ nvicDisableVector(TIVA_MAC_NUMBER); @@ -537,9 +537,9 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) tdp->physdesc->locked = 0; /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) { - ETH->DMARIS = (1 << 2); - ETH->TXPOLLD = 1; /* Any value is OK.*/ + if ((HWREG(EMAC_O_DMARIS) & (0x7 << 20)) == (6 << 20)) { + HWREG(EMAC_O_DMARIS) = (1 << 2); + HWREG(EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/ } osalSysUnlock(); @@ -616,9 +616,9 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) rdp->physdesc->rdes0 = TIVA_RDES0_OWN; /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) { - ETH->DMARIS = (1 << 7); - ETH->TXPOLLD = 1; /* Any value is OK.*/ + if ((HWREG(EMAC_O_STATUS) & (0xf << 17)) == (4 << 17)) { + HWREG(EMAC_O_DMARIS) = (1 << 7); + HWREG(EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/ } osalSysUnlock(); @@ -638,7 +638,7 @@ bool mac_lld_poll_link_status(MACDriver *macp) { uint32_t maccfg, bmsr, bmcr; - maccfg = ETH->CFG; + maccfg = HWREG(EMAC_O_CFG); /* PHY CR and SR registers read.*/ (void)mii_read(macp, MII_BMSR); @@ -688,7 +688,7 @@ bool mac_lld_poll_link_status(MACDriver *macp) } /* Changes the mode in the MAC.*/ - ETH->CFG = maccfg; + HWREG(EMAC_O_CFG) = maccfg; /* Returns the link status.*/ return macp->link_up = true; diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.h b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h index 98036bb..98036bb 100644 --- a/os/hal/ports/TIVA/LLD/hal_mac_lld.h +++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c index ad7c587..964f45b 100644 --- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c +++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c @@ -30,13 +30,6 @@ /* Driver local definitions. */ /*===========================================================================*/ -#define PWM_INT_CMPBD (1 << 5) -#define PWM_INT_CMPBU (1 << 4) -#define PWM_INT_CMPAD (1 << 3) -#define PWM_INT_CMPAU (1 << 2) -#define PWM_INT_CNTLOAD (1 << 1) -#define PWM_INT_CNTZERO (1 << 0) - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -59,6 +52,8 @@ PWMDriver PWMD2; /* Driver local variables and types. */ /*===========================================================================*/ +static uint32_t pwm_generator_offsets[] = { PWM_GEN_0_OFFSET, PWM_GEN_1_OFFSET, PWM_GEN_2_OFFSET, PWM_GEN_3_OFFSET}; + /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ @@ -75,35 +70,36 @@ PWMDriver PWMD2; static void pwm_lld_serve_generator_interrupt (PWMDriver *pwmp, uint8_t i) { uint32_t isc; + uint32_t pwm = pwmp->pwm; - isc = pwmp->pwm->PWM[i].ISC; - pwmp->pwm->PWM[i].ISC = isc; + isc = HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC) = isc; - if (((isc & PWM_INT_CMPAD) != 0) && + if (((isc & PWM_X_ISC_INTCMPAD) != 0) && (pwmp->config->channels[i * 2 + 0].callback != NULL)) { pwmp->config->channels[i * 2 + 0].callback(pwmp); } - if (((isc & PWM_INT_CMPAU) != 0) && + if (((isc & PWM_X_ISC_INTCMPAU) != 0) && (pwmp->config->channels[i * 2 + 0].callback != NULL)) { pwmp->config->channels[i * 2 + 0].callback(pwmp); } - if (((isc & PWM_INT_CMPBD) != 0) && + if (((isc & PWM_X_ISC_INTCMPBD) != 0) && (pwmp->config->channels[i * 2 + 1].callback != NULL)) { pwmp->config->channels[i * 2 + 1].callback(pwmp); } - if (((isc & PWM_INT_CMPBU) != 0) && + if (((isc & PWM_X_ISC_INTCMPBU) != 0) && (pwmp->config->channels[i * 2 + 1].callback != NULL)) { pwmp->config->channels[i * 2 + 1].callback(pwmp); } - if (((isc & PWM_INT_CNTLOAD) != 0) && (pwmp->config->callback != NULL)) { + if (((isc & PWM_X_ISC_INTCNTLOAD) != 0) && (pwmp->config->callback != NULL)) { pwmp->config->callback(pwmp); } - if (((isc & PWM_INT_CNTZERO) != 0) && (pwmp->config->callback != NULL)) { + if (((isc & PWM_X_ISC_INTCNTZERO) != 0) && (pwmp->config->callback != NULL)) { pwmp->config->callback(pwmp); } } @@ -311,13 +307,13 @@ void pwm_lld_init(void) #if TIVA_PWM_USE_PWM0 pwmObjectInit(&PWMD1); PWMD1.channels = PWM_CHANNELS; - PWMD1.pwm = PWM0; + PWMD1.pwm = PWM0_BASE; #endif #if TIVA_PWM_USE_PWM1 pwmObjectInit(&PWMD2); PWMD2.channels = PWM_CHANNELS; - PWMD2.pwm = PWM1; + PWMD2.pwm = PWM1_BASE; #endif } @@ -335,14 +331,15 @@ void pwm_lld_start(PWMDriver *pwmp) uint8_t i; uint32_t invert = 0; uint32_t enable = 0; + uint32_t pwm = pwmp->pwm; if (pwmp->state == PWM_STOP) { /* Clock activation.*/ #if TIVA_PWM_USE_PWM0 if (&PWMD1 == pwmp) { - SYSCTL->RCGCPWM |= (1 << 0); + HWREG(SYSCTL_RCGCPWM) |= (1 << 0); - while (!(SYSCTL->PRPWM & (1 << 0))) + while (!(HWREG(SYSCTL_PRPWM) & (1 << 0))) ; nvicEnableVector(TIVA_PWM0FAULT_NUMBER, @@ -356,9 +353,9 @@ void pwm_lld_start(PWMDriver *pwmp) #if TIVA_PWM_USE_PWM1 if (&PWMD2 == pwmp) { - SYSCTL->RCGCPWM |= (1 << 1); + HWREG(SYSCTL_RCGCPWM) |= (1 << 1); - while (!(SYSCTL->PRPWM & (1 << 1))) + while (!(HWREG(SYSCTL_PRPWM) & (1 << 1))) ; nvicEnableVector(TIVA_PWM1FAULT_NUMBER, @@ -372,20 +369,20 @@ void pwm_lld_start(PWMDriver *pwmp) } else { /* Driver re-configuration scenario, it must be stopped first.*/ - pwmp->pwm->PWM[0].CTL = 0; - pwmp->pwm->PWM[1].CTL = 0; - pwmp->pwm->PWM[2].CTL = 0; - pwmp->pwm->PWM[3].CTL = 0; + HWREG(pwm + PWM_O_0_CTL) = 0; + HWREG(pwm + PWM_O_1_CTL) = 0; + HWREG(pwm + PWM_O_2_CTL) = 0; + HWREG(pwm + PWM_O_3_CTL) = 0; } /* Timer configuration.*/ for (i = 0; i < (PWM_CHANNELS >> 1); i++) { - pwmp->pwm->PWM[i].CTL = 0; - pwmp->pwm->PWM[i].GEN[0] = 0x08C; - pwmp->pwm->PWM[i].GEN[1] = 0x80C; - pwmp->pwm->PWM[i].LOAD = (uint16_t)(pwmp->config->frequency - 1); - pwmp->pwm->PWM[i].CMP[0] = (uint16_t)(pwmp->period - 1); - pwmp->pwm->PWM[i].CMP[1] = (uint16_t)(pwmp->period - 1); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CTL) = 0; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_GENA) = 0x08C; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_GENB) = 0x80C; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_LOAD) = (uint16_t)(pwmp->config->frequency - 1); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CMPA) = (uint16_t)(pwmp->period - 1); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CMPB) = (uint16_t)(pwmp->period - 1); } /* Output enables and polarities setup.*/ @@ -407,9 +404,9 @@ void pwm_lld_start(PWMDriver *pwmp) } } - pwmp->pwm->INVERT = invert; - pwmp->pwm->ENABLE = enable; - pwmp->pwm->ISC = 0xFFFFFFFF; + HWREG(pwm + PWM_O_INVERT) = invert; + HWREG(pwm + PWM_O_ENABLE) = enable; + HWREG(pwm + PWM_O_ISC) = 0xFFFFFFFF; } /** @@ -421,12 +418,14 @@ void pwm_lld_start(PWMDriver *pwmp) */ void pwm_lld_stop(PWMDriver *pwmp) { + uint32_t pwm = pwmp->pwm; + /* If in ready state then disables the PWM clock.*/ if (pwmp->state == PWM_READY) { - pwmp->pwm->PWM[0].CTL = 0; - pwmp->pwm->PWM[1].CTL = 0; - pwmp->pwm->PWM[2].CTL = 0; - pwmp->pwm->PWM[3].CTL = 0; + HWREG(pwm + PWM_O_0_CTL) = 0; + HWREG(pwm + PWM_O_1_CTL) = 0; + HWREG(pwm + PWM_O_2_CTL) = 0; + HWREG(pwm + PWM_O_3_CTL) = 0; #if TIVA_PWM_USE_PWM0 if (&PWMD1 == pwmp) { @@ -435,7 +434,7 @@ void pwm_lld_stop(PWMDriver *pwmp) nvicDisableVector(TIVA_PWM0GEN1_NUMBER); nvicDisableVector(TIVA_PWM0GEN2_NUMBER); nvicDisableVector(TIVA_PWM0GEN3_NUMBER); - SYSCTL->RCGCPWM &= ~(1 << 0); + HWREG(SYSCTL_RCGCPWM) &= ~(1 << 0); } #endif @@ -446,7 +445,7 @@ void pwm_lld_stop(PWMDriver *pwmp) nvicDisableVector(TIVA_PWM1GEN1_NUMBER); nvicDisableVector(TIVA_PWM1GEN2_NUMBER); nvicDisableVector(TIVA_PWM1GEN3_NUMBER); - SYSCTL->RCGCPWM &= ~(1 << 1); + HWREG(SYSCTL_RCGCPWM) &= ~(1 << 1); } #endif } @@ -469,9 +468,16 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width) { + uint32_t pwm = pwmp->pwm; + /* Changing channel duty cycle on the fly.*/ - pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = width; - pwmp->pwm->PWM[channel >> 1].CTL |= (1 << 0); + if (channel & 1) + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPB) = width; + else + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPA) = width; + + + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CTL) = (1 << 0); } /** @@ -488,8 +494,14 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, */ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { - pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = 0; - pwmp->pwm->PWM[channel >> 1].CTL &= ~(1 << 0); + uint32_t pwm = pwmp->pwm; + + if (channel & 1) + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPB) = 0; + else + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPA) = 0; + + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CTL) = (1 << 0); } /** @@ -505,18 +517,19 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { uint32_t inten; uint8_t i; + uint32_t pwm = pwmp->pwm; /* If the IRQ is not already enabled care must be taken to clear it, it is probably already pending because the timer is running.*/ for(i = 0; i < (PWM_CHANNELS >> 1); i++) { - inten = pwmp->pwm->PWM[i].INTEN; + inten = HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_INTEN); if ((inten & 0x03) == 0) { - pwmp->pwm->PWM[i].INTEN |= 0x03; - pwmp->pwm->PWM[i].ISC = 0x03; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_INTEN) |= 0x03; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC) = 0x03; } } - pwmp->pwm->INTEN = 0x3f; + HWREG(pwm + PWM_O_INTEN) = 0x3f; } /** @@ -530,11 +543,14 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) */ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { - pwmp->pwm->PWM[0].INTEN &= ~(0x03); - pwmp->pwm->PWM[1].INTEN &= ~(0x03); - pwmp->pwm->PWM[2].INTEN &= ~(0x03); - pwmp->pwm->PWM[3].INTEN &= ~(0x03); - pwmp->pwm->INTEN &= ~(0x3F); + uint32_t pwm = pwmp->pwm; + + HWREG(pwm + PWM_O_0_INTEN) = ~(0x03); + HWREG(pwm + PWM_O_1_INTEN) = ~(0x03); + HWREG(pwm + PWM_O_2_INTEN) = ~(0x03); + HWREG(pwm + PWM_O_3_INTEN) = ~(0x03); + + HWREG(pwm + PWM_O_INTEN) &= ~(0x3F); } /** @@ -551,13 +567,14 @@ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) void pwm_lld_enable_channel_notification(PWMDriver *pwmp, pwmchannel_t channel) { - uint32_t inten = pwmp->pwm->PWM[channel >> 1].INTEN; + uint32_t pwm = pwmp->pwm; + uint32_t inten = HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_ISC); /* If the IRQ is not already enabled care must be taken to clear it, it is probably already pending because the timer is running.*/ if ((inten & (0x03 << (((channel & 1) * 2) + 2))) == 0) { - pwmp->pwm->PWM[channel >> 1].INTEN |= (0x03 << (((channel & 1) * 2) + 2)); - pwmp->pwm->PWM[channel >> 1].ISC = (0x03 << (((channel & 1) * 2) + 2)); + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_INTEN) |= (0x03 << (((channel & 1) * 2) + 2)); + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_ISC) = (0x03 << (((channel & 1) * 2) + 2)); } } @@ -575,7 +592,9 @@ void pwm_lld_enable_channel_notification(PWMDriver *pwmp, void pwm_lld_disable_channel_notification(PWMDriver *pwmp, pwmchannel_t channel) { - pwmp->pwm->PWM[channel >> 1].INTEN &= ~(0x03 << (((channel & 1) * 2) + 2)); + uint32_t pwm = pwmp->pwm; + + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_INTEN) = ~(0x03 << (((channel & 1) * 2) + 2)); } #endif /* HAL_USE_PWM */ diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h index ac64fe1..7ddbd4d 100644 --- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h +++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h @@ -304,7 +304,7 @@ struct PWMDriver { /** * @brief Pointer to the PWMx registers block. */ - PWM_TypeDef *pwm; + uint32_t pwm; }; /*===========================================================================*/ @@ -328,10 +328,10 @@ struct PWMDriver { * @notapi */ #define pwm_lld_change_period(pwmp, period) \ - ((pwmp)->pwm->PWM[0].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[1].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[2].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[3].LOAD = (uint16_t)((period) - 1)) + HWREG((pwmp)->pwm + PWM_O_0_LOAD) = (uint16_t)((period) - 1); \ + HWREG((pwmp)->pwm + PWM_O_1_LOAD) = (uint16_t)((period) - 1); \ + HWREG((pwmp)->pwm + PWM_O_2_LOAD) = (uint16_t)((period) - 1); \ + HWREG((pwmp)->pwm + PWM_O_3_LOAD) = (uint16_t)((period) - 1) /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c index ded2b99..42efca6 100644 --- a/os/hal/ports/TIVA/LLD/hal_spi_lld.c +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c @@ -77,19 +77,19 @@ static uint16_t dummyrx; */ static void spi_serve_interrupt(SPIDriver *spip) { - SSI_TypeDef *ssi = spip->ssi; - uint32_t mis = ssi->MIS; - uint32_t dmachis = UDMA->CHIS; + uint32_t ssi = spip->ssi; + uint32_t mis = HWREG(ssi + SSI_O_MIS); + uint32_t dmachis = HWREG(UDMA_CHIS); /* SPI error handling.*/ - if ((mis & (TIVA_MIS_RORMIS | TIVA_MIS_RTMIS)) != 0) { + if ((mis & (SSI_MIS_RORMIS | SSI_MIS_RTMIS)) != 0) { TIVA_SPI_SSI_ERROR_HOOK(spip); } - if ( (dmachis & ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) == - ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) { + if ((dmachis & ((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) == + (uint32_t)((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) { /* Clear DMA Channel interrupts.*/ - UDMA->CHIS = (1 << spip->dmarxnr) | (1 << spip->dmatxnr); + HWREG(UDMA_CHIS) = (1 << spip->dmarxnr) | (1 << spip->dmatxnr); /* Portable SPI ISR code defined in the high level driver, note, it is a macro.*/ @@ -180,7 +180,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI0 spiObjectInit(&SPID1); - SPID1.ssi = SSI0; + SPID1.ssi = SSI0_BASE; SPID1.dmarxnr = TIVA_SPI_SSI0_RX_UDMA_CHANNEL; SPID1.dmatxnr = TIVA_SPI_SSI0_TX_UDMA_CHANNEL; SPID1.rxchnmap = TIVA_SPI_SSI0_RX_UDMA_MAPPING; @@ -189,7 +189,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI1 spiObjectInit(&SPID2); - SPID2.ssi = SSI1; + SPID2.ssi = SSI1_BASE; SPID2.dmarxnr = TIVA_SPI_SSI1_RX_UDMA_CHANNEL; SPID2.dmatxnr = TIVA_SPI_SSI1_TX_UDMA_CHANNEL; SPID2.rxchnmap = TIVA_SPI_SSI1_RX_UDMA_MAPPING; @@ -198,7 +198,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI2 spiObjectInit(&SPID3); - SPID3.ssi = SSI2; + SPID3.ssi = SSI2_BASE; SPID3.dmarxnr = TIVA_SPI_SSI2_RX_UDMA_CHANNEL; SPID3.dmatxnr = TIVA_SPI_SSI2_TX_UDMA_CHANNEL; SPID3.rxchnmap = TIVA_SPI_SSI2_RX_UDMA_MAPPING; @@ -207,7 +207,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI3 spiObjectInit(&SPID4); - SPID4.ssi = SSI3; + SPID4.ssi = SSI3_BASE; SPID4.dmarxnr = TIVA_SPI_SSI3_RX_UDMA_CHANNEL; SPID4.dmatxnr = TIVA_SPI_SSI3_TX_UDMA_CHANNEL; SPID4.rxchnmap = TIVA_SPI_SSI3_RX_UDMA_MAPPING; @@ -235,8 +235,8 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 0); - while (!(SYSCTL->PRSSI & (1 << 0))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 0); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 0))) ; nvicEnableVector(TIVA_SSI0_NUMBER, TIVA_SPI_SSI0_IRQ_PRIORITY); @@ -251,8 +251,8 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 1); - while (!(SYSCTL->PRSSI & (1 << 1))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 1); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 1))) ; nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY); @@ -267,8 +267,8 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 2); - while (!(SYSCTL->PRSSI & (1 << 2))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 2); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 2))) ; nvicEnableVector(TIVA_SSI2_NUMBER, TIVA_SPI_SSI2_IRQ_PRIORITY); @@ -283,40 +283,40 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 3); - while (!(SYSCTL->PRSSI & (1 << 3))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 3); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 3))) ; nvicEnableVector(TIVA_SSI3_NUMBER, TIVA_SPI_SSI3_IRQ_PRIORITY); } #endif - UDMA->CHMAP[spip->dmarxnr / 8] |= (spip->rxchnmap << (spip->dmarxnr % 8)); - UDMA->CHMAP[spip->dmatxnr / 8] |= (spip->txchnmap << (spip->dmatxnr % 8)); + HWREG(UDMA_CHMAP0 + (spip->dmarxnr / 8) * 4) |= (spip->rxchnmap << (spip->dmarxnr % 8)); + HWREG(UDMA_CHMAP0 + (spip->dmatxnr / 8) * 4) |= (spip->txchnmap << (spip->dmatxnr % 8)); } /* Set master operation mode.*/ - spip->ssi->CR1 = 0; + HWREG(spip->ssi + SSI_O_CR1) = 0; /* Clock configuration - System Clock.*/ - spip->ssi->CC = 0; + HWREG(spip->ssi + SSI_O_CC) = 0; /* Clear pending interrupts.*/ - spip->ssi->ICR = TIVA_ICR_RTIC | TIVA_ICR_RORIC; + HWREG(spip->ssi + SSI_O_ICR) = SSI_ICR_RTIC | SSI_ICR_RORIC; /* Enable Receive Time-Out and Receive Overrun Interrupts.*/ - spip->ssi->IM = TIVA_IM_RTIM | TIVA_IM_RORIM; + HWREG(spip->ssi + SSI_O_IM) = SSI_IM_RTIM | SSI_IM_RORIM; /* Configure the clock prescale divisor.*/ - spip->ssi->CPSR = spip->config->cpsr; + HWREG(spip->ssi + SSI_O_CPSR) = spip->config->cpsr; /* Serial clock rate, phase/polarity, data size, fixed SPI frame format.*/ - spip->ssi->CR0 = (spip->config->cr0 & ~TIVA_CR0_FRF_MASK) | TIVA_CR0_FRF(0); + HWREG(spip->ssi + SSI_O_CR0) = (spip->config->cr0 & ~SSI_CR0_FRF_M) | SSI_CR0_FRF_MOTO; /* Enable SSI.*/ - spip->ssi->CR1 |= TIVA_CR1_SSE; + HWREG(spip->ssi + SSI_O_CR1) |= SSI_CR1_SSE; /* Enable RX and TX DMA channels.*/ - spip->ssi->DMACTL = (TIVA_DMACTL_TXDMAE | TIVA_DMACTL_RXDMAE); + HWREG(spip->ssi + SSI_O_DMACTL) = (SSI_DMACTL_TXDMAE | SSI_DMACTL_RXDMAE); } /** @@ -329,9 +329,9 @@ void spi_lld_start(SPIDriver *spip) void spi_lld_stop(SPIDriver *spip) { if (spip->state != SPI_STOP) { - spip->ssi->CR1 = 0; - spip->ssi->CR0 = 0; - spip->ssi->CPSR = 0; + HWREG(spip->ssi + SSI_O_CR1) = 0; + HWREG(spip->ssi + SSI_O_CR0) = 0; + HWREG(spip->ssi + SSI_O_CPSR) = 0; udmaChannelRelease(spip->dmarxnr); udmaChannelRelease(spip->dmatxnr); @@ -399,20 +399,20 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -420,17 +420,17 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -470,20 +470,20 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+n-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -491,17 +491,17 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -539,20 +539,20 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].dstendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -560,17 +560,17 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].dstendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -608,20 +608,20 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+n-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -629,17 +629,17 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -674,10 +674,10 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) */ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - spip->ssi->DR = (uint32_t)frame; - while ((spip->ssi->SR & TIVA_SR_RNE) == 0) + HWREG(spip->ssi + SSI_O_DR) = (uint32_t)frame; + while ((HWREG(spip->ssi + SSI_O_SR) & SSI_SR_RNE) == 0) ; - return (uint16_t)spip->ssi->DR; + return (uint16_t)HWREG(spip->ssi + SSI_O_DR); } #endif /* HAL_USE_SPI */ diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h index 2adc9ed..dd49e84 100644 --- a/os/hal/ports/TIVA/LLD/hal_spi_lld.h +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h @@ -32,89 +32,9 @@ /*===========================================================================*/ /** - * @name Control 0 - * @{ - */ -#define TIVA_CR0_DSS_MASK 0x0F -#define TIVA_CR0_DSS(n) ((n-1) << 0) - -#define TIVA_CR0_FRF_MASK (3 << 4) -#define TIVA_CR0_FRF(n) ((n) << 4) - -#define TIVA_CR0_SPO (1 << 6) -#define TIVA_CR0_SPH (1 << 7) - -#define TIVA_CR0_SRC_MASK (0xFF << 8) -#define TIVA_CR0_SRC(n) ((n) << 8) -/** @} */ - -/** - * @name Control 1 - * @{ - */ -#define TIVA_CR1_LBM (1 << 0) -#define TIVA_CR1_SSE (1 << 1) -#define TIVA_CR1_MS (1 << 2) -#define TIVA_CR1_SOD (1 << 3) -#define TIVA_CR1_EOT (1 << 4) -/** @} */ - -/** - * @name Status - * @{ - */ -#define TIVA_SR_TFE (1 << 0) -#define TIVA_SR_TNF (1 << 1) -#define TIVA_SR_RNE (1 << 2) -#define TIVA_SR_RFF (1 << 3) -#define TIVA_SR_BSY (1 << 4) -/** @} */ - -/** - * @name Interrupt Mask - * @{ - */ -#define TIVA_IM_RORIM (1 << 0) -#define TIVA_IM_RTIM (1 << 1) -#define TIVA_IM_RXIM (1 << 2) -#define TIVA_IM_TXIM (1 << 3) -/** @} */ - -/** - * @name Interrupt Status - * @{ - */ -#define TIVA_IS_RORIS (1 << 0) -#define TIVA_IS_RTIS (1 << 1) -#define TIVA_IS_RXIS (1 << 2) -#define TIVA_IS_TXIS (1 << 3) -/** @} */ - -/** - * @name Masked Interrupt Status - * @{ - */ -#define TIVA_MIS_RORMIS (1 << 0) -#define TIVA_MIS_RTMIS (1 << 1) -#define TIVA_MIS_RXMIS (1 << 2) -#define TIVA_MIS_TXMIS (1 << 3) -/** @} */ - -/** - * @name Interrupt Clear - * @{ - */ -#define TIVA_ICR_RORIC (1 << 0) -#define TIVA_ICR_RTIC (1 << 1) -/** @} */ - -/** - * @name DMA Control - * @{ + * @brief CR0 Serial Clock Rate helper. */ -#define TIVA_DMACTL_RXDMAE (1 << 0) -#define TIVA_DMACTL_TXDMAE (1 << 1) -/** @} */ +#define SSI_CR0_SCR(n) ((n) << 8) /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -320,7 +240,7 @@ struct SPIDriver { /** * @brief Pointer to the SSI registers block. */ - SSI_TypeDef *ssi; + uint32_t ssi; /** * @brief Receive DMA channel number. */ diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c index 89d29da..2e3b213 100644 --- a/os/hal/ports/TIVA/LLD/hal_serial_lld.c +++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c @@ -34,58 +34,42 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** - * @brief UART0 serial driver identifier. - */ +/** @brief UART0 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) SerialDriver SD1; #endif -/** - * @brief UART1 serial driver identifier. - */ +/** @brief UART1 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) SerialDriver SD2; #endif -/** - * @brief UART2 serial driver identifier. - */ +/** @brief UART2 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) SerialDriver SD3; #endif -/** - * @brief UART3 serial driver identifier. - */ +/** @brief UART3 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) SerialDriver SD4; #endif -/** - * @brief UART4 serial driver identifier. - */ +/** @brief UART4 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) SerialDriver SD5; #endif -/** - * @brief UART5 serial driver identifier. - */ +/** @brief UART5 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) SerialDriver SD6; #endif -/** - * @brief UART6 serial driver identifier. - */ +/** @brief UART6 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) SerialDriver SD7; #endif -/** - * @brief UART7 serial driver identifier. - */ +/** @brief UART7 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) SerialDriver SD8; #endif @@ -94,14 +78,14 @@ SerialDriver SD8; /* Driver local variables. */ /*===========================================================================*/ -/** - * @brief Driver default configuration. - */ +/** @brief Driver default configuration.*/ static const SerialConfig sd_default_config = { SERIAL_DEFAULT_BITRATE, - TIVA_LCRH_FEN | TIVA_LCRH_WLEN_8, - TIVA_IFLS_TXIFLSEL_1_8_F | TIVA_IFLS_RXIFLSEL_1_8_E + 0, + UART_LCRH_FEN | UART_LCRH_WLEN_8, + UART_IFLS_TX4_8 | UART_IFLS_RX7_8, + UART_CC_CS_SYSCLK }; /*===========================================================================*/ @@ -111,23 +95,55 @@ static const SerialConfig sd_default_config = /** * @brief UART initialization. * - * @param[in] sdp communication channel associated to the UART + * @param[in] sdp pointer to a @p SerialDriver object * @param[in] config the architecture-dependent serial driver configuration */ static void uart_init(SerialDriver *sdp, const SerialConfig *config) { - UART_TypeDef *u = sdp->uart; - uint32_t div; /* baud rate divisor */ - - /* disable the UART before any of the control registers are reprogrammed */ - u->CTL &= ~TIVA_CTL_UARTEN; - div = (((TIVA_SYSCLK * 8) / config->sc_speed) + 1) / 2; - u->IBRD = div / 64; /* integer portion of the baud rate divisor */ - u->FBRD = div % 64; /* fractional portion of the baud rate divisor */ - u->LCRH = config->sc_lcrh; /* set data format */ - u->IFLS = config->sc_ifls; - u->CTL |= TIVA_CTL_TXE | TIVA_CTL_RXE | TIVA_CTL_UARTEN; - u->IM |= TIVA_IM_RXIM | TIVA_IM_TXIM | TIVA_IM_RTIM; /* interrupts enable */ + uint32_t u = sdp->uart; + uint32_t brd; + uint32_t speed = config->speed; + uint32_t clock_source; + + if (config->ctl & UART_CTL_HSE) { + /* High speed mode is enabled, half the baud rate to compensate + * for high speed mode.*/ + speed = (speed + 1) / 2; + } + + if ((config->cc & UART_CC_CS_SYSCLK) == UART_CC_CS_SYSCLK) { + /* UART is clocked using the SYSCLK.*/ + clock_source = TIVA_SYSCLK * 8; + } + else { + /* UART is clocked using the PIOSC.*/ + clock_source = 16000000 * 8; + } + + /* Calculate the baud rate divisor */ + brd = ((clock_source / speed) + 1) / 2; + + /* Disable UART.*/ + HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN; + + /* Set baud rate.*/ + HWREG(u + UART_O_IBRD) = brd / 64; + HWREG(u + UART_O_FBRD) = brd % 64; + + /* Line control/*/ + HWREG(u + UART_O_LCRH) = config->lcrh; + + /* Select clock source.*/ + HWREG(u + UART_O_CC) = config->cc & UART_CC_CS_M; + + /* FIFO configuration.*/ + HWREG(u + UART_O_IFLS) = config->ifls & (UART_IFLS_RX_M | UART_IFLS_TX_M); + + /* Note that some bits are enforced.*/ + HWREG(u + UART_O_CTL) = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN; + + /* Enable interrupts.*/ + HWREG(u + UART_O_IM) = UART_IM_RXIM | UART_IM_TXIM | UART_IM_RTIM; } /** @@ -135,9 +151,9 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config) * * @param[in] u pointer to an UART I/O block */ -static void uart_deinit(UART_TypeDef *u) +static void uart_deinit(uint32_t u) { - u->CTL &= ~TIVA_CTL_UARTEN; + HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN; } /** @@ -150,13 +166,13 @@ static void set_error(SerialDriver *sdp, uint16_t err) { eventflags_t sts = 0; - if (err & TIVA_MIS_FEMIS) + if (err & UART_MIS_FEMIS) sts |= SD_FRAMING_ERROR; - if (err & TIVA_MIS_PEMIS) + if (err & UART_MIS_PEMIS) sts |= SD_PARITY_ERROR; - if (err & TIVA_MIS_BEMIS) + if (err & UART_MIS_BEMIS) sts |= SD_BREAK_DETECTED; - if (err & TIVA_MIS_OEMIS) + if (err & UART_MIS_OEMIS) sts |= SD_OVERRUN_ERROR; osalSysLockFromISR(); chnAddFlagsI(sdp, sts); @@ -174,44 +190,44 @@ static void set_error(SerialDriver *sdp, uint16_t err) */ static void serial_serve_interrupt(SerialDriver *sdp) { - UART_TypeDef *u = sdp->uart; - uint16_t mis = u->MIS; + uint32_t u = sdp->uart; + uint16_t mis = HWREG(u + UART_O_MIS); - u->ICR = mis; /* clear interrupts */ + HWREG(u + UART_O_ICR) = mis; /* clear interrupts */ - if (mis & (TIVA_MIS_FEMIS | TIVA_MIS_PEMIS | TIVA_MIS_BEMIS | TIVA_MIS_OEMIS)) { + if (mis & (UART_MIS_FEMIS | UART_MIS_PEMIS | UART_MIS_BEMIS | UART_MIS_OEMIS)) { set_error(sdp, mis); } - if ((mis & TIVA_MIS_RXMIS) || (mis & TIVA_MIS_RTMIS)) { + if ((mis & UART_MIS_RXMIS) || (mis & UART_MIS_RTMIS)) { osalSysLockFromISR(); if (iqIsEmptyI(&sdp->iqueue)) { chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); } osalSysUnlockFromISR(); - while ((u->FR & TIVA_FR_RXFE) == 0) { + while ((HWREG(u + UART_O_FR) & UART_FR_RXFE) == 0) { osalSysLockFromISR(); - if (iqPutI(&sdp->iqueue, u->DR) < Q_OK) { + if (iqPutI(&sdp->iqueue, HWREG(u + UART_O_DR)) < Q_OK) { chnAddFlagsI(sdp, SD_OVERRUN_ERROR); } osalSysUnlockFromISR(); } } - if (mis & TIVA_MIS_TXMIS) { - while ((u->FR & TIVA_FR_TXFF) == 0) { + if (mis & UART_MIS_TXMIS) { + while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) { msg_t b; osalSysLockFromISR(); b = oqGetI(&sdp->oqueue); osalSysUnlockFromISR(); if (b < Q_OK) { - u->IM &= ~TIVA_IM_TXIM; + HWREG(u + UART_O_IM) &= ~UART_IM_TXIM; osalSysLockFromISR(); chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); osalSysUnlockFromISR(); break; } - u->DR = b; + HWREG(u + UART_O_DR) = b; } } } @@ -221,17 +237,18 @@ static void serial_serve_interrupt(SerialDriver *sdp) */ static void fifo_load(SerialDriver *sdp) { - UART_TypeDef *u = sdp->uart; + uint32_t u = sdp->uart; - while ((u->FR & TIVA_FR_TXFF) == 0) { + while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) { msg_t b = oqGetI(&sdp->oqueue); if (b < Q_OK) { chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); return; } - u->DR = b; + HWREG(u + UART_O_DR) = b; } - u->IM |= TIVA_IM_TXIM; /* transmit interrupt enable */ + + HWREG(u + UART_O_IM) |= UART_IM_TXIM; /* transmit interrupt enable */ } /** @@ -452,42 +469,42 @@ void sd_lld_init(void) { #if TIVA_SERIAL_USE_UART0 sdObjectInit(&SD1, NULL, notify1); - SD1.uart = UART0; + SD1.uart = UART0_BASE; #endif #if TIVA_SERIAL_USE_UART1 sdObjectInit(&SD2, NULL, notify2); - SD2.uart = UART1; + SD2.uart = UART1_BASE; #endif #if TIVA_SERIAL_USE_UART2 sdObjectInit(&SD3, NULL, notify3); - SD3.uart = UART2; + SD3.uart = UART2_BASE; #endif #if TIVA_SERIAL_USE_UART3 sdObjectInit(&SD4, NULL, notify4); - SD4.uart = UART3; + SD4.uart = UART3_BASE; #endif #if TIVA_SERIAL_USE_UART4 sdObjectInit(&SD5, NULL, notify5); - SD5.uart = UART4; + SD5.uart = UART4_BASE; #endif #if TIVA_SERIAL_USE_UART5 sdObjectInit(&SD6, NULL, notify6); - SD6.uart = UART5; + SD6.uart = UART5_BASE; #endif #if TIVA_SERIAL_USE_UART6 sdObjectInit(&SD7, NULL, notify7); - SD7.uart = UART6; + SD7.uart = UART6_BASE; #endif #if TIVA_SERIAL_USE_UART7 sdObjectInit(&SD8, NULL, notify8); - SD8.uart = UART7; + SD8.uart = UART7_BASE; #endif } @@ -507,9 +524,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) if (sdp->state == SD_STOP) { #if TIVA_SERIAL_USE_UART0 if (&SD1 == sdp) { - SYSCTL->RCGCUART |= (1 << 0); + HWREG(SYSCTL_RCGCUART) |= (1 << 0); - while (!(SYSCTL->PRUART & (1 << 0))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 0))) ; nvicEnableVector(TIVA_UART0_NUMBER, TIVA_SERIAL_UART0_PRIORITY); @@ -517,9 +534,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART1 if (&SD2 == sdp) { - SYSCTL->RCGCUART |= (1 << 1); + HWREG(SYSCTL_RCGCUART) |= (1 << 1); - while (!(SYSCTL->PRUART & (1 << 1))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 1))) ; nvicEnableVector(TIVA_UART1_NUMBER, TIVA_SERIAL_UART1_PRIORITY); @@ -527,9 +544,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART2 if (&SD3 == sdp) { - SYSCTL->RCGCUART |= (1 << 2); + HWREG(SYSCTL_RCGCUART) |= (1 << 2); - while (!(SYSCTL->PRUART & (1 << 2))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 2))) ; nvicEnableVector(TIVA_UART2_NUMBER, TIVA_SERIAL_UART2_PRIORITY); @@ -537,9 +554,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART3 if (&SD4 == sdp) { - SYSCTL->RCGCUART |= (1 << 3); + HWREG(SYSCTL_RCGCUART) |= (1 << 3); - while (!(SYSCTL->PRUART & (1 << 3))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 3))) ; nvicEnableVector(TIVA_UART3_NUMBER, TIVA_SERIAL_UART3_PRIORITY); @@ -547,9 +564,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART4 if (&SD5 == sdp) { - SYSCTL->RCGCUART |= (1 << 4); + HWREG(SYSCTL_RCGCUART) |= (1 << 4); - while (!(SYSCTL->PRUART & (1 << 4))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 4))) ; nvicEnableVector(TIVA_UART4_NUMBER, TIVA_SERIAL_UART4_PRIORITY); @@ -557,9 +574,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART5 if (&SD6 == sdp) { - SYSCTL->RCGCUART |= (1 << 5); + HWREG(SYSCTL_RCGCUART) |= (1 << 5); - while (!(SYSCTL->PRUART & (1 << 5))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 5))) ; nvicEnableVector(TIVA_UART5_NUMBER, TIVA_SERIAL_UART5_PRIORITY); @@ -567,9 +584,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART6 if (&SD7 == sdp) { - SYSCTL->RCGCUART |= (1 << 6); + HWREG(SYSCTL_RCGCUART) |= (1 << 6); - while (!(SYSCTL->PRUART & (1 << 6))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 6))) ; nvicEnableVector(TIVA_UART6_NUMBER, TIVA_SERIAL_UART6_PRIORITY); @@ -577,9 +594,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) #endif #if TIVA_SERIAL_USE_UART7 if (&SD8 == sdp) { - SYSCTL->RCGCUART |= (1 << 7); + HWREG(SYSCTL_RCGCUART) |= (1 << 7); - while (!(SYSCTL->PRUART & (1 << 7))) + while (!(HWREG(SYSCTL_PRUART) & (1 << 7))) ; nvicEnableVector(TIVA_UART7_NUMBER, TIVA_SERIAL_UART7_PRIORITY); @@ -602,56 +619,56 @@ void sd_lld_stop(SerialDriver *sdp) uart_deinit(sdp->uart); #if TIVA_SERIAL_USE_UART0 if (&SD1 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 0); /* disable UART0 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 0); /* disable UART0 module */ nvicDisableVector(TIVA_UART0_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART1 if (&SD2 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 1); /* disable UART1 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 1); /* disable UART1 module */ nvicDisableVector(TIVA_UART1_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART2 if (&SD3 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 2); /* disable UART2 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 2); /* disable UART2 module */ nvicDisableVector(TIVA_UART2_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART3 if (&SD4 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 3); /* disable UART3 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 3); /* disable UART3 module */ nvicDisableVector(TIVA_UART3_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART4 if (&SD5 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 4); /* disable UART4 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 4); /* disable UART4 module */ nvicDisableVector(TIVA_UART4_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART5 if (&SD6 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 5); /* disable UART5 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 5); /* disable UART5 module */ nvicDisableVector(TIVA_UART5_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART6 if (&SD7 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 6); /* disable UART6 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 6); /* disable UART6 module */ nvicDisableVector(TIVA_UART6_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART7 if (&SD8 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 7); /* disable UART7 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 7); /* disable UART7 module */ nvicDisableVector(TIVA_UART7_NUMBER); return; } diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h index 203ef6a..d52828c 100644 --- a/os/hal/ports/TIVA/LLD/hal_serial_lld.h +++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h @@ -31,163 +31,6 @@ /* Driver constants. */ /*===========================================================================*/ -/** - * @name FR register bits definitions - * @{ - */ - -#define TIVA_FR_CTS (1 << 0) - -#define TIVA_FR_BUSY (1 << 3) - -#define TIVA_FR_RXFE (1 << 4) - -#define TIVA_FR_TXFF (1 << 5) - -#define TIVA_FR_RXFF (1 << 6) - -#define TIVA_FR_TXFE (1 << 7) - -/** - * @} - */ - -/** - * @name LCRH register bits definitions - * @{ - */ - -#define TIVA_LCRH_BRK (1 << 0) - -#define TIVA_LCRH_PEN (1 << 1) - -#define TIVA_LCRH_EPS (1 << 2) - -#define TIVA_LCRH_STP2 (1 << 3) - -#define TIVA_LCRH_FEN (1 << 4) - -#define TIVA_LCRH_WLEN_MASK (3 << 5) -#define TIVA_LCRH_WLEN_5 (0 << 5) -#define TIVA_LCRH_WLEN_6 (1 << 5) -#define TIVA_LCRH_WLEN_7 (2 << 5) -#define TIVA_LCRH_WLEN_8 (3 << 5) - -#define TIVA_LCRH_SPS (1 << 7) - -/** - * @} - */ - -/** - * @name CTL register bits definitions - * @{ - */ - -#define TIVA_CTL_UARTEN (1 << 0) - -#define TIVA_CTL_SIREN (1 << 1) - -#define TIVA_CTL_SIRLP (1 << 2) - -#define TIVA_CTL_SMART (1 << 3) - -#define TIVA_CTL_EOT (1 << 4) - -#define TIVA_CTL_HSE (1 << 5) - -#define TIVA_CTL_LBE (1 << 7) - -#define TIVA_CTL_TXE (1 << 8) - -#define TIVA_CTL_RXE (1 << 9) - -#define TIVA_CTL_RTS (1 << 11) - -#define TIVA_CTL_RTSEN (1 << 14) - -#define TIVA_CTL_CTSEN (1 << 15) - -/** - * @} - */ - -/** - * @name IFLS register bits definitions - * @{ - */ - -#define TIVA_IFLS_TXIFLSEL_MASK (7 << 0) -#define TIVA_IFLS_TXIFLSEL_1_8_F (0 << 0) -#define TIVA_IFLS_TXIFLSEL_1_4_F (1 << 0) -#define TIVA_IFLS_TXIFLSEL_1_2_F (2 << 0) -#define TIVA_IFLS_TXIFLSEL_3_4_F (3 << 0) -#define TIVA_IFLS_TXIFLSEL_7_8_F (4 << 0) - -#define TIVA_IFLS_RXIFLSEL_MASK (7 << 3) -#define TIVA_IFLS_RXIFLSEL_7_8_E (0 << 3) -#define TIVA_IFLS_RXIFLSEL_3_4_E (1 << 3) -#define TIVA_IFLS_RXIFLSEL_1_2_E (2 << 3) -#define TIVA_IFLS_RXIFLSEL_1_4_E (3 << 3) -#define TIVA_IFLS_RXIFLSEL_1_8_E (4 << 3) - -/** - * @} - */ - -/** - * @name MIS register bits definitions - * @{ - */ - -#define TIVA_MIS_CTSMIS (1 << 1) - -#define TIVA_MIS_RXMIS (1 << 4) - -#define TIVA_MIS_TXMIS (1 << 5) - -#define TIVA_MIS_RTMIS (1 << 6) - -#define TIVA_MIS_FEMIS (1 << 7) - -#define TIVA_MIS_PEMIS (1 << 8) - -#define TIVA_MIS_BEMIS (1 << 9) - -#define TIVA_MIS_OEMIS (1 << 10) - -#define TIVA_MIS_9BITMIS (1 << 12) - -/** - * @} - */ - -/** - * @name IM register bits definitions - * @{ - */ - -#define TIVA_IM_CTSIM (1 << 1) - -#define TIVA_IM_RXIM (1 << 4) - -#define TIVA_IM_TXIM (1 << 5) - -#define TIVA_IM_RTIM (1 << 6) - -#define TIVA_IM_FEIM (1 << 7) - -#define TIVA_IM_PEIM (1 << 8) - -#define TIVA_IM_BEIM (1 << 9) - -#define TIVA_IM_OEIM (1 << 10) - -#define TIVA_IM_9BITIM (1 << 12) - -/** - * @} - */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -388,22 +231,32 @@ * @brief Tiva Serial Driver configuration structure. * @details An instance of this structure must be passed to @p sdStart() * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. */ typedef struct { /** * @brief Bit rate. */ - uint32_t sc_speed; + uint32_t speed; /* End of the mandatory fields. */ /** - * @brief Initialization value for the LCRH (Line Control) register. + * @brief Initialization value for the CTL register. + */ + uint16_t ctl; + /** + * @brief Initialization value for the LCRH register. + */ + uint8_t lcrh; + /** + * @brief Initialization value for the IFLS register. */ - uint32_t sc_lcrh; + uint8_t ifls; /** - * @brief Initialization value for the IFLS (Interrupt FIFO Level Select) - * register. + * @brief Initialization value for the CC register. */ - uint32_t sc_ifls; + uint8_t cc; } SerialConfig; /** @@ -423,7 +276,7 @@ typedef struct { uint8_t ob[SERIAL_BUFFERS_SIZE]; \ /* End of the mandatory fields.*/ \ /* Pointer to the USART registers block.*/ \ - UART_TypeDef *uart; + uint32_t uart; /*===========================================================================*/ /* Driver macros. */ diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c index 38dcef0..ddd01e0 100644 --- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c +++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c @@ -60,14 +60,14 @@ static void serve_interrupt(WDGDriver *wdgp) { uint32_t mis; - mis = wdgp->wdt->MIS; + mis = HWREG(wdgp->wdt + WDT_O_MIS); - if (mis & MIS_WDTMIS) { + if (mis & WDT_MIS_WDTMIS) { /* Invoke callback, if any */ if (wdgp->config->callback) { if (wdgp->config->callback(wdgp)) { /* Clear interrupt */ - wdgp->wdt->ICR = 0; + HWREG(wdgp->wdt + WDT_O_ICR) = 0; wdgTivaSyncWrite(wdgp); } } @@ -113,12 +113,12 @@ void wdg_lld_init(void) { #if TIVA_WDG_USE_WDT0 WDGD1.state = WDG_STOP; - WDGD1.wdt = WDT0; + WDGD1.wdt = WATCHDOG0_BASE; #endif /* TIVA_WDG_USE_WDT0 */ #if TIVA_WDG_USE_WDT1 WDGD2.state = WDG_STOP; - WDGD2.wdt = WDT1; + WDGD2.wdt = WATCHDOG1_BASE; #endif /* TIVA_WDG_USE_WDT1 */ /* The shared vector is initialized on driver initialization and never @@ -137,32 +137,32 @@ void wdg_lld_start(WDGDriver *wdgp) { #if TIVA_WDG_USE_WDT0 if (&WDGD1 == wdgp) { - SYSCTL->RCGCWD |= (1 << 0); + HWREG(SYSCTL_RCGCWD) |= (1 << 0); - while (!(SYSCTL->PRWD & (1 << 0))) + while (!(HWREG(SYSCTL_PRWD) & (1 << 0))) ; } #endif /* TIVA_WDG_USE_WDT0 */ #if TIVA_WDG_USE_WDT1 if (&WDGD2 == wdgp) { - SYSCTL->RCGCWD |= (1 << 1); + HWREG(SYSCTL_RCGCWD) |= (1 << 1); - while (!(SYSCTL->PRWD & (1 << 1))) + while (!(HWREG(SYSCTL_PRWD) & (1 << 1))) ; } #endif /* TIVA_WDG_USE_WDT1 */ - wdgp->wdt->LOAD = wdgp->config->load; + HWREG(wdgp->wdt + WDT_O_LOAD) = wdgp->config->load; wdgTivaSyncWrite(wdgp); - wdgp->wdt->TEST = wdgp->config->test; + HWREG(wdgp->wdt + WDT_O_TEST) = wdgp->config->test; wdgTivaSyncWrite(wdgp); - wdgp->wdt->CTL |= CTL_RESEN; + HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_RESEN; wdgTivaSyncWrite(wdgp); - wdgp->wdt->CTL |= CTL_INTEN; + HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_INTEN; wdgTivaSyncWrite(wdgp); } @@ -177,15 +177,15 @@ void wdg_lld_stop(WDGDriver *wdgp) { #if TIVA_WDG_USE_WDT0 if (&WDGD1 == wdgp) { - SYSCTL->SRWD |= (1 << 0); - SYSCTL->SRWD &= ~(1 << 0); + HWREG(SYSCTL_SRWD) |= (1 << 0); + HWREG(SYSCTL_SRWD) &= ~(1 << 0); } #endif /* TIVA_WDG_USE_WDT0 */ #if TIVA_WDG_USE_WDT1 if (&WDGD2 == wdgp) { - SYSCTL->SRWD |= (1 << 1); - SYSCTL->SRWD &= ~(1 << 1); + HWREG(SYSCTL_SRWD) |= (1 << 1); + HWREG(SYSCTL_SRWD) &= ~(1 << 1); } #endif /* TIVA_WDG_USE_WDT1 */ } @@ -219,7 +219,7 @@ void wdg_lld_reset(WDGDriver *wdgp) #endif /* defined(TM4C123_USE_REVISION_6_FIX) || defined(TM4C123_USE_REVISION_7_FIX) */ - wdgp->wdt->LOAD = wdgp->config->load; + HWREG(wdgp->wdt + WDT_O_LOAD) = wdgp->config->load; wdgTivaSyncWrite(wdgp); } @@ -234,7 +234,7 @@ void wdg_lld_reset(WDGDriver *wdgp) void wdgTivaSyncWrite(WDGDriver *wdgp) { if (&WDGD2 == wdgp) { - while (!(wdgp->wdt->CTL & CTL_WRC)) { + while (!(HWREG(wdgp->wdt + WDT_O_CTL) & CTL_WRC)) { ; } } diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h index f88fa26..77badb3 100644 --- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h +++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h @@ -32,23 +32,6 @@ /* Driver constants. */ /*===========================================================================*/ -#define LOCK_UNLOCK 0x1ACCE551U -#define LOCK_LOCK 0x00000000U - -#define LOCK_IS_UNLOCKED 0U -#define LOCK_IS_LOCKED 1U - -#define TEST_STALL (1 << 8) - -#define MIS_WDTMIS (1 << 0) -#define RIS_WDTRIS (1 << 0) -#define ICR_WDTICR (1 << 0) - -#define CTL_INTEN (1 << 0) -#define CTL_RESEN (1 << 1) -#define CTL_INTTYPE (1 << 2) -#define CTL_WRC (1 << 31) - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -146,7 +129,7 @@ struct WDGDriver /** * @brief Pointer to the WDT registers block. */ - WDT_TypeDef *wdt; + uint32_t wdt; }; /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/tiva_gpt.h b/os/hal/ports/TIVA/LLD/tiva_gpt.h deleted file mode 100644 index 114831b..0000000 --- a/os/hal/ports/TIVA/LLD/tiva_gpt.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file tiva_gpt.h - * @brief TIVA GPT registers layout header. - * - * @addtogroup TIVA_GPT - * @{ - */ - -#ifndef TIVA_GPT_H_ -#define TIVA_GPT_H_ - -// cfg -#define GPTM_CFG_CFG_MASK (7 << 0) -#define GPTM_CFG_CFG_WHOLE (0 << 0) -#define GPTM_CFG_CFG_RTC (1 << 0) -#define GPTM_CFG_CFG_SPLIT (4 << 0) - -// tamr -#define GPTM_TAMR_TAMR_MASK (3 << 0) -#define GPTM_TAMR_TAMR_ONESHOT (1 << 0) -#define GPTM_TAMR_TAMR_PERIODIC (2 << 0) -#define GPTM_TAMR_TAMR_CAPTURE (3 << 0) - -#define GPTM_TAMR_TACMR (1 << 2) - -#define GPTM_TAMR_TAAMS (1 << 3) - -#define GPTM_TAMR_TACDIR (1 << 4) - -#define GPTM_TAMR_TAMIE (1 << 5) - -#define GPTM_TAMR_TAWOT (1 << 6) - -#define GPTM_TAMR_TASNAPS (1 << 7) - -#define GPTM_TAMR_TAILD (1 << 8) - -#define GPTM_TAMR_TAPWMIE (1 << 9) - -#define GPTM_TAMR_TAMRSU (1 << 10) - -#define GPTM_TAMR_TAPLO (1 << 11) - -// ctl -#define GPTM_CTL_TAEN (1 << 0) - -#define GPTM_CTL_TASTALL (1 << 1) - -#define GPTM_CTL_TAEVENT_MASK (3 << 2) -#define GPTM_CTL_TAEVENT_POS (0 << 2) -#define GPTM_CTL_TAEVENT_NEG (1 << 2) -#define GPTM_CTL_TAEVENT_BOTH (3 << 2) - -#define GPTM_CTL_RTCEN (1 << 4) - -#define GPTM_CTL_TAOTE (1 << 5) - -#define GPTM_CTL_TAPWML (1 << 6) - -#define GPTM_CTL_TBEN (1 << 8) - -#define GPTM_CTL_TBSTALL (1 << 9) - -#define GPTM_CTL_TBEVENT_MASK (3 << 10) -#define GPTM_CTL_TBEVENT_POS (0 << 10) -#define GPTM_CTL_TBEVENT_NEG (1 << 10) -#define GPTM_CTL_TBEVENT_BOTH (3 << 10) - -#define GPTM_CTL_TBOTE (1 << 13) - -#define GPTM_CTL_TBPWML (1 << 14) - -// imr -#define GPTM_IMR_TATOIM (1 << 0) - -#define GPTM_IMR_CAMIM (1 << 1) - -#define GPTM_IMR_CAEIM (1 << 2) - -#define GPTM_IMR_RTCIM (1 << 3) - -#define GPTM_IMR_TAMIM (1 << 4) - -#define GPTM_IMR_TBTOIM (1 << 8) - -#define GPTM_IMR_CBMIM (1 << 9) - -#define GPTM_IMR_CBEIM (1 << 10) - -#define GPTM_IMR_TBMIM (1 << 11) - -#define GPTM_IMR_WUEIM (1 << 16) - -// icr -#define GPTM_ICR_TATOCINT (1 << 0) - -#define GPTM_ICR_CAMCINT (1 << 1) - -#define GPTM_ICR_CAECINT (1 << 2) - -#define GPTM_ICR_RTCCINT (1 << 3) - -#define GPTM_ICR_TAMCINT (1 << 4) - -#define GPTM_ICR_TBTOCINT (1 << 8) - -#define GPTM_ICR_CBMCINT (1 << 9) - -#define GPTM_ICR_CBECINT (1 << 10) - -#define GPTM_ICR_TBMCINT (1 << 11) - -#define GPTM_ICR_WUECINT (1 << 16) - -#endif /* TIVA_GPT_H_ */ - -/* - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.c b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c index 9f122b2..bb379cb 100644 --- a/os/hal/ports/TIVA/LLD/tiva_udma.c +++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c @@ -75,8 +75,8 @@ OSAL_IRQ_HANDLER(TIVA_UDMA_ERR_HANDLER) /* TODO Do we need to halt the system on a DMA error?*/ - if (UDMA->ERRCLR) { - UDMA->ERRCLR = 1; + if (HWREG(UDMA_ERRCLR)) { + HWREG(UDMA_ERRCLR) = 1; } OSAL_IRQ_EPILOGUE(); @@ -96,18 +96,18 @@ void udmaInit(void) udma_channel_mask = 0; /* Enable UDMA module.*/ - SYSCTL->RCGCDMA = 1; - while (!(SYSCTL->PRDMA & (1 << 0))) + HWREG(SYSCTL_RCGCDMA) = 1; + while (!(HWREG(SYSCTL_PRDMA) & (1 << 0))) ; nvicEnableVector(TIVA_UDMA_ERR_NUMBER, TIVA_UDMA_ERR_IRQ_PRIORITY); nvicEnableVector(TIVA_UDMA_SW_NUMBER, TIVA_UDMA_SW_IRQ_PRIORITY); /* Enable UDMA controller.*/ - UDMA->CFG = 1; + HWREG(UDMA_CFG) = UDMA_CFG_MASTEN; /* Set address of control table.*/ - UDMA->CTLBASE = (uint32_t)udmaControlTable.primary; + HWREG(UDMA_CTLBASE) = (uint32_t)udmaControlTable.primary; } /** diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.h b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h index 6479b08..0157277 100644 --- a/os/hal/ports/TIVA/LLD/tiva_udma.h +++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h @@ -22,52 +22,9 @@ /*===========================================================================*/ /** - * @name CHCTL register defines. - * @{ + * @brief CHCTL XFERSIZE helper. */ -#define UDMA_CHCTL_DSTINC_MASK 0xC0000000 -#define UDMA_CHCTL_DSTINC_0 0xC0000000 -#define UDMA_CHCTL_DSTINC_8 0x00000000 -#define UDMA_CHCTL_DSTINC_16 0x40000000 -#define UDMA_CHCTL_DSTINC_32 0x80000000 -#define UDMA_CHCTL_DSTSIZE_MASK 0x30000000 -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 -#define UDMA_CHCTL_SRCINC_MASK 0x0C000000 -#define UDMA_CHCTL_SRCINC_0 0x0C000000 -#define UDMA_CHCTL_SRCINC_8 0x00000000 -#define UDMA_CHCTL_SRCINC_16 0x04000000 -#define UDMA_CHCTL_SRCINC_32 0x08000000 -#define UDMA_CHCTL_SRCSIZE_MASK 0x03000000 -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 -#define UDMA_CHCTL_ARBSIZE_MASK 0x0003C000 -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 -#define UDMA_CHCTL_XFERSIZE_MASK 0x00003FF0 #define UDMA_CHCTL_XFERSIZE(n) ((n-1) << 4) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 -#define UDMA_CHCTL_XFERMODE_MASK 0x00000007 -#define UDMA_CHCTL_XFERMODE_STOP 0x00000000 -#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 -#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 -#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 -#define UDMA_CHCTL_XFERMODE_MSG 0x00000004 -#define UDMA_CHCTL_XFERMODE_AMSG 0x00000005 -#define UDMA_CHCTL_XFERMODE_PSG 0x00000006 -#define UDMA_CHCTL_XFERMODE_APSG 0x00000007 -/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -137,43 +94,43 @@ typedef struct __attribute__((packed, aligned(1024))) /*===========================================================================*/ #define dmaChannelEnable(dmach) {\ - UDMA->ENASET = (1 << dmach);\ + HWREG(UDMA_ENASET) = (1 << dmach);\ } #define dmaChannelDisable(dmach) { \ - UDMA->ENACLR = (1 << dmach); \ + HWREG(UDMA_ENACLR) = (1 << dmach); \ } #define dmaChannelPrimary(dmach) {\ - UDMA->ALTCLR = (1 << dmach); \ + HWREG(UDMA_ALTCLR) = (1 << dmach); \ } #define dmaChannelAlternate(dmach) { \ - UDMA->ALTSET = (1 << dmach); \ + HWREG(UDMA_ALTSET) = (1 << dmach); \ } #define dmaChannelSingleBurst(dmach) { \ - UDMA->USEBURSTCLR = (1 << dmach); \ + HWREG(UDMA_USEBURSTCLR) = (1 << dmach); \ } #define dmaChannelBurstOnly(dmach) { \ - UDMA->USEBURSTSET = (1 << dmach); \ + HWREG(UDMA_USEBURSTSET) = (1 << dmach); \ } #define dmaChannelPriorityHigh(dmach) { \ - UDMA->PRIOSET = (1 << dmach); \ + HWREG(UDMA_PRIOSET) = (1 << dmach); \ } #define dmaChannelPriorityDefault(dmach) { \ - UDMA->PRIOCLR = (1 << dmach); \ + HWREG(UDMA_PRIOCLR) = (1 << dmach); \ } #define dmaChannelEnableRequest(dmach) {\ - UDMA->REQMASKCLR = (1 << dmach); \ + HWREG(UDMA_REQMASKCLR) = (1 << dmach); \ } #define dmaChannelDisableRequest(dmach) {\ - UDMA->REQMASKSET = (1 << dmach); \ + HWREG(UDMA_REQMASKSET) = (1 << dmach); \ } /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.c b/os/hal/ports/TIVA/TM4C123x/hal_lld.c index ddcddb3..74a6651 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.c +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.c @@ -76,60 +76,60 @@ void tiva_clock_init(void) * PLL. */ /* read */ - rcc = SYSCTL->RCC; - rcc2 = SYSCTL->RCC2; + rcc = HWREG(SYSCTL_RCC); + rcc2 = HWREG(SYSCTL_RCC2); /* modify */ - rcc |= TIVA_RCC_BYPASS; - rcc &= ~TIVA_RCC_USESYSDIV; - rcc2 |= TIVA_RCC2_BYPASS2 | TIVA_RCC2_USERCC2; + rcc |= SYSCTL_RCC_BYPASS; + rcc &= ~SYSCTL_RCC_USESYSDIV; + rcc2 |= SYSCTL_RCC2_BYPASS2 | SYSCTL_RCC2_USERCC2; /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; /* 2 Select the crystal value (XTAL) and oscillator source (OSCSRC), and * clear the PWRDN bit in RCC and RCC2. Setting the XTAL field automatically * pulls valid PLL configuration data for the appropriate crystal, and * clearing the PWRDN bit powers and enables the PLL and its output. */ /* modify */ - rcc &= ~(TIVA_RCC_OSCSRC_MASK | TIVA_RCC_XTAL_MASK | TIVA_RCC_PWRDN | TIVA_RCC_MOSCDIS); - rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (TIVA_RCC_XTAL_MASK | TIVA_RCC_OSCSRC_MASK | TIVA_RCC_MOSCDIS)); - rcc2 &= ~(TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_PWRDN2); - rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_DIV400)); + rcc &= ~(SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_XTAL_M | SYSCTL_RCC_PWRDN | SYSCTL_RCC_MOSCDIS); + rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_MOSCDIS)); + rcc2 &= ~(SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_PWRDN2); + rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_DIV400)); /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; for(i = 100000; i; i--); /* 3. Select the desired system divider (SYSDIV) in RCC and RCC2 and set the * USESYSDIV bit in RCC. The SYSDIV field determines the system frequency for * the microcontroller. */ /* modify */ - rcc &= ~TIVA_RCC_SYSDIV_MASK; - rcc |= (TIVA_SYSDIV & TIVA_RCC_SYSDIV_MASK) | TIVA_USESYSDIV; - rcc2 &= ~(TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB); - rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB)); + rcc &= ~SYSCTL_RCC_SYSDIV_M; + rcc |= (TIVA_SYSDIV & SYSCTL_RCC_SYSDIV_M) | SYSCTL_RCC_USESYSDIV; + rcc2 &= ~(SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB); + rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB)); /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; /* 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw * Interrupt Status (RIS) register. */ - while ((SYSCTL->RIS & SYSCTL_RIS_PLLLRIS) == 0); + while ((HWREG(SYSCTL_RIS) & SYSCTL_RIS_PLLLRIS) == 0); /* 5. Enable use of the PLL by clearing the BYPASS bit in RCC and RCC2. */ - rcc &= ~TIVA_RCC_BYPASS; - rcc2 &= ~TIVA_RCC2_BYPASS2; + rcc &= ~SYSCTL_RCC_BYPASS; + rcc2 &= ~SYSCTL_RCC2_BYPASS2; rcc |= (TIVA_BYPASS_VALUE << 11); rcc2 |= (TIVA_BYPASS_VALUE << 11); - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; #if HAL_USE_PWM - SYSCTL->RCC |= TIVA_PWM_FIELDS; + HWREG(SYSCTL_RCC) |= TIVA_PWM_FIELDS; #endif #if defined(TIVA_UDMA_REQUIRED) diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h index ec81806..10936c3 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h @@ -45,123 +45,6 @@ * @} */ -/** - * @name RCC register bits definitions - * @{ - */ - -#define TIVA_RCC_MOSCDIS (0x01 << 0) - -#define TIVA_RCC_OSCSRC_MASK (0x03 << 4) -#define TIVA_RCC_OSCSRC_MOSC (0x00 << 4) -#define TIVA_RCC_OSCSRC_PIOSC (0x01 << 4) -#define TIVA_RCC_OSCSRC_PIOSC_4 (0x02 << 4) -#define TIVA_RCC_OSCSRC_LFIOSC (0x03 << 4) - -#define TIVA_RCC_XTAL_MASK (0x1f << 6) -#define TIVA_RCC_XTAL_4000000 (0x06 << 6) -#define TIVA_RCC_XTAL_4096000 (0x07 << 6) -#define TIVA_RCC_XTAL_4915200 (0x08 << 6) -#define TIVA_RCC_XTAL_5000000 (0x09 << 6) -#define TIVA_RCC_XTAL_5120000 (0x0a << 6) -#define TIVA_RCC_XTAL_6000000 (0x0b << 6) -#define TIVA_RCC_XTAL_6144000 (0x0c << 6) -#define TIVA_RCC_XTAL_7372800 (0x0d << 6) -#define TIVA_RCC_XTAL_8000000 (0x0e << 6) -#define TIVA_RCC_XTAL_8192000 (0x0f << 6) -#define TIVA_RCC_XTAL_10000000 (0x10 << 6) -#define TIVA_RCC_XTAL_12000000 (0x11 << 6) -#define TIVA_RCC_XTAL_12288000 (0x12 << 6) -#define TIVA_RCC_XTAL_13560000 (0x13 << 6) -#define TIVA_RCC_XTAL_14318180 (0x14 << 6) -#define TIVA_RCC_XTAL_16000000 (0x15 << 6) -#define TIVA_RCC_XTAL_16384000 (0x16 << 6) -#define TIVA_RCC_XTAL_18000000 (0x17 << 6) -#define TIVA_RCC_XTAL_20000000 (0x18 << 6) -#define TIVA_RCC_XTAL_24000000 (0x19 << 6) -#define TIVA_RCC_XTAL_25000000 (0x1a << 6) - -#define TIVA_RCC_BYPASS (1 << 11) - -#define TIVA_RCC_PWRDN (1 << 13) - -#define TIVA_RCC_PWMDIV_MASK (0x07 << 17) -#define TIVA_RCC_PWMDIV_2 (0x00 << 17) -#define TIVA_RCC_PWMDIV_4 (0x01 << 17) -#define TIVA_RCC_PWMDIV_8 (0x02 << 17) -#define TIVA_RCC_PWMDIV_16 (0x03 << 17) -#define TIVA_RCC_PWMDIV_32 (0x04 << 17) -#define TIVA_RCC_PWMDIV_64 (0x07 << 17) - -#define TIVA_RCC_USEPWMDIV (1 << 20) - -#define TIVA_RCC_USESYSDIV (1 << 22) - -#define TIVA_RCC_SYSDIV_MASK (0x0f << 23) -#define TIVA_RCC_SYSDIV_1 (0x00 << 23) -#define TIVA_RCC_SYSDIV_2 (0x01 << 23) -#define TIVA_RCC_SYSDIV_3 (0x02 << 23) -#define TIVA_RCC_SYSDIV_4 (0x03 << 23) -#define TIVA_RCC_SYSDIV_5 (0x04 << 23) -#define TIVA_RCC_SYSDIV_6 (0x05 << 23) -#define TIVA_RCC_SYSDIV_7 (0x06 << 23) -#define TIVA_RCC_SYSDIV_8 (0x07 << 23) -#define TIVA_RCC_SYSDIV_9 (0x08 << 23) -#define TIVA_RCC_SYSDIV_10 (0x09 << 23) -#define TIVA_RCC_SYSDIV_11 (0x0a << 23) -#define TIVA_RCC_SYSDIV_12 (0x0b << 23) -#define TIVA_RCC_SYSDIV_13 (0x0c << 23) -#define TIVA_RCC_SYSDIV_14 (0x0d << 23) -#define TIVA_RCC_SYSDIV_15 (0x0e << 23) -#define TIVA_RCC_SYSDIV_16 (0x0f << 23) - -#define TIVA_RCC_ACG (1 << 27) - -/** - * @} - */ - -/** - * @name RCC2 register bits definitions - * @{ - */ - -#define TIVA_RCC2_OSCSRC2_MASK (0x07 << 4) -#define TIVA_RCC2_OSCSRC2_MOSC (0x00 << 4) -#define TIVA_RCC2_OSCSRC2_PIOSC (0x01 << 4) -#define TIVA_RCC2_OSCSRC2_PIOSC_4 (0x02 << 4) -#define TIVA_RCC2_OSCSRC2_LFIOSC (0x03 << 4) -#define TIVA_RCC2_OSCSRC2_32768 (0x07 << 4) - -#define TIVA_RCC2_BYPASS2 (1 << 11) - -#define TIVA_RCC2_PWRDN2 (1 << 13) - -#define TIVA_RCC2_USBPWRDN (1 << 14) - -#define TIVA_RCC2_SYSDIV2LSB (1 << 22) - -#define TIVA_RCC2_SYSDIV2_MASK (0x3f << 23) - -#define TIVA_RCC2_DIV400 (1 << 30) - -#define TIVA_RCC2_USERCC2 (1 << 31) - -/** - * @} - */ - -/** - * @name RIS register bits definitions - * @{ - */ - -#define SYSCTL_RIS_PLLLRIS (1 << 6) - -/** - * @} - */ - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -172,7 +55,7 @@ */ #if !defined(TIVA_OSCSRC) -#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO #endif #if !defined(TIVA_MOSC_ENABLE) @@ -217,56 +100,56 @@ /* * Oscillator-related checks. */ -#if !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_MOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC_4) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_LFIOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_32768) +#if !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO4) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_30) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_32) #error "Invalid value for TIVA_OSCSRC defined" #endif #if TIVA_XTAL_VALUE == 4000000 -#define TIVA_XTAL_ (0x06 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4MHZ #elif TIVA_XTAL_VALUE == 4096000 -#define TIVA_XTAL_ (0x07 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_09MHZ #elif TIVA_XTAL_VALUE == 4915200 -#define TIVA_XTAL_ (0x08 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_91MHZ #elif TIVA_XTAL_VALUE == 5000000 -#define TIVA_XTAL_ (0x09 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5MHZ #elif TIVA_XTAL_VALUE == 5120000 -#define TIVA_XTAL_ (0x0a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5_12MHZ #elif TIVA_XTAL_VALUE == 6000000 -#define TIVA_XTAL_ (0x0b << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6MHZ #elif TIVA_XTAL_VALUE == 6144000 -#define TIVA_XTAL_ (0x0c << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6_14MHZ #elif TIVA_XTAL_VALUE == 7372800 -#define TIVA_XTAL_ (0x0d << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_7_37MHZ #elif TIVA_XTAL_VALUE == 8000000 -#define TIVA_XTAL_ (0x0e << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8MHZ #elif TIVA_XTAL_VALUE == 8192000 -#define TIVA_XTAL_ (0x0f << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8_19MHZ #elif TIVA_XTAL_VALUE == 10000000 -#define TIVA_XTAL_ (0x10 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_10MHZ #elif TIVA_XTAL_VALUE == 12000000 -#define TIVA_XTAL_ (0x11 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12MHZ #elif TIVA_XTAL_VALUE == 12288000 -#define TIVA_XTAL_ (0x12 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12_2MHZ #elif TIVA_XTAL_VALUE == 13560000 -#define TIVA_XTAL_ (0x13 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_13_5MHZ #elif TIVA_XTAL_VALUE == 14318180 -#define TIVA_XTAL_ (0x14 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_14_3MHZ #elif TIVA_XTAL_VALUE == 16000000 -#define TIVA_XTAL_ (0x15 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16MHZ #elif TIVA_XTAL_VALUE == 16384000 -#define TIVA_XTAL_ (0x16 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16_3MHZ #elif TIVA_XTAL_VALUE == 18000000 -#define TIVA_XTAL_ (0x17 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_18MHZ #elif TIVA_XTAL_VALUE == 20000000 -#define TIVA_XTAL_ (0x18 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_20MHZ #elif TIVA_XTAL_VALUE == 24000000 -#define TIVA_XTAL_ (0x19 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_24MHZ #elif TIVA_XTAL_VALUE == 25000000 -#define TIVA_XTAL_ (0x1a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_25MHZ #else #error "Invalid value for TIVA_XTAL_VALUE defined" #endif diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk index 0abafcc..ae1ea08 100644 --- a/os/hal/ports/TIVA/TM4C123x/platform.mk +++ b/os/hal/ports/TIVA/TM4C123x/platform.mk @@ -1,18 +1,58 @@ # List of all the TM4C123x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_i2c_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_gpt_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pwm_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_spi_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/tiva_udma.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c +ifeq ($(USE_SMART_BUILD),yes) +HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define")) + +PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c +ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c +endif +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c +endif +ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c +endif +ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c +endif +ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c +endif +ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c +endif +ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c +endif +ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c +endif +else +PLATFORMSRC := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c +endif # Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD +PLATFORMINC := ${CHIBIOS}/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_isr.h b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h index b380e46..9d41434 100644 --- a/os/hal/ports/TIVA/TM4C123x/tiva_isr.h +++ b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h @@ -42,11 +42,11 @@ #define TIVA_UDMA_ERR_NUMBER 47 /* GPIO units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) \ - || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM) \ - || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) \ + || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1236D5PM) \ + || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -63,11 +63,11 @@ #define TIVA_GPIOF_NUMBER 30 #define TIVA_GPIOG_NUMBER 31 #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -82,11 +82,11 @@ #define TIVA_GPIOE_NUMBER 4 #define TIVA_GPIOF_NUMBER 30 #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ) \ - || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PZ) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PZ) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -111,8 +111,8 @@ #define TIVA_GPIOK_NUMBER 55 #define TIVA_GPIOL_NUMBER 56 #endif -#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\ - || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE) +#if defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1237H6PGE)\ + || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123GH6PGE) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -157,7 +157,7 @@ #define TIVA_GPIOP6_NUMBER 122 #define TIVA_GPIOP7_NUMBER 123 #endif -#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -220,23 +220,23 @@ #endif /* GPTM units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_GPT0A_HANDLER Vector8C #define TIVA_GPT0B_HANDLER Vector90 #define TIVA_GPT1A_HANDLER Vector94 @@ -291,46 +291,46 @@ #endif /* WDT units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_WDT_HANDLER Vector88 #define TIVA_WDT_NUMBER 18 #endif /* ADC units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_ADC0_SEQ0_HANDLER Vector78 #define TIVA_ADC0_SEQ1_HANDLER Vector7C #define TIVA_ADC0_SEQ2_HANDLER Vector80 @@ -351,23 +351,23 @@ #endif /* UART units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_UART0_HANDLER Vector54 #define TIVA_UART1_HANDLER Vector58 #define TIVA_UART2_HANDLER VectorC4 @@ -388,23 +388,23 @@ #endif /* SPI units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_SSI0_HANDLER Vector5C #define TIVA_SSI1_HANDLER VectorC8 #define TIVA_SSI2_HANDLER Vector124 @@ -417,18 +417,18 @@ #endif /* I2C units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \ - || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) \ - || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PGE) \ + || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) \ + || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_I2C0_HANDLER Vector60 #define TIVA_I2C1_HANDLER VectorD4 #define TIVA_I2C2_HANDLER Vector150 @@ -443,11 +443,11 @@ #define TIVA_I2C4_NUMBER 109 #define TIVA_I2C5_NUMBER 110 #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_I2C0_HANDLER Vector60 #define TIVA_I2C1_HANDLER VectorD4 #define TIVA_I2C2_HANDLER Vector150 @@ -460,28 +460,28 @@ #endif /* CAN units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) #define TIVA_CAN0_HANDLER VectorDC #define TIVA_CAN0_NUMBER 39 #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_CAN0_HANDLER VectorDC #define TIVA_CAN1_HANDLER VectorE0 @@ -490,55 +490,55 @@ #endif /* USB units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) /* No interrupt handler and number.*/ #endif -#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) \ - || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \ - || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) \ + || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) \ + || defined(PART_TM4C123GH5ZXR) #define TIVA_USB0_HANDLER VectorF0 #define TIVA_USB0_NUMBER 44 #endif /* AC units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM) \ - || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM) \ - || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || defined(PART_TM4C1233E6PM) \ + || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_AC0_HANDLER VectorA4 #define TIVA_AC1_HANDLER VectorA8 #define TIVA_AC0_NUMBER 25 #define TIVA_AC1_NUMBER 26 #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE) \ - || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \ - || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PGE) \ + || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1237D5PZ) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PZ) \ + || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE)\ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_AC0_HANDLER VectorA4 #define TIVA_AC1_HANDLER VectorA8 #define TIVA_AC2_HANDLER VectorAC @@ -549,26 +549,26 @@ #endif /* PWM units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) /* No interrupt handler and number.*/ #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_PWM0FAULT_HANDLER Vector64 #define TIVA_PWM0GEN0_HANDLER Vector68 #define TIVA_PWM0GEN1_HANDLER Vector6C @@ -593,25 +593,25 @@ #endif /* QEI units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) /* No interrupt handler and number.*/ #endif -#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_QEI0_HANLDER Vector74 #define TIVA_QEI1_HANLDER VectorD8 diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h index ac7a1d2..88cc376 100644 --- a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h +++ b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h @@ -29,32 +29,32 @@ /* Defined device check. */ /*===========================================================================*/ -#if !defined(TM4C1230C3PM) && !defined(TM4C1230D5PM) && \ - !defined(TM4C1230E6PM) && !defined(TM4C1230H6PM) && \ - !defined(TM4C1231C3PM) && !defined(TM4C1231D5PM) && \ - !defined(TM4C1231D5PZ) && !defined(TM4C1231E6PM) && \ - !defined(TM4C1231E6PZ) && !defined(TM4C1231H6PGE) && \ - !defined(TM4C1231H6PM) && !defined(TM4C1231H6PZ) && \ - !defined(TM4C1232C3PM) && !defined(TM4C1232D5PM) && \ - !defined(TM4C1232E6PM) && !defined(TM4C1232H6PM) && \ - !defined(TM4C1233C3PM) && !defined(TM4C1233D5PM) && \ - !defined(TM4C1233D5PZ) && !defined(TM4C1233E6PM) && \ - !defined(TM4C1233E6PZ) && !defined(TM4C1233H6PGE) && \ - !defined(TM4C1233H6PM) && !defined(TM4C1233H6PZ) && \ - !defined(TM4C1236D5PM) && !defined(TM4C1236E6PM) && \ - !defined(TM4C1236H6PM) && !defined(TM4C1237D5PM) && \ - !defined(TM4C1237D5PZ) && !defined(TM4C1237E6PM) && \ - !defined(TM4C1237E6PZ) && !defined(TM4C1237H6PGE) && \ - !defined(TM4C1237H6PM) && !defined(TM4C1237H6PZ) && \ - !defined(TM4C123AE6PM) && !defined(TM4C123AH6PM) && \ - !defined(TM4C123BE6PM) && !defined(TM4C123BE6PZ) && \ - !defined(TM4C123BH6PGE) && !defined(TM4C123BH6PM) && \ - !defined(TM4C123BH6PZ) && !defined(TM4C123BH6ZRB) && \ - !defined(TM4C123FE6PM) && !defined(TM4C123FH6PM) && \ - !defined(TM4C123GE6PM) && !defined(TM4C123GE6PZ) && \ - !defined(TM4C123GH6PGE) && !defined(TM4C123GH6PM) && \ - !defined(TM4C123GH6PZ) && !defined(TM4C123GH6ZRB) && \ - !defined(TM4C123GH5ZXR) +#if !defined(PART_TM4C1230C3PM) && !defined(PART_TM4C1230D5PM) && \ + !defined(PART_TM4C1230E6PM) && !defined(PART_TM4C1230H6PM) && \ + !defined(PART_TM4C1231C3PM) && !defined(PART_TM4C1231D5PM) && \ + !defined(PART_TM4C1231D5PZ) && !defined(PART_TM4C1231E6PM) && \ + !defined(PART_TM4C1231E6PZ) && !defined(PART_TM4C1231H6PGE) && \ + !defined(PART_TM4C1231H6PM) && !defined(PART_TM4C1231H6PZ) && \ + !defined(PART_TM4C1232C3PM) && !defined(PART_TM4C1232D5PM) && \ + !defined(PART_TM4C1232E6PM) && !defined(PART_TM4C1232H6PM) && \ + !defined(PART_TM4C1233C3PM) && !defined(PART_TM4C1233D5PM) && \ + !defined(PART_TM4C1233D5PZ) && !defined(PART_TM4C1233E6PM) && \ + !defined(PART_TM4C1233E6PZ) && !defined(PART_TM4C1233H6PGE) && \ + !defined(PART_TM4C1233H6PM) && !defined(PART_TM4C1233H6PZ) && \ + !defined(PART_TM4C1236D5PM) && !defined(PART_TM4C1236E6PM) && \ + !defined(PART_TM4C1236H6PM) && !defined(PART_TM4C1237D5PM) && \ + !defined(PART_TM4C1237D5PZ) && !defined(PART_TM4C1237E6PM) && \ + !defined(PART_TM4C1237E6PZ) && !defined(PART_TM4C1237H6PGE) && \ + !defined(PART_TM4C1237H6PM) && !defined(PART_TM4C1237H6PZ) && \ + !defined(PART_TM4C123AE6PM) && !defined(PART_TM4C123AH6PM) && \ + !defined(PART_TM4C123BE6PM) && !defined(PART_TM4C123BE6PZ) && \ + !defined(PART_TM4C123BH6PGE) && !defined(PART_TM4C123BH6PM) && \ + !defined(PART_TM4C123BH6PZ) && !defined(PART_TM4C123BH6ZRB) && \ + !defined(PART_TM4C123FE6PM) && !defined(PART_TM4C123FH6PM) && \ + !defined(PART_TM4C123GE6PM) && !defined(PART_TM4C123GE6PZ) && \ + !defined(PART_TM4C123GH6PGE) && !defined(PART_TM4C123GH6PM) && \ + !defined(PART_TM4C123GH6PZ) && !defined(PART_TM4C123GH6ZRB) && \ + !defined(PART_TM4C123GH5ZXR) #error "No valid device defined." #endif @@ -75,11 +75,11 @@ */ /* GPIO attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) \ - || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM) \ - || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) \ + || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1236D5PM) \ + || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -100,11 +100,11 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 56 #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -125,11 +125,11 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 48 #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ) \ - || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PZ) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PZ) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -150,8 +150,8 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 88 #endif -#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\ - || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE) +#if defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1237H6PGE)\ + || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123GH6PGE) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -172,7 +172,7 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 112 #endif -#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -195,23 +195,23 @@ #endif /* GPTM attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_GPT0 TRUE #define TIVA_HAS_GPT1 TRUE #define TIVA_HAS_GPT2 TRUE @@ -229,67 +229,67 @@ #endif /* WDT attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_WDT0 TRUE #define TIVA_HAS_WDT1 TRUE #endif /* ADC attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_ADC0 TRUE #define TIVA_HAS_ADC1 TRUE #endif /* UART attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_UART0 TRUE #define TIVA_HAS_UART1 TRUE #define TIVA_HAS_UART2 TRUE @@ -301,23 +301,23 @@ #endif /* SPI attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_SSI0 TRUE #define TIVA_HAS_SSI1 TRUE #define TIVA_HAS_SSI2 TRUE @@ -325,18 +325,18 @@ #endif /* I2C attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \ - || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) \ - || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PGE) \ + || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) \ + || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_I2C0 TRUE #define TIVA_HAS_I2C1 TRUE #define TIVA_HAS_I2C2 TRUE @@ -348,11 +348,11 @@ #define TIVA_HAS_I2C8 FALSE #define TIVA_HAS_I2C9 FALSE #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_HAS_I2C0 TRUE #define TIVA_HAS_I2C1 TRUE #define TIVA_HAS_I2C2 TRUE @@ -366,129 +366,129 @@ #endif /* CAN attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) #define TIVA_HAS_CAN0 TRUE #define TIVA_HAS_CAN1 FALSE #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_CAN0 TRUE #define TIVA_HAS_CAN1 TRUE #endif /* USB attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) #define TIVA_HAS_USB0 FALSE #endif -#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) \ - || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \ - || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) \ + || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) \ + || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_USB0 TRUE #endif /* AC attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM) \ - || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM) \ - || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || defined(PART_TM4C1233E6PM) \ + || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_HAS_AC0 TRUE #define TIVA_HAS_AC1 TRUE #define TIVA_HAS_AC2 FALSE #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE) \ - || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \ - || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PGE) \ + || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1237D5PZ) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PZ) \ + || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE)\ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_AC0 TRUE #define TIVA_HAS_AC1 TRUE #define TIVA_HAS_AC2 TRUE #endif /* PWM attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) #define TIVA_HAS_PWM0 FALSE #define TIVA_HAS_PWM1 FALSE #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_PWM0 TRUE #define TIVA_HAS_PWM1 TRUE #endif /* QEI attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) #define TIVA_HAS_QEI0 FALSE #define TIVA_HAS_QEI1 FALSE #endif -#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_QEI0 TRUE #define TIVA_HAS_QEI1 TRUE #endif diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.c b/os/hal/ports/TIVA/TM4C129x/hal_lld.c index 60d6763..e12ab5e 100644 --- a/os/hal/ports/TIVA/TM4C129x/hal_lld.c +++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.c @@ -76,8 +76,8 @@ void tiva_clock_init(void) /* * 2. Power up the MOSC by clearing the NOXTAL bit in the MOSCCTL register. */ - moscctl = SYSCTL->MOSCCTL; - moscctl &= ~MOSCCTL_NOXTAL; + moscctl = HWREG(SYSCTL_MOSCCTL); + moscctl &= ~SYSCTL_MOSCCTL_NOXTAL; /* * 3. If single-ended MOSC mode is required, the MOSC is ready to use. If crystal mode is required, @@ -85,18 +85,18 @@ void tiva_clock_init(void) * (RIS), indicating MOSC crystal mode is ready. */ #if TIVA_MOSC_SINGLE_ENDED - SYSCTL->MOSCCTL = moscctl; + HWREG(SYSCTL_MOSCCTL) = moscctl; #else - moscctl &= ~MOSCCTL_PWRDN; - SYSCTL->MOSCCTL = moscctl; + moscctl &= ~SYSCTL_MOSCCTL_PWRDN; + HWREG(SYSCTL_MOSCCTL) = moscctl; - while (!(SYSCTL->RIS & SYSCTL_RIS_MOSCPUPRIS)); + while (!(HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS)); #endif /* * 4. Set the OSCSRC field to 0x3 in the RSCLKCFG register at offset 0x0B0. */ - rsclkcfg = SYSCTL->RSCLKCFG; + rsclkcfg = HWREG(SYSCTL_RSCLKCFG); rsclkcfg |= TIVA_RSCLKCFG_OSCSRC; @@ -109,44 +109,42 @@ void tiva_clock_init(void) * 6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to * the configure the desired VCO frequency setting. */ - SYSCTL->PLLFREQ1 = (0x04 << 0); // 5 - 1 - SYSCTL->PLLFREQ0 = (0x60 << 0) | PLLFREQ0_PLLPWR; + HWREG(SYSCTL_PLLFREQ1) = (0x04 << 0); // 5 - 1 + HWREG(SYSCTL_PLLFREQ0) = (0x60 << 0) | SYSCTL_PLLFREQ0_PLLPWR; /* * 7. Write the MEMTIM0 register to correspond to the new system clock setting. */ - SYSCTL->MEMTIM0 = (MEMTIM0_FBCHT_3_5 | MEMTIM0_FWS_5 | MEMTIM0_EBCHT_3_5 | MEMTIM0_EWS_5 | MEMTIM0_MB1); + HWREG(SYSCTL_MEMTIM0) = (SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) | SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) | SYSCTL_MEMTIM0_MB1); /* * Wait for the PLLSTAT register to indicate the PLL has reached lock at the new operating point * (or that a timeout period has passed and lock has failed, in which case an error condition exists * and this sequence is abandoned and error processing is initiated). */ - while (!SYSCTL->PLLSTAT & PLLSTAT_LOCK); + while (!HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK); /* * 9. Write the RSCLKCFG register's PSYSDIV value, set the USEPLL bit to enabled, and MEMTIMU * bit. */ - rsclkcfg = SYSCTL->RSCLKCFG; + rsclkcfg = HWREG(SYSCTL_RSCLKCFG); - rsclkcfg |= (RSCLKCFG_USEPLL | (0x03 << 0) | (0x03 << 20) | (0x03 << 24)); + rsclkcfg |= (SYSCTL_RSCLKCFG_USEPLL | (0x03 << 0) | (0x03 << 20) | (0x03 << 24)); //rsclkcfg |= ((0x03 << 0) | (1 << 28) | (0x03 << 20)); - rsclkcfg |= RSCLKCFG_MEMTIMU; + rsclkcfg |= SYSCTL_RSCLKCFG_MEMTIMU; // set new configuration - SYSCTL->RSCLKCFG = rsclkcfg; + HWREG(SYSCTL_RSCLKCFG) = rsclkcfg; #if HAL_USE_PWM #if TIVA_PWM_USE_PWM0 - PWM0->CC = TIVA_PWM_FIELDS; + HWREG(PWM0_CC) = TIVA_PWM_FIELDS; #endif #endif } -/** - * @} - */ +/** @} */ diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.h b/os/hal/ports/TIVA/TM4C129x/hal_lld.h index e5c667d..3768957 100644 --- a/os/hal/ports/TIVA/TM4C129x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.h @@ -38,170 +38,8 @@ * @name Platform identification * @{ */ - #define PLATFORM_NAME "Tiva C Series TM4C129x" - -/** - * @} - */ - -/** - * @name RIS register bits definitions - * @{ - */ - -#define SYSCTL_RIS_PLLLRIS (1 << 6) -#define SYSCTL_RIS_MOSCPUPRIS (1 << 8) - -/** - * @} - */ - -/** - * @name MOSCCTL register bits definitions - * @{ - */ - -#define MOSCCTL_CVAL (1 << 0) -#define MOSCCTL_MOSCIM (1 << 1) -#define MOSCCTL_NOXTAL (1 << 2) -#define MOSCCTL_PWRDN (1 << 3) -#define MOSCCTL_OSCRNG (1 << 4) - -/** - * @} - */ - -/** - * @name RSCLKCFG register bits definitions - * @{ - */ - -#define RSCLKCFG_PSYSDIV_bm (0xfffff << 0) -#define RSCLKCFG_OSYSDIV_bm (0xfffff << 10 - -#define RSCLKCFG_OSCSRC_bm (0xff << 20) -#define RSCLKCFG_OSCSRC_PIOSC (0 << 20) -#define RSCLKCFG_OSCSRC_LFIOSC (0x02 << 20) -#define RSCLKCFG_OSCSRC_MOSC (0x03 << 20) -#define RSCLKCFG_OSCSRC_RTCOSC (0x04 << 20) - -#define RSCLKCFG_PLLSRC_bm (0xff << 24) -#define RSCLKCFG_PLLSRC_PIOSC (0 << 24) -#define RSCLKCFG_PLLSRC_MOSC (0x03 << 24) - -#define RSCLKCFG_USEPLL (1 << 28) - -#define RSCLKCFG_ACG (1 << 29) - -#define RSCLKCFG_NEWFREQ (1 << 30) - -#define RSCLKCFG_MEMTIMU (1 << 31) - -/** - * @} - */ - -/** - * @name PLLFREQ0 register bits definitions - * The PLL frequency can be calculated using the following equation: - * fVCO = (fIN * MDIV) - * where - * fIN = fXTAL/(Q+1)(N+1) or fPIOSC/(Q+1)(N+1) - * MDIV = MINT + (MFRAC / 1024) - * The Q and N values are programmed in the PLLFREQ1 register. Note that to reduce jitter, MFRAC - * should be programmed to 0x0. - * @{ - */ - -#define PLLFREQ0_MINT_bm (0xfffff << 0) -#define PLLFREQ0_MFRAC_bm (0xfffff << 10) -#define PLLFREQ0_PLLPWR (1 << 23) - -/** - * @} - */ - -/** - * @name PLLFREQ1 register bits definitions - * @{ - */ - -#define PLLFREQ1_N_bm (0x7ff << 0) -#define PLLFREQ1_Q_bm (0x7ff << 8) - -/** - * @} - */ - -/** - * @name MEMTIM0 register bits definitions - * @{ - */ - -#define MEMTIM0_FWS_bm (0xff << 0) -#define MEMTIM0_FWS_0 (0x00 << 0) -#define MEMTIM0_FWS_1 (0x01 << 0) -#define MEMTIM0_FWS_2 (0x02 << 0) -#define MEMTIM0_FWS_3 (0x03 << 0) -#define MEMTIM0_FWS_4 (0x04 << 0) -#define MEMTIM0_FWS_5 (0x05 << 0) -#define MEMTIM0_FWS_6 (0x06 << 0) -#define MEMTIM0_FWS_7 (0x07 << 0) - -#define MEMTIM0_FBCE (1 << 5) - -#define MEMTIM0_FBCHT_bm (0xff << 6) -#define MEMTIM0_FBCHT_0_5 (0x00 << 6) -#define MEMTIM0_FBCHT_1 (0x01 << 6) -#define MEMTIM0_FBCHT_1_5 (0x02 << 6) -#define MEMTIM0_FBCHT_2 (0x03 << 6) -#define MEMTIM0_FBCHT_2_5 (0x04 << 6) -#define MEMTIM0_FBCHT_3 (0x05 << 6) -#define MEMTIM0_FBCHT_3_5 (0x06 << 6) -#define MEMTIM0_FBCHT_4 (0x07 << 6) -#define MEMTIM0_FBCHT_4_5 (0x08 << 6) - -#define MEMTIM0_EWS_bm (0xff << 16) -#define MEMTIM0_EWS_0 (0x00 << 16) -#define MEMTIM0_EWS_1 (0x01 << 16) -#define MEMTIM0_EWS_2 (0x02 << 16) -#define MEMTIM0_EWS_3 (0x03 << 16) -#define MEMTIM0_EWS_4 (0x04 << 16) -#define MEMTIM0_EWS_5 (0x05 << 16) -#define MEMTIM0_EWS_6 (0x06 << 16) -#define MEMTIM0_EWS_7 (0x07 << 16) - -#define MEMTIM0_EBCE (1 << 21) - -#define MEMTIM0_EBCHT_bm (0xff << 22) -#define MEMTIM0_EBCHT_0_5 (0x00 << 22) -#define MEMTIM0_EBCHT_1 (0x01 << 22) -#define MEMTIM0_EBCHT_1_5 (0x02 << 22) -#define MEMTIM0_EBCHT_2 (0x03 << 22) -#define MEMTIM0_EBCHT_2_5 (0x04 << 22) -#define MEMTIM0_EBCHT_3 (0x05 << 22) -#define MEMTIM0_EBCHT_3_5 (0x06 << 22) -#define MEMTIM0_EBCHT_4 (0x07 << 22) -#define MEMTIM0_EBCHT_4_5 (0x08 << 22) - -// XXX: what is this? -#define MEMTIM0_MB1 0x00100010 // MB1 = Must be one - -/** - * @} - */ - -/** - * @name PLLSTAT register bits definitions - * @{ - */ - -#define PLLSTAT_LOCK (1 << 0) - -/** - * @} - */ +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -212,7 +50,7 @@ #endif #if !defined(TIVA_RSCLKCFG_OSCSRC) -#define TIVA_RSCLKCFG_OSCSRC RSCLKCFG_OSCSRC_MOSC +#define TIVA_RSCLKCFG_OSCSRC SYSCTL_RSCLKCFG_OSCSRC_MOSC #endif /*===========================================================================*/ @@ -229,55 +67,55 @@ /* * Oscillator-related checks. */ -#if !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_PIOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_LFIOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_MOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_RTCOSC) +#if !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_PIOSC) && \ + !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_LFIOSC) && \ + !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_MOSC) && \ + !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_RTC) #error "Invalid value for TIVA_RSCLKCFG_OSCSRC defined" #endif #if TIVA_XTAL_VALUE == 4000000 -#define TIVA_XTAL_ (0x06 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4MHZ #elif TIVA_XTAL_VALUE == 4096000 -#define TIVA_XTAL_ (0x07 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_09MHZ #elif TIVA_XTAL_VALUE == 4915200 -#define TIVA_XTAL_ (0x08 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_91MHZ #elif TIVA_XTAL_VALUE == 5000000 -#define TIVA_XTAL_ (0x09 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5MHZ #elif TIVA_XTAL_VALUE == 5120000 -#define TIVA_XTAL_ (0x0a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5_12MHZ #elif TIVA_XTAL_VALUE == 6000000 -#define TIVA_XTAL_ (0x0b << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6MHZ #elif TIVA_XTAL_VALUE == 6144000 -#define TIVA_XTAL_ (0x0c << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6_14MHZ #elif TIVA_XTAL_VALUE == 7372800 -#define TIVA_XTAL_ (0x0d << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_7_37MHZ #elif TIVA_XTAL_VALUE == 8000000 -#define TIVA_XTAL_ (0x0e << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8MHZ #elif TIVA_XTAL_VALUE == 8192000 -#define TIVA_XTAL_ (0x0f << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8_19MHZ #elif TIVA_XTAL_VALUE == 10000000 -#define TIVA_XTAL_ (0x10 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_10MHZ #elif TIVA_XTAL_VALUE == 12000000 -#define TIVA_XTAL_ (0x11 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12MHZ #elif TIVA_XTAL_VALUE == 12288000 -#define TIVA_XTAL_ (0x12 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12_2MHZ #elif TIVA_XTAL_VALUE == 13560000 -#define TIVA_XTAL_ (0x13 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_13_5MHZ #elif TIVA_XTAL_VALUE == 14318180 -#define TIVA_XTAL_ (0x14 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_14_3MHZ #elif TIVA_XTAL_VALUE == 16000000 -#define TIVA_XTAL_ (0x15 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16MHZ #elif TIVA_XTAL_VALUE == 16384000 -#define TIVA_XTAL_ (0x16 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16_3MHZ #elif TIVA_XTAL_VALUE == 18000000 -#define TIVA_XTAL_ (0x17 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_18MHZ #elif TIVA_XTAL_VALUE == 20000000 -#define TIVA_XTAL_ (0x18 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_20MHZ #elif TIVA_XTAL_VALUE == 24000000 -#define TIVA_XTAL_ (0x19 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_24MHZ #elif TIVA_XTAL_VALUE == 25000000 -#define TIVA_XTAL_ (0x1a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_25MHZ #else #error "Invalid value for TIVA_XTAL_VALUE defined" #endif diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk index b8363f3..18ed48d 100644 --- a/os/hal/ports/TIVA/TM4C129x/platform.mk +++ b/os/hal/ports/TIVA/TM4C129x/platform.mk @@ -1,14 +1,63 @@ # List of all the TM4C129x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ +ifeq ($(USE_SMART_BUILD),yes) +HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define")) + +PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x/hal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c +ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c +endif +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c +endif +ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c +endif +ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c +endif +ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c +endif +ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c +endif +ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c +endif +ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c +endif +ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c +endif +else +PLATFORMSRC := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_mac_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c +endif # Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ +PLATFORMINC := ${CHIBIOS}/os/hal/ports/common/ARMCMx \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/MAC \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_isr.h b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h index 255bfd6..330d5c6 100644 --- a/os/hal/ports/TIVA/TM4C129x/tiva_isr.h +++ b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h @@ -35,9 +35,9 @@ */ /* GPIO units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -98,10 +98,10 @@ #define TIVA_GPIOQ6_NUMBER 90 #define TIVA_GPIOQ7_NUMBER 91 #endif -#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\ - || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -170,85 +170,85 @@ #endif /* EPI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_EPI0_HANDLER Vector108 #define TIVA_EPI0_NUMBER 50 #endif /* CRC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) /* CRC has no interrupts.*/ #endif /* AES Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) /* no interrupts.*/ #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) \ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_AES_HANDLER Vector1BC #define TIVA_AES_NUMBER 95 #endif /* DES Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) /* no interrupts.*/ #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_DES_HANDLER Vector1C0 #define TIVA_DES_NUMBER 51 #endif /* SHA/MD5 Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) /* no interrupts.*/ #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_SHA_MD5_HANDLER Vector1B8 #define TIVA_SHA_MD5_NUMBER 94 #endif /* GPT units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_GPT0A_HANDLER Vector8C #define TIVA_GPT0B_HANDLER Vector90 #define TIVA_GPT1A_HANDLER Vector94 @@ -285,26 +285,26 @@ #endif /* WDT units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_WDT_HANDLER Vector88 #define TIVA_WDT_NUMBER 18 #endif /* ADC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_ADC0_SEQ0_HANDLER Vector78 #define TIVA_ADC0_SEQ1_HANDLER Vector7C #define TIVA_ADC0_SEQ2_HANDLER Vector80 @@ -325,13 +325,13 @@ #endif /* UART units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_UART0_HANDLER Vector54 #define TIVA_UART1_HANDLER Vector58 #define TIVA_UART2_HANDLER VectorC4 @@ -352,13 +352,13 @@ #endif /* QSSI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_QSSI0_HANDLER Vector5C #define TIVA_QSSI1_HANDLER VectorC8 #define TIVA_QSSI2_HANDLER Vector118 @@ -371,13 +371,13 @@ #endif /* I2C units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_I2C0_HANDLER Vector60 #define TIVA_I2C1_HANDLER VectorD4 #define TIVA_I2C2_HANDLER Vector134 @@ -402,28 +402,28 @@ #endif /* 1-Wire Master units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) #define TIVA_HAS_1WIRE FALSE #endif -#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_1WIRE_HANDLER Vector1E4 #define TIVA_1WIRE_NUMBER 105 #endif /* CAN units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_CAN0_HANDLER VectorD8 #define TIVA_CAN1_HANDLER VectorDC @@ -432,69 +432,69 @@ #endif /* Ethernet MAC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\ - || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1297NCZAD)\ + || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) /* no interrupts.*/ #endif -#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_MAC_HANDLER VectorE0 #define TIVA_MAC_NUMBER 40 #endif /* Ethernet PHY units.*/ -#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \ - || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) +#if defined(PART_TM4C1290NCPDT)|| defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) \ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) /* no interrupts.*/ #endif -#if defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\ - || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) /* no interrupts.*/ #endif /* USB units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_USB0_HANDLER VectorE8 #define TIVA_USB0_NUMBER 42 #endif /* LCD units.*/ -#if defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_LCD_HANDLER Vector1C4 #define TIVA_LCD_NUMBER 97 #endif -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) /* no interrupts.*/ #endif /* AC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_AC0_HANDLER VectorA4 #define TIVA_AC1_HANDLER VectorA8 #define TIVA_AC2_HANDLER VectorAC @@ -505,13 +505,13 @@ #endif /* PWM units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_PWM0FAULT_HANDLER Vector64 #define TIVA_PWM0GEN0_HANDLER Vector68 #define TIVA_PWM0GEN1_HANDLER Vector6C @@ -526,13 +526,13 @@ #endif /* QEI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_QEI0_HANLDER Vector74 #define TIVA_QEI0_NUMBER 13 diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h index 5815351..99e4f81 100644 --- a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h +++ b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h @@ -35,9 +35,9 @@ */ /* GPIO attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -57,10 +57,10 @@ #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE #endif -#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\ - || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -82,77 +82,77 @@ #endif /* EPI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_EPI0 TRUE #endif /* CRC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_CRC0 TRUE #endif /* AES Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) #define TIVA_HAS_AES FALSE #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) \ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_AES TRUE #endif /* DES Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) #define TIVA_HAS_DES FALSE #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_DES TRUE #endif /* SHA/MD5 Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) #define TIVA_HAS_SHA_MD5 FALSE #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_SHA_MD5 TRUE #endif /* GPT attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_GPT0 TRUE #define TIVA_HAS_GPT1 TRUE #define TIVA_HAS_GPT2 TRUE @@ -170,37 +170,37 @@ #endif /* WDT attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_WDT0 TRUE #define TIVA_HAS_WDT1 TRUE #endif /* ADC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_ADC0 TRUE #define TIVA_HAS_ADC1 TRUE #endif /* UART attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_UART0 TRUE #define TIVA_HAS_UART1 TRUE #define TIVA_HAS_UART2 TRUE @@ -212,13 +212,13 @@ #endif /* QSSI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_QSSI0 TRUE #define TIVA_HAS_QSSI1 TRUE #define TIVA_HAS_QSSI2 TRUE @@ -226,13 +226,13 @@ #endif /* I2C attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_I2C0 TRUE #define TIVA_HAS_I2C1 TRUE #define TIVA_HAS_I2C2 TRUE @@ -246,113 +246,113 @@ #endif /* 1-Wire Master attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) #define TIVA_HAS_1WIRE FALSE #endif -#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_1WIRE TRUE #endif /* CAN attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_CAN0 TRUE #define TIVA_HAS_CAN1 TRUE #endif /* Ethernet MAC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\ - || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1297NCZAD)\ + || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) #define TIVA_HAS_ETHERNET_MAC FALSE #endif -#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_ETHERNET_MAC TRUE #endif /* Ethernet PHY attributes.*/ -#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \ - || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) +#if defined(PART_TM4C1290NCPDT)|| defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) \ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) #define TIVA_HAS_ETHERNET_PHY FALSE #endif -#if defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\ - || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_ETHERNET_PHY TRUE #endif /* USB attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_USB0 TRUE #endif /* LCD attributes.*/ -#if defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_LCD TRUE #endif -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) #define TIVA_HAS_LCD FALSE #endif /* AC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_AC0 TRUE #define TIVA_HAS_AC1 TRUE #define TIVA_HAS_AC2 TRUE #endif /* PWM attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_PWM0 TRUE #define TIVA_HAS_PWM1 FALSE #endif /* QEI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_QEI0 TRUE #define TIVA_HAS_QEI1 FALSE #endif diff --git a/os/hal/src/hal_nand.c b/os/hal/src/hal_nand.c index 24dd6de..e1b298a 100644 --- a/os/hal/src/hal_nand.c +++ b/os/hal/src/hal_nand.c @@ -80,16 +80,13 @@ static void pagesize_check(size_t page_data_size) { */ static void calc_addr(const NANDConfig *cfg, uint32_t block, uint32_t page, uint32_t page_offset, uint8_t *addr, size_t addr_len) { - size_t i = 0; - uint32_t row = 0; + size_t i; + uint32_t row; - /* Incorrect buffer length.*/ osalDbgCheck(cfg->rowcycles + cfg->colcycles == addr_len); osalDbgCheck((block < cfg->blocks) && (page < cfg->pages_per_block) && (page_offset < cfg->page_data_size + cfg->page_spare_size)); - /* convert address to NAND specific */ - memset(addr, 0, addr_len); row = (block * cfg->pages_per_block) + page; for (i=0; i<cfg->colcycles; i++){ addr[i] = page_offset & 0xFF; @@ -115,17 +112,14 @@ static void calc_addr(const NANDConfig *cfg, uint32_t block, uint32_t page, */ static void calc_blk_addr(const NANDConfig *cfg, uint32_t block, uint8_t *addr, size_t addr_len) { - size_t i = 0; - uint32_t row = 0; + size_t i; + uint32_t row; - /* Incorrect buffer length.*/ - osalDbgCheck(cfg->rowcycles == addr_len); - osalDbgCheck((block < cfg->blocks)); + osalDbgCheck(cfg->rowcycles == addr_len); /* Incorrect buffer length */ + osalDbgCheck(block < cfg->blocks); /* Overflow */ - /* convert address to NAND specific */ - memset(addr, 0, addr_len); row = block * cfg->pages_per_block; - for (i=0; i<addr_len; i++){ + for (i=0; i<addr_len; i++) { addr[i] = row & 0xFF; row = row >> 8; } @@ -415,7 +409,6 @@ void nandReadPageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, const uint8_t *spare, size_t sparelen) { - uint8_t retVal; const NANDConfig *cfg = nandp->config; uint8_t addr[8]; size_t addrlen = cfg->rowcycles + cfg->colcycles; @@ -425,8 +418,7 @@ uint8_t nandWritePageSpare(NANDDriver *nandp, uint32_t block, uint32_t page, osalDbgAssert(nandp->state == NAND_READY, "invalid state"); calc_addr(cfg, block, page, cfg->page_data_size, addr, addrlen); - retVal = nand_lld_write_data(nandp, spare, sparelen, addr, addrlen, NULL); - return retVal; + return nand_lld_write_data(nandp, spare, sparelen, addr, addrlen, NULL); } /** @@ -478,7 +470,6 @@ uint8_t nandReadBadMark(NANDDriver *nandp, uint32_t block, uint32_t page) { */ uint8_t nandErase(NANDDriver *nandp, uint32_t block) { - uint8_t retVal; const NANDConfig *cfg = nandp->config; uint8_t addr[4]; size_t addrlen = cfg->rowcycles; @@ -487,8 +478,7 @@ uint8_t nandErase(NANDDriver *nandp, uint32_t block) { osalDbgAssert(nandp->state == NAND_READY, "invalid state"); calc_blk_addr(cfg, block, addr, addrlen); - retVal = nand_lld_erase(nandp, addr, addrlen); - return retVal; + return nand_lld_erase(nandp, addr, addrlen); } /** diff --git a/os/hal/src/hal_onewire.c b/os/hal/src/hal_onewire.c index a93eec0..06e63e6 100644 --- a/os/hal/src/hal_onewire.c +++ b/os/hal/src/hal_onewire.c @@ -46,7 +46,7 @@ on every timer overflow event. */ /** - * @file onewire.c + * @file hal_onewire.c * @brief 1-wire Driver code. * * @addtogroup onewire @@ -251,7 +251,6 @@ static void ow_write_bit_I(onewireDriver *owp, ioline_t bit) { static void ow_reset_cb(PWMDriver *pwmp, onewireDriver *owp) { owp->reg.slave_present = (PAL_LOW == ow_read_bit(owp)); - osalSysLockFromISR(); pwmDisableChannelI(pwmp, owp->config->sample_channel); osalThreadResumeI(&owp->thread, MSG_OK); @@ -661,7 +660,7 @@ bool onewireReset(onewireDriver *owp) { pwmcfg->channels[mch].callback = NULL; pwmcfg->channels[mch].mode = owp->config->pwmmode; pwmcfg->channels[sch].callback = pwm_reset_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW; + pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED; ow_bus_active(owp); @@ -680,7 +679,7 @@ bool onewireReset(onewireDriver *owp) { } /** - * @brief Read some bites from slave device. + * @brief Read some bytes from slave device. * * @param[in] owp pointer to the @p onewireDriver object * @param[out] rxbuf pointer to the buffer for read data @@ -714,7 +713,7 @@ void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) { pwmcfg->channels[mch].callback = NULL; pwmcfg->channels[mch].mode = owp->config->pwmmode; pwmcfg->channels[sch].callback = pwm_read_bit_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW; + pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED; ow_bus_active(owp); osalSysLock(); @@ -728,7 +727,7 @@ void onewireRead(onewireDriver *owp, uint8_t *rxbuf, size_t rxbytes) { } /** - * @brief Read some bites from slave device. + * @brief Write some bytes to slave device. * * @param[in] owp pointer to the @p onewireDriver object * @param[in] txbuf pointer to the buffer with data to be written @@ -848,7 +847,7 @@ size_t onewireSearchRom(onewireDriver *owp, uint8_t *result, pwmcfg->channels[mch].callback = NULL; pwmcfg->channels[mch].mode = owp->config->pwmmode; pwmcfg->channels[sch].callback = pwm_search_rom_cb; - pwmcfg->channels[sch].mode = PWM_OUTPUT_ACTIVE_LOW; + pwmcfg->channels[sch].mode = PWM_OUTPUT_DISABLED; ow_bus_active(owp); osalSysLock(); @@ -882,7 +881,7 @@ size_t onewireSearchRom(onewireDriver *owp, uint8_t *result, * Include test code (if enabled). */ #if ONEWIRE_SYNTH_SEARCH_TEST -#include "search_rom_synth.c" +#include "synth_searchrom.c" #endif #endif /* HAL_USE_ONEWIRE */ diff --git a/os/hal/src/hal_timcap.c b/os/hal/src/hal_timcap.c index a352490..309c147 100644 --- a/os/hal/src/hal_timcap.c +++ b/os/hal/src/hal_timcap.c @@ -19,7 +19,7 @@ */ /** - * @file timcap.c + * @file hal_timcap.c * @brief TIMCAP Driver code. * * @addtogroup TIMCAP diff --git a/os/hal/src/hal_usb_msd.c b/os/hal/src/hal_usb_msd.c new file mode 100644 index 0000000..068d698 --- /dev/null +++ b/os/hal/src/hal_usb_msd.c @@ -0,0 +1,408 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_usb_msd.c + * @brief USM mass storage device code. + * + * @addtogroup usb_msd + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_USB_MSD == TRUE) || defined(__DOXYGEN__) + +#include <string.h> + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define MSD_REQ_RESET 0xFF +#define MSD_GET_MAX_LUN 0xFE + +#define MSD_CBW_SIGNATURE 0x43425355 +#define MSD_CSW_SIGNATURE 0x53425355 + +#define MSD_THD_PRIO NORMALPRIO + +#define CBW_FLAGS_RESERVED_MASK 0b01111111 +#define CBW_LUN_RESERVED_MASK 0b11110000 +#define CBW_CMD_LEN_RESERVED_MASK 0b11000000 + +#define CSW_STATUS_PASSED 0x00 +#define CSW_STATUS_FAILED 0x01 +#define CSW_STATUS_PHASE_ERROR 0x02 + +#define MSD_SETUP_WORD(setup, index) (uint16_t)(((uint16_t)setup[index+1] << 8)\ + | (setup[index] & 0x00FF)) + +#define MSD_SETUP_VALUE(setup) MSD_SETUP_WORD(setup, 2) +#define MSD_SETUP_INDEX(setup) MSD_SETUP_WORD(setup, 4) +#define MSD_SETUP_LENGTH(setup) MSD_SETUP_WORD(setup, 6) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ +/** + * @brief USB mass storage driver identifier. + */ +USBMassStorageDriver USBMSD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Hardcoded default SCSI inquiry response structure. + */ +static const scsi_inquiry_response_t default_scsi_inquiry_response = { + 0x00, /* direct access block device */ + 0x80, /* removable */ + 0x04, /* SPC-2 */ + 0x02, /* response data format */ + 0x20, /* response has 0x20 + 4 bytes */ + 0x00, + 0x00, + 0x00, + "Chibios", + "Mass Storage", + {'v',CH_KERNEL_MAJOR+'0','.',CH_KERNEL_MINOR+'0'} +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Checks validity of CBW content. + * @details The device shall consider the CBW valid when: + * • The CBW was received after the device had sent a CSW or after a reset, + * • the CBW is 31 (1Fh) bytes in length, + * • and the dCBWSignature is equal to 43425355h. + * + * @param[in] cbw pointer to the @p msd_cbw_t object + * @param[in] recvd number of received bytes + * + * @return Operation status. + * @retval true CBW is meaningful. + * @retval false CBW is bad. + * + * @notapi + */ +static bool cbw_valid(const msd_cbw_t *cbw, msg_t recvd) { + if ((sizeof(msd_cbw_t) != recvd) || (cbw->signature != MSD_CBW_SIGNATURE)) { + return false; + } + else { + return true; + } +} + +/** + * @brief Checks meaningfulness of CBW content. + * @details The device shall consider the contents of a valid CBW meaningful when: + * • no reserved bits are set, + * • the bCBWLUN contains a valid LUN supported by the device, + * • and both bCBWCBLength and the content of the CBWCB are in + * accordance with bInterfaceSubClass. + * + * @param[in] cbw pointer to the @p msd_cbw_t object + * + * @return Operation status. + * @retval true CBW is meaningful. + * @retval false CBW is bad. + * + * @notapi + */ +static bool cbw_meaningful(const msd_cbw_t *cbw) { + if (((cbw->cmd_len & CBW_CMD_LEN_RESERVED_MASK) != 0) + || ((cbw->flags & CBW_FLAGS_RESERVED_MASK) != 0) + || (cbw->lun != 0)) { + return false; + } + else { + return true; + } +} + +/** + * @brief SCSI transport transmit function. + * + * @param[in] transport pointer to the @p SCSITransport object + * @param[in] data payload + * @param[in] len number of bytes to be transmitted + * + * @return Number of successfully transmitted bytes. + + * @notapi + */ +static uint32_t scsi_transport_transmit(const SCSITransport *transport, + const uint8_t *data, size_t len) { + + usb_scsi_transport_handler_t *trp = transport->handler; + msg_t status = usbTransmit(trp->usbp, trp->ep, data, len); + if (MSG_OK == status) + return len; + else + return 0; +} + +/** + * @brief SCSI transport receive function. + * + * @param[in] transport pointer to the @p SCSITransport object + * @param[in] data payload + * @param[in] len number bytes to be received + * + * @return Number of successfully received bytes. + + * @notapi + */ +static uint32_t scsi_transport_receive(const SCSITransport *transport, + uint8_t *data, size_t len) { + + usb_scsi_transport_handler_t *trp = transport->handler; + msg_t status = usbReceive(trp->usbp, trp->ep, data, len); + if (MSG_RESET != status) + return status; + else + return 0; +} + +/** + * @brief Fills and sends CSW message. + * + * @param[in] msdp pointer to the @p USBMassStorageDriver object + * @param[in] status status returned by SCSI layer + * @param[in] residue number of residue bytes in case of failed transaction + * + * @notapi + */ +static void send_csw(USBMassStorageDriver *msdp, uint8_t status, + uint32_t residue) { + + msdp->csw.signature = MSD_CSW_SIGNATURE; + msdp->csw.data_residue = residue; + msdp->csw.tag = msdp->cbw.tag; + msdp->csw.status = status; + + usbTransmit(msdp->usbp, USB_MSD_DATA_EP, (uint8_t *)&msdp->csw, + sizeof(msd_csw_t)); +} + +/** + * @brief Mass storage worker thread. + * + * @param[in] arg pointer to the @p USBMassStorageDriver object + * + * @notapi + */ +static THD_FUNCTION(usb_msd_worker, arg) { + USBMassStorageDriver *msdp = arg; + + while(! chThdShouldTerminateX()) { + const msg_t status = usbReceive(msdp->usbp, USB_MSD_DATA_EP, + (uint8_t *)&msdp->cbw, sizeof(msd_cbw_t)); + if (MSG_RESET == status) { + osalThreadSleepMilliseconds(50); + } + else if (cbw_valid(&msdp->cbw, status) && cbw_meaningful(&msdp->cbw)) { + if (SCSI_SUCCESS == scsiExecCmd(&msdp->scsi_target, msdp->cbw.cmd_data)) { + send_csw(msdp, CSW_STATUS_PASSED, 0); + } + else { + send_csw(msdp, CSW_STATUS_FAILED, scsiResidue(&msdp->scsi_target)); + } + } + else { + ; /* do NOT send CSW here. Incorrect CBW must be silently ignored */ + } + } + + chThdExit(MSG_OK); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Mass storage specific request hook for USB. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +bool msd_request_hook(USBDriver *usbp) { + + if (((usbp->setup[0] & USB_RTYPE_TYPE_MASK) == USB_RTYPE_TYPE_CLASS) && + ((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE)) { + /* check that the request is for interface 0.*/ + if (MSD_SETUP_INDEX(usbp->setup) != 0) + return false; + + /* act depending on bRequest = setup[1] */ + switch(usbp->setup[1]) { + case MSD_REQ_RESET: + /* check that it is a HOST2DEV request */ + if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) != USB_RTYPE_DIR_HOST2DEV) || + (MSD_SETUP_LENGTH(usbp->setup) != 0) || + (MSD_SETUP_VALUE(usbp->setup) != 0)) { + return false; + } + + /* + As required by the BOT specification, the Bulk-only mass storage reset request (classspecific + request) is implemented. This request is used to reset the mass storage device and + its associated interface. This class-specific request should prepare the device for the next + CBW from the host. + To generate the BOT Mass Storage Reset, the host must send a device request on the + default pipe of: + • bmRequestType: Class, interface, host to device + • bRequest field set to 255 (FFh) + • wValue field set to ‘0’ + • wIndex field set to the interface number + • wLength field set to ‘0’ + */ + chSysLockFromISR(); + + /* release and abandon current transmission */ + usbStallReceiveI(usbp, 1); + usbStallTransmitI(usbp, 1); + /* The device shall NAK the status stage of the device request until + * the Bulk-Only Mass Storage Reset is complete. + * NAK EP1 in and out */ + usbp->otg->ie[1].DIEPCTL = DIEPCTL_SNAK; + usbp->otg->oe[1].DOEPCTL = DOEPCTL_SNAK; + + chSysUnlockFromISR(); + + /* response to this request using EP0 */ + usbSetupTransfer(usbp, 0, 0, NULL); + return true; + + case MSD_GET_MAX_LUN: + /* check that it is a DEV2HOST request */ + if (((usbp->setup[0] & USB_RTYPE_DIR_MASK) != USB_RTYPE_DIR_DEV2HOST) || + (MSD_SETUP_LENGTH(usbp->setup) != 1) || + (MSD_SETUP_VALUE(usbp->setup) != 0)) { + return false; + } + + /* stall to indicate that we don't support LUN */ + osalSysLockFromISR(); + usbStallTransmitI(usbp, 0); + osalSysUnlockFromISR(); + return true; + + default: + return false; + break; + } + } + return false; +} + +/** + * @brief Initializes the standard part of a @p USBMassStorageDriver structure. + * + * @param[out] msdp pointer to the @p USBMassStorageDriver object + * + * @init + */ +void msdObjectInit(USBMassStorageDriver *msdp) { + + memset(msdp, 0x55, sizeof(USBMassStorageDriver)); + msdp->state = USB_MSD_STOP; + msdp->usbp = NULL; + msdp->worker = NULL; + + scsiObjectInit(&msdp->scsi_target); +} + +/** + * @brief Stops the USB mass storage driver. + * + * @param[in] msdp pointer to the @p USBMassStorageDriver object + * + * @api + */ +void msdStop(USBMassStorageDriver *msdp) { + + osalDbgCheck(msdp != NULL); + osalDbgAssert((msdp->state == USB_MSD_READY), "invalid state"); + + chThdTerminate(msdp->worker); + chThdWait(msdp->worker); + + scsiStop(&msdp->scsi_target); + + msdp->worker = NULL; + msdp->state = USB_MSD_STOP; + msdp->usbp = NULL; +} + +/** + * @brief Configures and activates the USB mass storage driver. + * + * @param[in] msdp pointer to the @p USBMassStorageDriver object + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] blkdev pointer to the @p BaseBlockDevice object + * @param[in] blkbuf pointer to the working area buffer, must be allocated + * by user, must be big enough to store 1 data block + * @param[in] inquiry pointer to the SCSI inquiry response structure, + * set it to @p NULL to use default hardcoded value. + * + * @api + */ +void msdStart(USBMassStorageDriver *msdp, USBDriver *usbp, + BaseBlockDevice *blkdev, uint8_t *blkbuf, + const scsi_inquiry_response_t *inquiry) { + + osalDbgCheck((msdp != NULL) && (usbp != NULL) + && (blkdev != NULL) && (blkbuf != NULL)); + osalDbgAssert((msdp->state == USB_MSD_STOP), "invalid state"); + + msdp->usbp = usbp; + + msdp->usb_scsi_transport_handler.usbp = msdp->usbp; + msdp->usb_scsi_transport_handler.ep = USB_MSD_DATA_EP; + msdp->scsi_transport.handler = &msdp->usb_scsi_transport_handler; + msdp->scsi_transport.transmit = scsi_transport_transmit; + msdp->scsi_transport.receive = scsi_transport_receive; + + if (NULL == inquiry) { + msdp->scsi_config.inquiry_response = &default_scsi_inquiry_response; + } + else { + msdp->scsi_config.inquiry_response = inquiry; + } + msdp->scsi_config.blkbuf = blkbuf; + msdp->scsi_config.blkdev = blkdev; + msdp->scsi_config.transport = &msdp->scsi_transport; + + scsiStart(&msdp->scsi_target, &msdp->scsi_config); + + msdp->state = USB_MSD_READY; + msdp->worker = chThdCreateStatic(msdp->waMSDWorker, sizeof(msdp->waMSDWorker), + MSD_THD_PRIO, usb_msd_worker, msdp); +} + +#endif /* HAL_USE_USB_MSD */ + +/** @} */ diff --git a/os/hal/src/usbh/hal_usbh_debug.c b/os/hal/src/usbh/hal_usbh_debug.c index 9f17189..51ca166 100644 --- a/os/hal/src/usbh/hal_usbh_debug.c +++ b/os/hal/src/usbh/hal_usbh_debug.c @@ -111,7 +111,7 @@ static char *ftoa(char *p, double num, unsigned long precision, bool dot) { static inline void _put(char c) { input_queue_t *iqp = &USBH_DEBUG_USBHD.iq; - if (chIQIsFullI(iqp)) + if (iqIsFullI(iqp)) return; iqp->q_counter++; @@ -407,8 +407,8 @@ void usbDbgReset(void) { const char *msg = "\r\n\r\n==== DEBUG OUTPUT RESET ====\r\n"; syssts_t sts = chSysGetStatusAndLockX(); - chIQResetI(&USBH_DEBUG_USBHD.iq); - chOQResetI(&USBH_DEBUG_SD.oqueue); + iqResetI(&USBH_DEBUG_USBHD.iq); + oqResetI(&USBH_DEBUG_SD.oqueue); while (*msg) { *USBH_DEBUG_SD.oqueue.q_wrptr++ = *msg++; USBH_DEBUG_SD.oqueue.q_counter--; @@ -478,7 +478,7 @@ static void usb_debug_thread(void *p) { chRegSetThreadName("USBH_DBG"); while (true) { - msg_t c = chIQGet(&host->iq); + msg_t c = iqGet(&host->iq); if (c < 0) goto reset; if (state == 0) { @@ -491,16 +491,16 @@ static void usb_debug_thread(void *p) { uint32_t hfnum; hfir = c; - c = chIQGet(&host->iq); if (c < 0) goto reset; + c = iqGet(&host->iq); if (c < 0) goto reset; hfir |= c << 8; - c = chIQGet(&host->iq); if (c < 0) goto reset; + c = iqGet(&host->iq); if (c < 0) goto reset; hfnum = c; - c = chIQGet(&host->iq); if (c < 0) goto reset; + c = iqGet(&host->iq); if (c < 0) goto reset; hfnum |= c << 8; - c = chIQGet(&host->iq); if (c < 0) goto reset; + c = iqGet(&host->iq); if (c < 0) goto reset; hfnum |= c << 16; - c = chIQGet(&host->iq); if (c < 0) goto reset; + c = iqGet(&host->iq); if (c < 0) goto reset; hfnum |= c << 24; uint32_t f = hfnum & 0xffff; @@ -508,7 +508,7 @@ static void usb_debug_thread(void *p) { chprintf((BaseSequentialStream *)&USBH_DEBUG_SD, "%05d.%03d ", f, p); while (true) { - c = chIQGet(&host->iq); if (c < 0) goto reset; + c = iqGet(&host->iq); if (c < 0) goto reset; if (!c) { sdPut(&USBH_DEBUG_SD, '\r'); sdPut(&USBH_DEBUG_SD, '\n'); @@ -528,7 +528,7 @@ reset: void usbDbgInit(USBHDriver *host) { if (host != &USBH_DEBUG_USBHD) return; - chIQObjectInit(&USBH_DEBUG_USBHD.iq, USBH_DEBUG_USBHD.dbg_buff, sizeof(USBH_DEBUG_USBHD.dbg_buff), 0, 0); + iqObjectInit(&USBH_DEBUG_USBHD.iq, USBH_DEBUG_USBHD.dbg_buff, sizeof(USBH_DEBUG_USBHD.dbg_buff), 0, 0); chThdCreateStatic(USBH_DEBUG_USBHD.waDebug, sizeof(USBH_DEBUG_USBHD.waDebug), NORMALPRIO, usb_debug_thread, &USBH_DEBUG_USBHD); } #endif diff --git a/os/hal/src/usbh/hal_usbh_hub.c b/os/hal/src/usbh/hal_usbh_hub.c index 7fdcef1..56257b2 100644 --- a/os/hal/src/usbh/hal_usbh_hub.c +++ b/os/hal/src/usbh/hal_usbh_hub.c @@ -15,6 +15,7 @@ limitations under the License. */ +#include <string.h> #include "hal.h" #include "hal_usbh.h" #include "usbh/internal.h" diff --git a/os/various/bitmap.h b/os/various/bitmap.h index d7831aa..115b54c 100644 --- a/os/various/bitmap.h +++ b/os/various/bitmap.h @@ -22,8 +22,8 @@ * @{ */ -#ifndef _BITMAP_H_ -#define _BITMAP_H_ +#ifndef BITMAP_H_ +#define BITMAP_H_ /*===========================================================================*/ /* Module constants. */ @@ -72,6 +72,6 @@ extern "C" { } #endif -#endif /* _BITMAP_H_ */ +#endif /* BITMAP_H_ */ /** @} */ diff --git a/os/various/dbgtrace.h b/os/various/dbgtrace.h new file mode 100644 index 0000000..b1fc297 --- /dev/null +++ b/os/various/dbgtrace.h @@ -0,0 +1,41 @@ +#ifndef DBGTRACE_H_ +#define DBGTRACE_H_ + +#include "chprintf.h" + +#if !defined(DEBUG_TRACE_PRINT) +#define DEBUG_TRACE_PRINT FALSE +#endif + +#if !defined(DEBUG_TRACE_WARNING) +#define DEBUG_TRACE_WARNING FALSE +#endif + +#if !defined(DEBUG_TRACE_ERROR) +#define DEBUG_TRACE_ERROR FALSE +#endif + +/* user must provide correctly initialized pointer to print channel */ +#if DEBUG_TRACE_PRINT || DEBUG_TRACE_WARNING || DEBUG_TRACE_ERROR +extern BaseSequentialStream *GlobalDebugChannel; +#endif + +#if DEBUG_TRACE_PRINT +#define dbgprintf(fmt, ...) chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__) +#else +#define dbgprintf(fmt, ...) do {} while(0) +#endif + +#if DEBUG_TRACE_WARNING +#define warnprintf(fmt, ...) chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__) +#else +#define warnprintf(fmt, ...) do {} while(0) +#endif + +#if DEBUG_TRACE_ERROR +#define errprintf(fmt, ...) chprintf(GlobalDebugChannel, fmt, ##__VA_ARGS__) +#else +#define errprintf(fmt, ...) do {} while(0) +#endif + +#endif /* DBGTRACE_H_ */ diff --git a/os/various/lib_scsi.c b/os/various/lib_scsi.c new file mode 100644 index 0000000..55aeb7e --- /dev/null +++ b/os/various/lib_scsi.c @@ -0,0 +1,507 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file lib_scsi.c + * @brief SCSI target driver source code. + * + * @addtogroup SCSI + * @{ + */ + +#include <string.h> + +#include "hal.h" + +#include "lib_scsi.h" + +#define DEBUG_TRACE_PRINT FALSE +#define DEBUG_TRACE_WARNING FALSE +#define DEBUG_TRACE_ERROR FALSE +#include "dbgtrace.h" + +#define ARCH_LITTLE_ENDIAN +#include "bswap.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +typedef struct { + uint32_t first_lba; + uint16_t blk_cnt; +} data_request_t; + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Combines data request from byte array. + * + * @notapi + */ +static data_request_t decode_data_request(const uint8_t *cmd) { + + data_request_t req; + uint32_t lba; + uint16_t blk; + + memcpy(&lba, &cmd[2], sizeof(lba)); + memcpy(&blk, &cmd[7], sizeof(blk)); + + req.first_lba = be32_to_cpu(lba); + req.blk_cnt = be16_to_cpu(blk); + + return req; +} + +/** + * @brief Fills sense structure. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] key SCSI sense key + * @param[in] code SCSI sense code + * @param[in] qual SCSI sense qualifier + * + * @notapi + */ +static void set_sense(SCSITarget *scsip, uint8_t key, + uint8_t code, uint8_t qual) { + + scsi_sense_response_t *sense = &scsip->sense; + memset(sense, 0 , sizeof(scsi_sense_response_t)); + + sense->byte[0] = 0x70; + sense->byte[2] = key; + sense->byte[7] = 8; + sense->byte[12] = code; + sense->byte[13] = qual; +} + +/** + * @brief Sets all values in sense data to 'success' condition. + * + * @param[in] scsip pointer to @p SCSITarget structure + * + * @notapi + */ +static void set_sense_ok(SCSITarget *scsip) { + set_sense(scsip, SCSI_SENSE_KEY_GOOD, + SCSI_ASENSE_NO_ADDITIONAL_INFORMATION, + SCSI_ASENSEQ_NO_QUALIFIER); +} + +/** + * @brief Transmits data via transport channel. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] data pointer to data buffer + * @param[in] len number of bytes to be transmitted + * + * @return The operation status. + * + * @notapi + */ +static bool transmit_data(SCSITarget *scsip, const uint8_t *data, uint32_t len) { + + const SCSITransport *trp = scsip->config->transport; + const uint32_t residue = len - trp->transmit(trp, data, len); + + if (residue > 0) { + scsip->residue = residue; + return SCSI_FAILED; + } + else { + return SCSI_SUCCESS; + } +} + +/** + * @brief Stub for unhandled SCSI commands. + * @details Sets error flags in sense data structure and returns error error. + */ +static bool cmd_unhandled(SCSITarget *scsip, const uint8_t *cmd) { + (void)cmd; + + set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, + SCSI_ASENSE_INVALID_COMMAND, + SCSI_ASENSEQ_NO_QUALIFIER); + return SCSI_FAILED; +} + +/** + * @brief Stub for unrealized but required SCSI commands. + * @details Sets sense data in 'all OK' condition and returns success status. + */ +static bool cmd_ignored(SCSITarget *scsip, const uint8_t *cmd) { + (void)scsip; + (void)cmd; + + set_sense_ok(scsip); + return SCSI_SUCCESS; +} + +/** + * @brief SCSI inquiry command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool inquiry(SCSITarget *scsip, const uint8_t *cmd) { + + if ((cmd[1] & 0b11) || cmd[2] != 0) { + set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, + SCSI_ASENSE_INVALID_FIELD_IN_CDB, + SCSI_ASENSEQ_NO_QUALIFIER); + return SCSI_FAILED; + } + else { + return transmit_data(scsip, (const uint8_t *)scsip->config->inquiry_response, + sizeof(scsi_inquiry_response_t)); + } +} + +/** + * @brief SCSI request sense command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool request_sense(SCSITarget *scsip, const uint8_t *cmd) { + + uint32_t tmp; + memcpy(&tmp, &cmd[1], 3); + + if ((tmp != 0) || (cmd[4] != sizeof(scsi_sense_response_t))) { + set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, + SCSI_ASENSE_INVALID_FIELD_IN_CDB, + SCSI_ASENSEQ_NO_QUALIFIER); + return SCSI_FAILED; + } + else { + return transmit_data(scsip, (uint8_t *)&scsip->sense, + sizeof(scsi_sense_response_t)); + } +} + +/** + * @brief SCSI mode sense (6) command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool mode_sense6(SCSITarget *scsip, const uint8_t *cmd) { + (void)cmd; + + scsip->mode_sense.byte[0] = sizeof(scsi_mode_sense6_response_t) - 1; + scsip->mode_sense.byte[1] = 0; + if (blkIsWriteProtected(scsip->config->blkdev)) { + scsip->mode_sense.byte[2] = 0x01 << 7; + } + else { + scsip->mode_sense.byte[2] = 0; + } + scsip->mode_sense.byte[3] = 0; + + return transmit_data(scsip, (uint8_t *)&scsip->mode_sense, + sizeof(scsi_mode_sense6_response_t)); +} + +/** + * @brief SCSI read format capacities command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool read_format_capacities(SCSITarget *scsip, const uint8_t *cmd) { + + /* An Allocation Length of zero indicates that no data shall be transferred. + This condition shall not be considered as an error. The Logical Unit + shall terminate the data transfer when Allocation Length bytes have + been transferred or when all available data have been transferred to + the Initiator, whatever is less. */ + + uint16_t len = cmd[7] << 8 | cmd[8]; + + if (0 == len) { + return SCSI_SUCCESS; + } + else { + scsi_read_format_capacities_response_t ret; + BlockDeviceInfo bdi; + blkGetInfo(scsip->config->blkdev, &bdi); + + uint32_t tmp = cpu_to_be32(bdi.blk_num); + memcpy(ret.blocknum, &tmp, 4); + + uint8_t formatted_media = 0b10; + uint16_t blocklen = bdi.blk_size; + ret.blocklen[0] = formatted_media; + ret.blocklen[1] = 0; + ret.blocklen[2] = blocklen >> 8; + ret.blocklen[3] = blocklen & 0xFF; + + ret.header[3] = 1 * 8; + + return transmit_data(scsip, (uint8_t *)&ret, + sizeof(scsi_read_format_capacities_response_t)); + } +} + +/** + * @brief SCSI read capacity (10) command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool read_capacity10(SCSITarget *scsip, const uint8_t *cmd) { + + (void)cmd; + + BlockDeviceInfo bdi; + blkGetInfo(scsip->config->blkdev, &bdi); + scsi_read_capacity10_response_t ret; + ret.block_size = cpu_to_be32(bdi.blk_size); + ret.last_block_addr = cpu_to_be32(bdi.blk_num - 1); + + return transmit_data(scsip, (uint8_t *)&ret, + sizeof(scsi_read_capacity10_response_t)); +} + +/** + * @brief Checks data request for media overflow. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * @retval true When media overflow detected. + * @retval false Otherwise. + * + * @notapi + */ +static bool data_overflow(SCSITarget *scsip, const data_request_t *req) { + + BlockDeviceInfo bdi; + blkGetInfo(scsip->config->blkdev, &bdi); + + if (req->first_lba + req->blk_cnt > bdi.blk_num) { + set_sense(scsip, SCSI_SENSE_KEY_ILLEGAL_REQUEST, + SCSI_ASENSE_LBA_OUT_OF_RANGE, + SCSI_ASENSEQ_NO_QUALIFIER); + return true; + } + else { + return false; + } +} + +/** + * @brief SCSI read/write (10) command handler. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @notapi + */ +static bool data_read_write10(SCSITarget *scsip, const uint8_t *cmd) { + + data_request_t req = decode_data_request(cmd); + + if (data_overflow(scsip, &req)) { + return SCSI_FAILED; + } + else { + const SCSITransport *tr = scsip->config->transport; + BaseBlockDevice *blkdev = scsip->config->blkdev; + BlockDeviceInfo bdi; + blkGetInfo(blkdev, &bdi); + size_t bs = bdi.blk_size; + uint8_t *buf = scsip->config->blkbuf; + + for (size_t i=0; i<req.blk_cnt; i++) { + if (cmd[0] == SCSI_CMD_READ_10) { + // TODO: block error handling + blkRead(blkdev, req.first_lba + i, buf, 1); + tr->transmit(tr, buf, bs); + } + else { + // TODO: block error handling + tr->receive(tr, buf, bs); + blkWrite(blkdev, req.first_lba + i, buf, 1); + } + } + } + return SCSI_SUCCESS; +} +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Executes SCSI command encoded in byte array. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] cmd pointer to SCSI command data + * + * @return The operation status. + * + * @api + */ +bool scsiExecCmd(SCSITarget *scsip, const uint8_t *cmd) { + + /* status will be overwritten later in case of error */ + set_sense_ok(scsip); + + switch (cmd[0]) { + case SCSI_CMD_INQUIRY: + dbgprintf("SCSI_CMD_INQUIRY\r\n"); + return inquiry(scsip, cmd); + + case SCSI_CMD_REQUEST_SENSE: + dbgprintf("SCSI_CMD_REQUEST_SENSE\r\n"); + return request_sense(scsip, cmd); + + case SCSI_CMD_READ_CAPACITY_10: + dbgprintf("SCSI_CMD_READ_CAPACITY_10\r\n"); + return read_capacity10(scsip, cmd); + + case SCSI_CMD_READ_10: + dbgprintf("SCSI_CMD_READ_10\r\n"); + return data_read_write10(scsip, cmd); + + case SCSI_CMD_WRITE_10: + dbgprintf("SCSI_CMD_WRITE_10\r\n"); + return data_read_write10(scsip, cmd); + + case SCSI_CMD_TEST_UNIT_READY: + dbgprintf("SCSI_CMD_TEST_UNIT_READY\r\n"); + return cmd_ignored(scsip, cmd); + + case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL: + dbgprintf("SCSI_CMD_ALLOW_MEDIUM_REMOVAL\r\n"); + return cmd_ignored(scsip, cmd); + + case SCSI_CMD_MODE_SENSE_6: + dbgprintf("SCSI_CMD_MODE_SENSE_6\r\n"); + return mode_sense6(scsip, cmd); + + case SCSI_CMD_READ_FORMAT_CAPACITIES: + dbgprintf("SCSI_CMD_READ_FORMAT_CAPACITIES\r\n"); + return read_format_capacities(scsip, cmd); + + case SCSI_CMD_VERIFY_10: + dbgprintf("SCSI_CMD_VERIFY_10\r\n"); + return cmd_ignored(scsip, cmd); + + default: + warnprintf("SCSI unhandled command: %X\r\n", cmd[0]); + return cmd_unhandled(scsip, cmd); + } +} + +/** + * @brief Driver structure initialization. + * + * @param[in] scsip pointer to @p SCSITarget structure + * + * @api + */ +void scsiObjectInit(SCSITarget *scsip) { + + scsip->config = NULL; + scsip->residue = 0; + memset(&scsip->sense, 0 , sizeof(scsi_sense_response_t)); + scsip->state = SCSI_TRGT_STOP; +} + +/** + * @brief Starts SCSITarget driver. + * + * @param[in] scsip pointer to @p SCSITarget structure + * @param[in] config pointer to @p SCSITargetConfig structure + * + * @api + */ +void scsiStart(SCSITarget *scsip, const SCSITargetConfig *config) { + + scsip->config = config; + scsip->state = SCSI_TRGT_READY; +} + +/** + * @brief Stops SCSITarget driver. + * + * @param[in] scsip pointer to @p SCSITarget structure + * + * @api + */ +void scsiStop(SCSITarget *scsip) { + + scsip->config = NULL; + scsip->state = SCSI_TRGT_STOP; +} + +/** + * @brief Retrieves residue bytes. + * + * @param[in] scsip pointer to @p SCSITarget structure + * + * @return Residue bytes. + * + * @api + */ +uint32_t scsiResidue(const SCSITarget *scsip) { + + return scsip->residue; +} + +/** @} */ diff --git a/os/various/lib_scsi.h b/os/various/lib_scsi.h new file mode 100644 index 0000000..97badb0 --- /dev/null +++ b/os/various/lib_scsi.h @@ -0,0 +1,278 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file wdg_lld.h + * @brief WDG Driver subsystem low level driver header template. + * + * @addtogroup WDG + * @{ + */ + +#ifndef LIB_SCSI_H_ +#define LIB_SCSI_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SCSI_CMD_TEST_UNIT_READY 0x00 +#define SCSI_CMD_REQUEST_SENSE 0x03 +#define SCSI_CMD_INQUIRY 0x12 +#define SCSI_CMD_MODE_SENSE_6 0x1A +#define SCSI_CMD_START_STOP_UNIT 0x1B +#define SCSI_CMD_SEND_DIAGNOSTIC 0x1D +#define SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E +#define SCSI_CMD_READ_CAPACITY_10 0x25 +#define SCSI_CMD_READ_FORMAT_CAPACITIES 0x23 +#define SCSI_CMD_READ_10 0x28 +#define SCSI_CMD_WRITE_10 0x2A +#define SCSI_CMD_VERIFY_10 0x2F + +#define SCSI_SENSE_KEY_GOOD 0x00 +#define SCSI_SENSE_KEY_RECOVERED_ERROR 0x01 +#define SCSI_SENSE_KEY_NOT_READY 0x02 +#define SCSI_SENSE_KEY_MEDIUM_ERROR 0x03 +#define SCSI_SENSE_KEY_HARDWARE_ERROR 0x04 +#define SCSI_SENSE_KEY_ILLEGAL_REQUEST 0x05 +#define SCSI_SENSE_KEY_UNIT_ATTENTION 0x06 +#define SCSI_SENSE_KEY_DATA_PROTECT 0x07 +#define SCSI_SENSE_KEY_BLANK_CHECK 0x08 +#define SCSI_SENSE_KEY_VENDOR_SPECIFIC 0x09 +#define SCSI_SENSE_KEY_COPY_ABORTED 0x0A +#define SCSI_SENSE_KEY_ABORTED_COMMAND 0x0B +#define SCSI_SENSE_KEY_VOLUME_OVERFLOW 0x0D +#define SCSI_SENSE_KEY_MISCOMPARE 0x0E + +#define SCSI_ASENSE_NO_ADDITIONAL_INFORMATION 0x00 +#define SCSI_ASENSE_LOGICAL_UNIT_NOT_READY 0x04 +#define SCSI_ASENSE_INVALID_FIELD_IN_CDB 0x24 +#define SCSI_ASENSE_NOT_READY_TO_READY_CHANGE 0x28 +#define SCSI_ASENSE_WRITE_PROTECTED 0x27 +#define SCSI_ASENSE_FORMAT_ERROR 0x31 +#define SCSI_ASENSE_INVALID_COMMAND 0x20 +#define SCSI_ASENSE_LBA_OUT_OF_RANGE 0x21 +#define SCSI_ASENSE_MEDIUM_NOT_PRESENT 0x3A + +#define SCSI_ASENSEQ_NO_QUALIFIER 0x00 +#define SCSI_ASENSEQ_FORMAT_COMMAND_FAILED 0x01 +#define SCSI_ASENSEQ_INIT_COMMAND_REQUIRED 0x02 +#define SCSI_ASENSEQ_OPERATION_IN_PROGRESS 0x07 + +#define SCSI_SUCCESS HAL_SUCCESS +#define SCSI_FAILED HAL_FAILED + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SCSI target. + */ +typedef struct SCSITarget SCSITarget; + +/** + * @brief Type of a structure representing an SCSI transport. + */ +typedef struct SCSITransport SCSITransport; + +/** + * @brief State of SCSI target. + */ +typedef enum { + SCSI_TRGT_UNINIT = 0, + SCSI_TRGT_STOP, + SCSI_TRGT_READY, +} scsitrgtstate_t; + +/** + * @brief Represents SCSI sense data structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR { + uint8_t byte[18]; +} scsi_sense_response_t; + +/** + * @brief Represents SCSI inquiry response structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR { + uint8_t peripheral; + uint8_t removable; + uint8_t version; + uint8_t response_data_format; + uint8_t additional_length; + uint8_t sccstp; + uint8_t bqueetc; + uint8_t cmdque; + uint8_t vendorID[8]; + uint8_t productID[16]; + uint8_t productRev[4]; +} scsi_inquiry_response_t; + +/** + * @brief Represents SCSI mode sense (6) request structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR { + uint8_t byte[6]; +} scsi_mode_sense6_request_t; + +/** + * @brief Represents SCSI mode sense (6) response structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR{ + uint8_t byte[4]; +} scsi_mode_sense6_response_t; + +/** + * @brief Represents SCSI read capacity (10) response structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR { + uint32_t last_block_addr; + uint32_t block_size; +} scsi_read_capacity10_response_t; + +/** + * @brief Represents SCSI read format capacity response structure. + * @details See SCSI specification. + */ +typedef struct PACKED_VAR { + uint8_t header[4]; + uint8_t blocknum[4]; + uint8_t blocklen[4]; +} scsi_read_format_capacities_response_t; + +/** + * @brief Type of a SCSI transport transmit call. + * + * @param[in] usbp pointer to the @p SCSITransport object + * @param[in] data pointer to payload buffer + * @param[in] len payload length + */ +typedef uint32_t (*scsi_transport_transmit_t)(const SCSITransport *transport, + const uint8_t *data, size_t len); + +/** + * @brief Type of a SCSI transport transmit call. + * + * @param[in] usbp pointer to the @p SCSITransport object + * @param[out] data pointer to receive buffer + * @param[in] len number of bytes to be received + */ +typedef uint32_t (*scsi_transport_receive_t)(const SCSITransport *transport, + uint8_t *data, size_t len); + +/** + * @brief SCSI transport structure. + */ +struct SCSITransport { + /** + * @brief Transmit call provided by lower level driver. + */ + scsi_transport_transmit_t transmit; + /** + * @brief Receive call provided by lower level driver. + */ + scsi_transport_receive_t receive; + /** + * @brief Transport handler provided by lower level driver. + */ + void *handler; +}; + +/** + * @brief SCSI target config structure. + */ +typedef struct { + /** + * @brief Pointer to @p SCSITransport object. + */ + const SCSITransport *transport; + /** + * @brief Pointer to @p BaseBlockDevice object. + */ + BaseBlockDevice *blkdev; + /** + * @brief Pointer to data buffer for single block. + */ + uint8_t *blkbuf; + /** + * @brief Pointer to SCSI inquiry response object. + */ + const scsi_inquiry_response_t *inquiry_response; +} SCSITargetConfig; + +/** + * + */ +struct SCSITarget { + /** + * @brief Pointer to @p SCSITargetConfig object. + */ + const SCSITargetConfig *config; + /** + * @brief Target state. + */ + scsitrgtstate_t state; + /** + * @brief SCSI sense response structure. + */ + scsi_sense_response_t sense; + /** + * @brief SCSI mode sense (6) response structure. + */ + scsi_mode_sense6_response_t mode_sense; + /** + * @brief Residue bytes. + */ + uint32_t residue; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void scsiObjectInit(SCSITarget *scsip); + void scsiStart(SCSITarget *scsip, const SCSITargetConfig *config); + void scsiStop(SCSITarget *scsip); + bool scsiExecCmd(SCSITarget *scsip, const uint8_t *cmd); + uint32_t scsiResidue(const SCSITarget *scsip); +#ifdef __cplusplus +} +#endif + +#endif /* LIB_SCSI_H_ */ + +/** @} */ diff --git a/os/various/ramdisk.c b/os/various/ramdisk.c new file mode 100644 index 0000000..08abdca --- /dev/null +++ b/os/various/ramdisk.c @@ -0,0 +1,219 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ramdisk.c + * @brief Virtual block devise driver source. + * + * @addtogroup ramdisk + * @{ + */ + +#include "hal.h" + +#include "ramdisk.h" + +#include <string.h> + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/* + * Interface implementation. + */ +static bool overflow(const RamDisk *rd, uint32_t startblk, uint32_t n) { + return (startblk + n) > rd->blk_num; +} + +static bool is_inserted(void *instance) { + (void)instance; + return true; +} + +static bool is_protected(void *instance) { + RamDisk *rd = instance; + if (BLK_READY == rd->state) { + return rd->readonly; + } + else { + return true; + } +} + +static bool connect(void *instance) { + RamDisk *rd = instance; + if (BLK_STOP == rd->state) { + rd->state = BLK_READY; + } + return HAL_SUCCESS; +} + +static bool disconnect(void *instance) { + RamDisk *rd = instance; + if (BLK_STOP != rd->state) { + rd->state = BLK_STOP; + } + return HAL_SUCCESS; +} + +static bool read(void *instance, uint32_t startblk, + uint8_t *buffer, uint32_t n) { + + RamDisk *rd = instance; + + if (overflow(rd, startblk, n)) { + return HAL_FAILED; + } + else { + const uint32_t bs = rd->blk_size; + memcpy(buffer, &rd->storage[startblk * bs], n * bs); + return HAL_SUCCESS; + } +} + +static bool write(void *instance, uint32_t startblk, + const uint8_t *buffer, uint32_t n) { + + RamDisk *rd = instance; + if (overflow(rd, startblk, n)) { + return HAL_FAILED; + } + else { + const uint32_t bs = rd->blk_size; + memcpy(&rd->storage[startblk * bs], buffer, n * bs); + return HAL_SUCCESS; + } +} + +static bool sync(void *instance) { + + RamDisk *rd = instance; + if (BLK_READY != rd->state) { + return HAL_FAILED; + } + else { + return HAL_SUCCESS; + } +} + +static bool get_info(void *instance, BlockDeviceInfo *bdip) { + + RamDisk *rd = instance; + if (BLK_READY != rd->state) { + return HAL_FAILED; + } + else { + bdip->blk_num = rd->blk_num; + bdip->blk_size = rd->blk_size; + return HAL_SUCCESS; + } +} + +/** + * + */ +static const struct BaseBlockDeviceVMT vmt = { + is_inserted, + is_protected, + connect, + disconnect, + read, + write, + sync, + get_info +}; + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief RAM disk object initialization. + * + * @param[in] rdp pointer to @p RamDisk object + * + * @init + */ +void ramdiskObjectInit(RamDisk *rdp) { + + rdp->vmt = &vmt; + rdp->state = SD_STOP; +} + +/** + * @brief Starts RAM disk. + * + * @param[in] rdp pointer to @p RamDisk object + * @param[in] storage pointer to array representing disk storage + * @param[in] blksize size of blocks in bytes + * @param[in] blknum total number of blocks in device + * @param[in] readonly read only flag + * + * @api + */ +void ramdiskStart(RamDisk *rdp, uint8_t *storage, uint32_t blksize, + uint32_t blknum, bool readonly) { + + osalDbgCheck(rdp != NULL); + + osalSysLock(); + osalDbgAssert((rdp->state == BLK_STOP) || (rdp->state == BLK_READY), + "invalid state"); + rdp->blk_num = blknum; + rdp->blk_size = blksize; + rdp->readonly = readonly; + rdp->storage = storage; + rdp->state = BLK_READY; + osalSysUnlock(); +} + +/** + * @brief Stops RAM disk. + * + * @param[in] rdp pointer to @p RamDisk object + * + * @api + */ +void ramdiskStop(RamDisk *rdp) { + + osalDbgCheck(rdp != NULL); + + osalSysLock(); + osalDbgAssert((rdp->state == BLK_STOP) || (rdp->state == BLK_READY), + "invalid state"); + rdp->storage = NULL; + rdp->state = BLK_STOP; + osalSysUnlock(); +} + +/** @} */ diff --git a/os/various/ramdisk.h b/os/various/ramdisk.h new file mode 100644 index 0000000..0860662 --- /dev/null +++ b/os/various/ramdisk.h @@ -0,0 +1,86 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ramdisk.h + * @brief Virtual block devise driver header. + * + * @addtogroup ramdisk + * @{ + */ + +#ifndef RAMDISK_H_ +#define RAMDISK_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +typedef struct RamDisk RamDisk; + +/** + * + */ +#define _ramdisk_device_data \ + _base_block_device_data \ + uint8_t *storage; \ + uint32_t blk_size; \ + uint32_t blk_num; \ + bool readonly; + +/** + * + */ +struct RamDisk { + /** @brief Virtual Methods Table.*/ + const struct BaseBlockDeviceVMT *vmt; + _ramdisk_device_data +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ramdiskObjectInit(RamDisk *rdp); + void ramdiskStart(RamDisk *rdp, uint8_t *storage, uint32_t blksize, + uint32_t blknum, bool readonly); + void ramdiskStop(RamDisk *rdp); +#ifdef __cplusplus +} +#endif + +#endif /* RAMDISK_H_ */ + +/** @} */ diff --git a/os/various/tribuf.h b/os/various/tribuf.h index 4ba3f25..8d8f9f4 100644 --- a/os/various/tribuf.h +++ b/os/various/tribuf.h @@ -22,8 +22,8 @@ * @{
*/
-#ifndef _TRIBUF_H_
-#define _TRIBUF_H_
+#ifndef TRIBUF_H_
+#define TRIBUF_H_
/*===========================================================================*/
/* Driver constants. */
@@ -221,5 +221,5 @@ extern "C" { }
#endif
-#endif /* _TRIBUF_H_ */
+#endif /* TRIBUF_H_ */
/** @} */
diff --git a/testhal/KINETIS/FRDM-K20D50M/USB_SERIAL/usbcfg.c b/testhal/KINETIS/FRDM-K20D50M/USB_SERIAL/usbcfg.c index 24a732f..96bfdba 100644 --- a/testhal/KINETIS/FRDM-K20D50M/USB_SERIAL/usbcfg.c +++ b/testhal/KINETIS/FRDM-K20D50M/USB_SERIAL/usbcfg.c @@ -284,7 +284,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { chSysLockFromISR();
/* Disconnection event on suspend.*/
- sduDisconnectI(&SDU1);
+ sduSuspendHookI(&SDU1);
chSysUnlockFromISR();
return;
diff --git a/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/usbcfg.c b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/usbcfg.c index 3093640..fa5b4f4 100644 --- a/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/usbcfg.c +++ b/testhal/KINETIS/FRDM-KL25Z/USB_SERIAL/usbcfg.c @@ -284,7 +284,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { chSysLockFromISR();
/* Disconnection event on suspend.*/
- sduDisconnectI(&SDU1);
+ sduSuspendHookI(&SDU1);
chSysUnlockFromISR();
return;
diff --git a/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/usbcfg.c b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/usbcfg.c index 3093640..fa5b4f4 100644 --- a/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/usbcfg.c +++ b/testhal/KINETIS/FRDM-KL26Z/USB_SERIAL/usbcfg.c @@ -284,7 +284,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { chSysLockFromISR();
/* Disconnection event on suspend.*/
- sduDisconnectI(&SDU1);
+ sduSuspendHookI(&SDU1);
chSysUnlockFromISR();
return;
diff --git a/testhal/KINETIS/MCHCK/USB_SERIAL/usbcfg.c b/testhal/KINETIS/MCHCK/USB_SERIAL/usbcfg.c index 3093640..fa5b4f4 100644 --- a/testhal/KINETIS/MCHCK/USB_SERIAL/usbcfg.c +++ b/testhal/KINETIS/MCHCK/USB_SERIAL/usbcfg.c @@ -284,7 +284,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { chSysLockFromISR();
/* Disconnection event on suspend.*/
- sduDisconnectI(&SDU1);
+ sduSuspendHookI(&SDU1);
chSysUnlockFromISR();
return;
diff --git a/testhal/KINETIS/TEENSY3_x/USB_SERIAL/usbcfg.c b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/usbcfg.c index 3093640..fa5b4f4 100644 --- a/testhal/KINETIS/TEENSY3_x/USB_SERIAL/usbcfg.c +++ b/testhal/KINETIS/TEENSY3_x/USB_SERIAL/usbcfg.c @@ -284,7 +284,7 @@ static void usb_event(USBDriver *usbp, usbevent_t event) { chSysLockFromISR();
/* Disconnection event on suspend.*/
- sduDisconnectI(&SDU1);
+ sduSuspendHookI(&SDU1);
chSysUnlockFromISR();
return;
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/Makefile b/testhal/MSP430X/EXP430FR5969/ADC/Makefile new file mode 100644 index 0000000..cf81f18 --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/Makefile @@ -0,0 +1,206 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Optimization level, can be [0, 1, 2, 3, s].
+# 0 = turn off optimization. s = optimize for size.
+# (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
+OPTIMIZE = 0
+
+# Debugging format.
+DEBUG =
+#DEBUG = stabs
+
+# Memory/data model
+MODEL = small
+
+# Object files directory
+# To put object files in current directory, use a dot (.), do NOT make
+# this an empty or blank macro!
+OBJDIR = .
+
+# Compiler flag to set the C Standard level.
+# c89 = "ANSI" C
+# gnu89 = c89 plus GCC extensions
+# c99 = ISO C99 standard (not yet fully implemented)
+# gnu99 = c99 plus GCC extensions
+CSTANDARD = -std=gnu11
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O$(OPTIMIZE) -g$(DEBUG)
+ USE_OPT += -funsigned-char -fshort-enums
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# Enable the selected hardware multiplier
+ifeq ($(USE_HWMULT),)
+ USE_HWMULT = f5series
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = yes
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the idle thread stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_IDLE_STACKSIZE),)
+ USE_IDLE_STACKSIZE = 0xC00
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = nil
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = ../../../..
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC/mk/startup_msp430fr5xxx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/EXP430FR5969/board.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/MSP430X/platform.mk
+include $(CHIBIOS)/os/hal/osal/nil/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/nil/nil.mk
+include $(CHIBIOS_CONTRIB)/os/common/ports/MSP430X/compilers/GCC/mk/port.mk
+# Other files (optional).
+
+# Define linker script file here
+LDSCRIPT = $(STARTUPLD)/msp430fr5969.ld
+
+# C sources
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ msp_vectors.c \
+ main.c
+
+# C++ sources
+CPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(CHIBIOS)/os/license \
+ $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = msp430fr5969
+
+TRGT = msp430-elf-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# MSP430-specific options here
+MOPT = -m$(MODEL)
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/chconf.h b/testhal/MSP430X/EXP430FR5969/ADC/chconf.h new file mode 100644 index 0000000..3b7a8e1 --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/chconf.h @@ -0,0 +1,274 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file nilconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef CHCONF_H
+#define CHCONF_H
+
+#define _CHIBIOS_NIL_CONF_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Number of user threads in the application.
+ * @note This number is not inclusive of the idle thread which is
+ * Implicitly handled.
+ */
+#define CH_CFG_NUM_THREADS 1
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name System timer settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 16
+
+/**
+ * @brief System tick frequency.
+ * @note This value together with the @p CH_CFG_ST_RESOLUTION
+ * option defines the maximum amount of time allowed for
+ * timeouts.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note Feature not currently implemented.
+ * @note The default is @p FALSE.
+ */
+#define CH_CFG_USE_MUTEXES FALSE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note Feature not currently implemented.
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief System assertions.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Stack check.
+ *
+ *@note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System initialization hook.
+ */
+#if !defined(CH_CFG_SYSTEM_INIT_HOOK) || defined(__DOXYGEN__)
+#define CH_CFG_SYSTEM_INIT_HOOK() { \
+}
+#endif
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXT_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ */
+#define CH_CFG_THREAD_EXT_INIT_HOOK(tr) { \
+ /* Add custom threads initialization code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief System halt hook.
+ */
+#if !defined(CH_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in nilcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/halconf.h b/testhal/MSP430X/EXP430FR5969/ADC/halconf.h new file mode 100644 index 0000000..2982a63 --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/halconf.h @@ -0,0 +1,388 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef HALCONF_H
+#define HALCONF_H
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the DMA subsystem.
+ */
+#if !defined(HAL_USE_DMA) || defined(__DOXYGEN__)
+#define HAL_USE_DMA TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC TRUE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE FALSE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS FALSE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING FALSE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING FALSE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 16 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 256 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/**
+ * @brief Serial over USB number of buffers.
+ * @note The default is 2 buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_NUMBER 2
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* UART driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
+#define UART_USE_WAIT FALSE
+#endif
+
+/**
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define UART_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/main.c b/testhal/MSP430X/EXP430FR5969/ADC/main.c new file mode 100644 index 0000000..8a530ec --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/main.c @@ -0,0 +1,270 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "string.h"
+#include "stdio.h" /* eesh */
+
+/* Disable watchdog because of lousy startup code in newlib */
+static void __attribute__((naked, section(".crt_0042disable_watchdog"), used))
+disable_watchdog(void) {
+ WDTCTL = WDTPW | WDTHOLD;
+}
+
+const char * start_msg = "\r\n\r\nExecuting ADC test suite...\r\n";
+const char * test_1_msg = "\r\nTEST 1: 1 channel, depth 1, no circular\r\n";
+const char * test_2_msg = "\r\nTEST 2: 1 channel, depth 8, no circular\r\n";
+const char * test_3_msg = "\r\nTEST 3: 4 channels, depth 1, no circular\r\n";
+const char * test_4_msg = "\r\nTEST 4: 4 channels, depth 8, no circular\r\n";
+const char * test_5_msg = "\r\nTEST 5: 1 channel, depth 1, circular\r\n";
+const char * test_6_msg = "\r\nTEST 6: 1 channel, depth 8, circular\r\n";
+const char * test_7_msg = "\r\nTEST 7: 4 channel, depth 1, circular\r\n";
+const char * test_8_msg = "\r\nTEST 8: 4 channel, depth 8, circular\r\n";
+const char * test_9_msg = "\r\nTEST 9: 1 channel, depth 1, synchronous\r\n";
+const char * test_10_msg = "\r\nTEST 9: 1 channel, depth 1, exclusive\r\n";
+
+const char * success_string = "\r\nSUCCESS\r\n";
+const char * fail_string = "\r\nFAILURE\r\n";
+
+char out_string[128];
+const char * raw_fmt_string = "Raw Value: %d\r\n";
+const char * cooked_fmt_string = "Cooked Value: %d\r\n";
+const char * chn_fmt_string = "\r\nCHANNEL %d\r\n";
+
+uint16_t buffer_margin[72];
+uint16_t * buffer = buffer_margin + 4;
+uint8_t depth;
+uint8_t cb_arg = 0;
+uint16_t cb_expect;
+
+static const int test = 0;
+
+ADCConfig config = {
+ 255 /* dma_index */
+};
+
+ADCConversionGroup group = {
+ false, /* circular */
+ 1, /* num_channels */
+ NULL, /* end_cb */
+ NULL, /* error_cb */
+ {
+ 30, 31, 30, 31, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, /* channels */
+ MSP430X_ADC_RES_12BIT, /* res */
+ MSP430X_ADC_SHT_32, /* rate */
+ MSP430X_ADC_VSS_VREF_BUF, /* ref */
+ MSP430X_REF_2V5 /* vref_src */
+};
+
+void print(const char * msg) {
+
+ if (!test) {
+ chnWrite(&SD0, (const uint8_t *)msg, strlen(msg));
+ }
+}
+
+void adc_callback(ADCDriver * adcp, adcsample_t *buffer, size_t n) {
+ (void)adcp;
+ (void)buffer;
+ (void)n;
+
+ cb_arg++;
+
+ if (adcp->grpp->circular && cb_arg == cb_expect) {
+ osalSysLockFromISR();
+ adcStopConversionI(adcp);
+ osalSysUnlockFromISR();
+ }
+}
+
+void run_test(const char * test_msg, uint8_t num_channels, uint8_t depth,
+ bool circular) {
+ print(test_msg);
+
+ cb_arg = 0;
+
+ group.num_channels = num_channels;
+ group.circular = circular;
+ group.end_cb = adc_callback;
+
+ if (depth > 1) cb_expect = 2;
+ else cb_expect = 1;
+ if (circular) cb_expect *= 3;
+
+ adcStartConversion(&ADCD1, &group, buffer, depth);
+
+ while (ADCD1.state == ADC_ACTIVE) ;
+
+
+ int index = 0;
+ for (int j = 0; j < depth; j++) {
+ for (int i = 0; i < group.num_channels; i++) {
+ index = i + (j * group.num_channels);
+ sniprintf(out_string, 128, chn_fmt_string, group.channels[i]);
+ print(out_string);
+
+ sniprintf(out_string, 128, raw_fmt_string, buffer[index]);
+ print(out_string);
+
+ if (group.channels[i] == 30) { /* internal temp sensor */
+ buffer[index] = adcMSP430XAdjustTemp(&group, buffer[index]);
+ }
+ else {
+ buffer[index] = adcMSP430XAdjustResult(&group, buffer[index]);
+ }
+
+ sniprintf(out_string, 128, cooked_fmt_string, buffer[index]);
+ print(out_string);
+ }
+ }
+
+ if (cb_arg == cb_expect) {
+ print(success_string);
+ }
+ else {
+ print(fail_string);
+ }
+}
+
+/*
+ * Thread 2.
+ */
+THD_WORKING_AREA(waThread1, 4096);
+THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+
+ /*
+ * Activate the serial driver 0 using the driver default configuration.
+ */
+ sdStart(&SD0, NULL);
+
+
+ while (chnGetTimeout(&SD0, TIME_INFINITE)) {
+ print(start_msg);
+ chThdSleepMilliseconds(2000);
+
+ /* Activate the ADC driver 1 using its config */
+ adcStart(&ADCD1, &config);
+
+ /* Test 1 - 1ch1d, no circular */
+ run_test(test_1_msg, 1, 1, false);
+
+ /* Test 2 - 1ch8d, no circular */
+ run_test(test_2_msg, 1, 8, false);
+
+ /* Test 3 - 4chd1, no circular */
+ run_test(test_3_msg, 4, 1, false);
+
+ /* Test 4 - 4ch8d, no circular */
+ run_test(test_4_msg, 4, 8, false);
+
+ /* Test 5 - 1ch1d, circular */
+ run_test(test_5_msg, 1, 1, true);
+
+ /* Test 6 - 1ch8d, circular */
+ run_test(test_6_msg, 1, 8, true);
+
+ /* Test 7 - 4ch1d, circular */
+ run_test(test_7_msg, 4, 1, true);
+
+ /* Test 8 - 4ch8d, circular */
+ run_test(test_8_msg, 4, 8, true);
+
+ /* Test 9 - 1ch1d, synchronous */
+ print(test_9_msg);
+ cb_arg = 0;
+
+ group.num_channels = 1;
+ group.circular = false;
+ group.end_cb = adc_callback;
+
+ cb_expect = 1;
+
+ adcConvert(&ADCD1, &group, buffer, 1);
+
+ while (ADCD1.state == ADC_ACTIVE) ;
+
+ sniprintf(out_string, 128, chn_fmt_string, group.channels[0]);
+ print(out_string);
+
+ sniprintf(out_string, 128, raw_fmt_string, buffer[0]);
+ print(out_string);
+
+ buffer[0] = adcMSP430XAdjustTemp(&group, buffer[0]);
+
+ sniprintf(out_string, 128, cooked_fmt_string, buffer[0]);
+ print(out_string);
+
+ if (cb_arg == cb_expect) {
+ print(success_string);
+ }
+ else {
+ print(fail_string);
+ }
+
+ /* Test 10 - 1ch1d, exclusive */
+ adcStop(&ADCD1);
+
+ config.dma_index = 0;
+
+ adcStart(&ADCD1, &config);
+
+ run_test(test_10_msg, 1, 1, false);
+
+ adcStop(&ADCD1);
+
+ config.dma_index = 255;
+ }
+}
+
+/*
+ * Threads static table, one entry per thread. The number of entries must
+ * match NIL_CFG_NUM_THREADS.
+ */
+THD_TABLE_BEGIN
+ THD_TABLE_ENTRY(waThread1, "adc_test", Thread1, NULL)
+THD_TABLE_END
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ WDTCTL = WDTPW | WDTHOLD;
+
+ halInit();
+ chSysInit();
+
+ /* This is now the idle thread loop, you may perform here a low priority
+ task but you must never try to sleep or wait in this loop. Note that
+ this tasks runs at the lowest priority level so any instruction added
+ here will be executed after all other tasks have been started.*/
+ while (true) {
+ }
+}
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/mcuconf.h b/testhal/MSP430X/EXP430FR5969/ADC/mcuconf.h new file mode 100644 index 0000000..70e29ff --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/mcuconf.h @@ -0,0 +1,68 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * MSP430X drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the driver
+ * is enabled in halconf.h.
+ *
+ */
+
+#define MSP430X_MCUCONF
+
+/* HAL driver system settings */
+#define MSP430X_ACLK_SRC MSP430X_VLOCLK
+#define MSP430X_LFXTCLK_FREQ 0
+#define MSP430X_HFXTCLK_FREQ 0
+#define MSP430X_DCOCLK_FREQ 8000000
+#define MSP430X_MCLK_DIV 1
+#define MSP430X_SMCLK_DIV 32
+
+/*
+ * SERIAL driver system settings.
+ */
+#define MSP430X_SERIAL_USE_USART0 TRUE
+#define MSP430X_USART0_CLK_SRC MSP430X_SMCLK_SRC
+#define MSP430X_SERIAL_USE_USART1 FALSE
+#define MSP430X_SERIAL_USE_USART2 FALSE
+#define MSP430X_SERIAL_USE_USART3 FALSE
+
+/*
+ * ST driver system settings.
+ */
+#define MSP430X_ST_CLK_SRC MSP430X_SMCLK_SRC
+#define MSP430X_ST_TIMER_TYPE B
+#define MSP430X_ST_TIMER_INDEX 0
+
+/*
+ * SPI driver system settings.
+ */
+#define MSP430X_SPI_USE_SPIA1 FALSE
+#define MSP430X_SPI_USE_SPIB0 FALSE
+#define MSP430X_SPI_EXCLUSIVE_DMA TRUE
+
+/*
+ * ADC driver system settings
+ */
+#define MSP430X_ADC_EXCLUSIVE_DMA TRUE
+#define MSP430X_ADC1_FREQ 5000000 / 256
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/MSP430X/EXP430FR5969/ADC/msp_vectors.c b/testhal/MSP430X/EXP430FR5969/ADC/msp_vectors.c new file mode 100644 index 0000000..d12ed53 --- /dev/null +++ b/testhal/MSP430X/EXP430FR5969/ADC/msp_vectors.c @@ -0,0 +1,286 @@ +#include <msp430.h>
+
+__attribute__((interrupt(1)))
+void Vector1(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(2)))
+void Vector2(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(3)))
+void Vector3(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(4)))
+void Vector4(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(5)))
+void Vector5(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(6)))
+void Vector6(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(7)))
+void Vector7(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(8)))
+void Vector8(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(9)))
+void Vector9(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(10)))
+void Vector10(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(11)))
+void Vector11(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(12)))
+void Vector12(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(13)))
+void Vector13(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(14)))
+void Vector14(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(15)))
+void Vector15(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(16)))
+void Vector16(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(17)))
+void Vector17(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(18)))
+void Vector18(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(19)))
+void Vector19(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(20)))
+void Vector20(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(21)))
+void Vector21(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(22)))
+void Vector22(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(23)))
+void Vector23(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(24)))
+void Vector24(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(25)))
+void Vector25(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(26)))
+void Vector26(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(27)))
+void Vector27(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(28)))
+void Vector28(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(29)))
+void Vector29(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(30)))
+void Vector30(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(31)))
+void Vector31(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(32)))
+void Vector32(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(35)))
+void Vector35(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(36)))
+void Vector36(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(38)))
+void Vector38(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(39)))
+void Vector39(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(41)))
+void Vector41(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(42)))
+void Vector42(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(44)))
+void Vector44(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(45)))
+void Vector45(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(46)))
+void Vector46(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(48)))
+void Vector48(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(50)))
+void Vector50(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(51)))
+void Vector51(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(53)))
+void Vector53(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(54)))
+void Vector54(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(55)))
+void Vector55(void) {
+
+ while (1) {
+ }
+}
+
+
diff --git a/testhal/MSP430X/EXP430FR5969/DMA/main.c b/testhal/MSP430X/EXP430FR5969/DMA/main.c index 1929af1..757eedc 100644 --- a/testhal/MSP430X/EXP430FR5969/DMA/main.c +++ b/testhal/MSP430X/EXP430FR5969/DMA/main.c @@ -35,6 +35,8 @@ const char * test_6_msg = "TEST 6: Attempt to claim already claimed DMA " "and succeed.\r\n";
const char * test_7_msg = "TEST 7: Claim DMA channel 1, perform a Word-to-word "
"memcpy, and release it\r\n";
+const char * test_8_msg = "TEST 8: Claim all three DMA channels, try to issue dmaRequest, "
+ "fail\r\n";
const char * succeed_string = "SUCCESS\r\n\r\n";
const char * fail_string = "FAILURE\r\n\r\n";
@@ -43,6 +45,8 @@ char instring[256]; char outstring[256];
msp430x_dma_req_t * request;
uint8_t cb_arg = 1;
+bool result;
+int result_i;
void dma_callback_test(void * args) {
@@ -120,6 +124,8 @@ msp430x_dma_req_t test_5_req = { };
msp430x_dma_ch_t ch = { NULL, 0, NULL };
+msp430x_dma_ch_t ch1 = { NULL, 0, NULL };
+msp430x_dma_ch_t ch2 = { NULL, 0, NULL };
/*
* Thread 2.
@@ -146,7 +152,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_1_req;
- dmaRequest(request, TIME_INFINITE);
+ chSysLock();
+ dmaRequestS(request, TIME_INFINITE);
+ chSysUnlock();
if (strcmp("After DMA test \r\n", outstring)) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
@@ -162,7 +170,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_2_req;
- dmaRequest(request, TIME_INFINITE);
+ chSysLock();
+ dmaRequestS(request, TIME_INFINITE);
+ chSysUnlock();
if (strcmp("After DMA test \r\n", outstring)) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
@@ -178,7 +188,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_3_req;
- dmaRequest(request, TIME_INFINITE);
+ chSysLock();
+ dmaRequestS(request, TIME_INFINITE);
+ chSysUnlock();
if (strcmp("AAAAAAAAAAAAAAAA\r\n", outstring)) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
@@ -196,7 +208,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_4_req;
- dmaRequest(request, TIME_INFINITE);
+ chSysLock();
+ dmaRequestS(request, TIME_INFINITE);
+ chSysUnlock();
if (strcmp("After DMA test \r\n", outstring) || cb_arg) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
@@ -213,7 +227,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_5_req;
- dmaAcquire(&ch, 0);
+ chSysLock();
+ dmaAcquireI(&ch, 0);
+ chSysUnlock();
dmaTransfer(&ch, request);
if (strcmp("After DMA test \r\n", outstring)) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
@@ -225,11 +241,17 @@ THD_FUNCTION(Thread1, arg) { /* Test 6 - Attempt to claim DMA channel 0, fail, release it, attempt to
* claim it again */
chnWrite(&SD0, (const uint8_t *)test_6_msg, strlen(test_6_msg));
- if (!dmaAcquire(&ch, 0)) {
+ chSysLock();
+ result = dmaAcquireI(&ch, 0);
+ chSysUnlock();
+ if (!result) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
dmaRelease(&ch);
- if (dmaAcquire(&ch, 0)) {
+ chSysLock();
+ result = dmaAcquireI(&ch, 0);
+ chSysUnlock();
+ if (result) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
else {
@@ -246,7 +268,9 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
}
request = &test_5_req;
- dmaAcquire(&ch, 1);
+ chSysLock();
+ dmaAcquireI(&ch, 1);
+ chSysUnlock();
dmaTransfer(&ch, request);
if (strcmp("After DMA test \r\n", outstring)) {
chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
@@ -255,6 +279,40 @@ THD_FUNCTION(Thread1, arg) { chnWrite(&SD0, (const uint8_t *)succeed_string, strlen(succeed_string));
}
dmaRelease(&ch);
+
+ /* Test 8 - Claim all 3 DMA channels, attempt dmaRequest, fail */
+ chnWrite(&SD0, (const uint8_t *)test_8_msg, strlen(test_8_msg));
+ chSysLock();
+ result = dmaAcquireI(&ch, 0);
+ chSysUnlock();
+ if (result) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ chSysLock();
+ result = dmaAcquireI(&ch1, 1);
+ chSysUnlock();
+ if (result) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ chSysLock();
+ result = dmaAcquireI(&ch2, 2);
+ chSysUnlock();
+ if (result) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ chSysLock();
+ result_i = dmaRequestS(request, TIME_IMMEDIATE);
+ chSysUnlock();
+ if (result_i > 0) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ else {
+ chnWrite(&SD0, (const uint8_t *)succeed_string, strlen(succeed_string));
+ }
+ dmaRelease(&ch);
+ dmaRelease(&ch1);
+ dmaRelease(&ch2);
+
}
}
diff --git a/testhal/MSP430X/EXP430FR5969/DMA/msp_vectors.c b/testhal/MSP430X/EXP430FR5969/DMA/msp_vectors.c index 8968fb9..f5ad4b6 100644 --- a/testhal/MSP430X/EXP430FR5969/DMA/msp_vectors.c +++ b/testhal/MSP430X/EXP430FR5969/DMA/msp_vectors.c @@ -192,18 +192,6 @@ void Vector32(void) { while (1) {
}
}
-__attribute__((interrupt(33)))
-void Vector33(void) {
-
- while (1) {
- }
-}
-__attribute__((interrupt(34)))
-void Vector34(void) {
-
- while (1) {
- }
-}
__attribute__((interrupt(35)))
void Vector35(void) {
@@ -216,12 +204,7 @@ void Vector36(void) { while (1) {
}
}
-__attribute__((interrupt(37)))
-void Vector37(void) {
- while (1) {
- }
-}
__attribute__((interrupt(38)))
void Vector38(void) {
@@ -234,12 +217,7 @@ void Vector39(void) { while (1) {
}
}
-__attribute__((interrupt(40)))
-void Vector40(void) {
- while (1) {
- }
-}
__attribute__((interrupt(41)))
void Vector41(void) {
diff --git a/testhal/MSP430X/EXP430FR5969/SPI/main.c b/testhal/MSP430X/EXP430FR5969/SPI/main.c index 17f5c86..8d28198 100644 --- a/testhal/MSP430X/EXP430FR5969/SPI/main.c +++ b/testhal/MSP430X/EXP430FR5969/SPI/main.c @@ -34,11 +34,12 @@ const char * test_5_msg = "TEST 5: spiIgnore\r\n"; const char * test_6_msg = "TEST 6: spiExchange\r\n";
const char * test_7_msg = "TEST 7: spiSend\r\n";
const char * test_8_msg = "TEST 8: spiReceive\r\n";
-const char * test_9_msg = "TEST 9: spiStartExchange with exclusive DMA\r\n";
-const char * test_10_msg =
- "TEST 10: spiStartExchange with exclusive DMA for TX\r\n";
+const char * test_9_msg = "TEST 9: spiPolledExchange\r\n";
+const char * test_10_msg = "TEST 10: spiStartExchange with exclusive DMA\r\n";
const char * test_11_msg =
- "TEST 11: spiStartExchange with exclusive DMA for RX\r\n";
+ "TEST 11: spiStartExchange with exclusive DMA for TX\r\n";
+const char * test_12_msg =
+ "TEST 12: spiStartExchange with exclusive DMA for RX\r\n";
const char * succeed_string = "SUCCESS\r\n\r\n";
const char * fail_string = "FAILURE\r\n\r\n";
@@ -270,6 +271,25 @@ THD_FUNCTION(Thread1, arg) { else {
chnWrite(&SD0, (const uint8_t *)succeed_string, strlen(succeed_string));
}
+
+ /* Test 9 - spiPolledExchange */
+ chnWrite(&SD0, (const uint8_t *)test_9_msg, strlen(test_9_msg));
+ strcpy(outstring, "After SPI test \r\n");
+ strcpy(instring, "Before SPI test \r\n");
+ if (strcmp("Before SPI test \r\n", instring) ||
+ strcmp("After SPI test \r\n", outstring)) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ spiSelect(&SPIDB0);
+ outstring[0] = spiPolledExchange(&SPIDB0, instring[0]);
+ spiUnselect(&SPIDB0);
+ if (strcmp("Bfter SPI test \r\n", outstring) ||
+ strcmp("Before SPI test \r\n", instring)) {
+ chnWrite(&SD0, (const uint8_t *)fail_string, strlen(fail_string));
+ }
+ else {
+ chnWrite(&SD0, (const uint8_t *)succeed_string, strlen(succeed_string));
+ }
/* Reconfigure SPIDA1 to use exclusive DMA for both */
spiStop(&SPIDA1);
@@ -278,8 +298,8 @@ THD_FUNCTION(Thread1, arg) { SPIDA1_config.spi_mode = 1; /* because why not get coverage */
spiStart(&SPIDA1, &SPIDA1_config);
- /* Test 9 - spiStartExchange with exclusive DMA */
- chnWrite(&SD0, (const uint8_t *)test_9_msg, strlen(test_9_msg));
+ /* Test 10 - spiStartExchange with exclusive DMA */
+ chnWrite(&SD0, (const uint8_t *)test_10_msg, strlen(test_10_msg));
strcpy(outstring, "After SPI test \r\n");
strcpy(instring, "Before SPI test \r\n");
cb_arg = 1;
@@ -307,8 +327,8 @@ THD_FUNCTION(Thread1, arg) { SPIDA1_config.spi_mode = 2; /* because why not get coverage */
spiStart(&SPIDA1, &SPIDA1_config);
- /* Test 10 - spiStartExchange with exclusive DMA for TX */
- chnWrite(&SD0, (const uint8_t *)test_10_msg, strlen(test_10_msg));
+ /* Test 11 - spiStartExchange with exclusive DMA for TX */
+ chnWrite(&SD0, (const uint8_t *)test_11_msg, strlen(test_11_msg));
strcpy(outstring, "After SPI test \r\n");
strcpy(instring, "Before SPI test \r\n");
cb_arg = 1;
@@ -336,8 +356,8 @@ THD_FUNCTION(Thread1, arg) { SPIDA1_config.spi_mode = 3; /* because why not get coverage */
spiStart(&SPIDA1, &SPIDA1_config);
- /* Test 11 - spiStartExchange with exclusive DMA for RX */
- chnWrite(&SD0, (const uint8_t *)test_11_msg, strlen(test_11_msg));
+ /* Test 12 - spiStartExchange with exclusive DMA for RX */
+ chnWrite(&SD0, (const uint8_t *)test_12_msg, strlen(test_12_msg));
strcpy(outstring, "After SPI test \r\n");
strcpy(instring, "Before SPI test \r\n");
cb_arg = 1;
diff --git a/testhal/MSP430X/EXP430FR5969/SPI/msp_vectors.c b/testhal/MSP430X/EXP430FR5969/SPI/msp_vectors.c index 8968fb9..c23cbc8 100644 --- a/testhal/MSP430X/EXP430FR5969/SPI/msp_vectors.c +++ b/testhal/MSP430X/EXP430FR5969/SPI/msp_vectors.c @@ -192,18 +192,6 @@ void Vector32(void) { while (1) {
}
}
-__attribute__((interrupt(33)))
-void Vector33(void) {
-
- while (1) {
- }
-}
-__attribute__((interrupt(34)))
-void Vector34(void) {
-
- while (1) {
- }
-}
__attribute__((interrupt(35)))
void Vector35(void) {
@@ -216,12 +204,6 @@ void Vector36(void) { while (1) {
}
}
-__attribute__((interrupt(37)))
-void Vector37(void) {
-
- while (1) {
- }
-}
__attribute__((interrupt(38)))
void Vector38(void) {
@@ -234,12 +216,6 @@ void Vector39(void) { while (1) {
}
}
-__attribute__((interrupt(40)))
-void Vector40(void) {
-
- while (1) {
- }
-}
__attribute__((interrupt(41)))
void Vector41(void) {
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/Makefile b/testhal/MSP430X/EXP430FR6989/ADC/Makefile new file mode 100644 index 0000000..b86021e --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/Makefile @@ -0,0 +1,206 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Optimization level, can be [0, 1, 2, 3, s].
+# 0 = turn off optimization. s = optimize for size.
+# (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
+OPTIMIZE = 0
+
+# Debugging format.
+DEBUG =
+#DEBUG = stabs
+
+# Memory/data model
+MODEL = small
+
+# Object files directory
+# To put object files in current directory, use a dot (.), do NOT make
+# this an empty or blank macro!
+OBJDIR = .
+
+# Compiler flag to set the C Standard level.
+# c89 = "ANSI" C
+# gnu89 = c89 plus GCC extensions
+# c99 = ISO C99 standard (not yet fully implemented)
+# gnu99 = c99 plus GCC extensions
+CSTANDARD = -std=gnu11
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O$(OPTIMIZE) -g$(DEBUG)
+ USE_OPT += -funsigned-char -fshort-enums
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = no
+endif
+
+# Enable the selected hardware multiplier
+ifeq ($(USE_HWMULT),)
+ USE_HWMULT = f5series
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = yes
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the idle thread stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_IDLE_STACKSIZE),)
+ USE_IDLE_STACKSIZE = 0xC00
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = nil
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS-RT
+CHIBIOS_CONTRIB = ../../../..
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC/mk/startup_msp430fr5xxx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/EXP430FR6989/board.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/MSP430X/platform.mk
+include $(CHIBIOS)/os/hal/osal/nil/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/nil/nil.mk
+include $(CHIBIOS_CONTRIB)/os/common/ports/MSP430X/compilers/GCC/mk/port.mk
+# Other files (optional).
+
+# Define linker script file here
+LDSCRIPT = $(STARTUPLD)/msp430fr6989.ld
+
+# C sources
+CSRC = $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(TESTSRC) \
+ msp_vectors.c \
+ main.c
+
+# C++ sources
+CPPSRC =
+
+# List ASM source files here
+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
+
+INCDIR = $(CHIBIOS)/os/license \
+ $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = msp430fr6989
+
+TRGT = msp430-elf-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# MSP430-specific options here
+MOPT = -m$(MODEL)
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS_CONTRIB)/os/common/startup/MSP430X/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/chconf.h b/testhal/MSP430X/EXP430FR6989/ADC/chconf.h new file mode 100644 index 0000000..3b7a8e1 --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/chconf.h @@ -0,0 +1,274 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file nilconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef CHCONF_H
+#define CHCONF_H
+
+#define _CHIBIOS_NIL_CONF_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Number of user threads in the application.
+ * @note This number is not inclusive of the idle thread which is
+ * Implicitly handled.
+ */
+#define CH_CFG_NUM_THREADS 1
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name System timer settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 16
+
+/**
+ * @brief System tick frequency.
+ * @note This value together with the @p CH_CFG_ST_RESOLUTION
+ * option defines the maximum amount of time allowed for
+ * timeouts.
+ */
+#define CH_CFG_ST_FREQUENCY 1000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note Feature not currently implemented.
+ * @note The default is @p FALSE.
+ */
+#define CH_CFG_USE_MUTEXES FALSE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note Feature not currently implemented.
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief System assertions.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Stack check.
+ *
+ *@note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System initialization hook.
+ */
+#if !defined(CH_CFG_SYSTEM_INIT_HOOK) || defined(__DOXYGEN__)
+#define CH_CFG_SYSTEM_INIT_HOOK() { \
+}
+#endif
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXT_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ */
+#define CH_CFG_THREAD_EXT_INIT_HOOK(tr) { \
+ /* Add custom threads initialization code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief System halt hook.
+ */
+#if !defined(CH_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in nilcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/halconf.h b/testhal/MSP430X/EXP430FR6989/ADC/halconf.h new file mode 100644 index 0000000..2982a63 --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/halconf.h @@ -0,0 +1,388 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef HALCONF_H
+#define HALCONF_H
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the DMA subsystem.
+ */
+#if !defined(HAL_USE_DMA) || defined(__DOXYGEN__)
+#define HAL_USE_DMA TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC TRUE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE FALSE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS FALSE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING FALSE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING FALSE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 16 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 256 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/**
+ * @brief Serial over USB number of buffers.
+ * @note The default is 2 buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_NUMBER 2
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* UART driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
+#define UART_USE_WAIT FALSE
+#endif
+
+/**
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define UART_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/main.c b/testhal/MSP430X/EXP430FR6989/ADC/main.c new file mode 100644 index 0000000..06f9a9c --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/main.c @@ -0,0 +1,254 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "string.h"
+#include "stdio.h" /* eesh */
+
+/* Disable watchdog because of lousy startup code in newlib */
+static void __attribute__((naked, section(".crt_0042disable_watchdog"), used))
+disable_watchdog(void) {
+ WDTCTL = WDTPW | WDTHOLD;
+}
+
+const char * start_msg = "\r\n\r\nExecuting ADC test suite...\r\n";
+const char * test_1_msg = "\r\nTEST 1: 1 channel, depth 1, no circular\r\n";
+const char * test_2_msg = "\r\nTEST 2: 1 channel, depth 8, no circular\r\n";
+const char * test_3_msg = "\r\nTEST 3: 4 channels, depth 1, no circular\r\n";
+const char * test_4_msg = "\r\nTEST 4: 4 channels, depth 8, no circular\r\n";
+const char * test_5_msg = "\r\nTEST 5: 1 channel, depth 1, circular\r\n";
+const char * test_6_msg = "\r\nTEST 6: 1 channel, depth 8, circular\r\n";
+const char * test_7_msg = "\r\nTEST 7: 4 channel, depth 1, circular\r\n";
+const char * test_8_msg = "\r\nTEST 8: 4 channel, depth 8, circular\r\n";
+const char * test_9_msg = "\r\nTEST 9: 1 channel, depth 1, synchronous\r\n";
+
+const char * success_string = "\r\nSUCCESS\r\n";
+const char * fail_string = "\r\nFAILURE\r\n";
+
+char out_string[128];
+const char * raw_fmt_string = "Raw Value: %d\r\n";
+const char * cooked_fmt_string = "Cooked Value: %d\r\n";
+const char * chn_fmt_string = "\r\nCHANNEL %d\r\n";
+
+uint16_t buffer_margin[72];
+uint16_t * buffer = buffer_margin + 4;
+uint8_t depth;
+uint8_t cb_arg = 0;
+uint16_t cb_expect;
+
+static const int test = 0;
+
+ADCConfig config = {
+};
+
+ADCConversionGroup group = {
+ false, /* circular */
+ 1, /* num_channels */
+ NULL, /* end_cb */
+ NULL, /* error_cb */
+ {
+ 30, 31, 30, 31, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, /* channels */
+ MSP430X_ADC_RES_12BIT, /* res */
+ MSP430X_ADC_SHT_32, /* rate */
+ MSP430X_ADC_VSS_VREF_BUF, /* ref */
+ MSP430X_REF_2V5 /* vref_src */
+};
+
+void print(const char * msg) {
+
+ if (!test) {
+ chnWrite(&SD1, (const uint8_t *)msg, strlen(msg));
+ }
+}
+
+void adc_callback(ADCDriver * adcp, adcsample_t *buffer, size_t n) {
+ (void)adcp;
+ (void)buffer;
+ (void)n;
+
+ cb_arg++;
+
+ if (adcp->grpp->circular && cb_arg == cb_expect) {
+ osalSysLockFromISR();
+ adcStopConversionI(adcp);
+ osalSysUnlockFromISR();
+ }
+}
+
+void run_test(const char * test_msg, uint8_t num_channels, uint8_t depth,
+ bool circular) {
+ print(test_msg);
+
+ cb_arg = 0;
+
+ group.num_channels = num_channels;
+ group.circular = circular;
+ group.end_cb = adc_callback;
+
+ if (depth > 1) cb_expect = 2;
+ else cb_expect = 1;
+ if (circular) cb_expect *= 3;
+
+ adcStartConversion(&ADCD1, &group, buffer, depth);
+
+ while (ADCD1.state == ADC_ACTIVE) ;
+
+
+ int index = 0;
+ for (int j = 0; j < depth; j++) {
+ for (int i = 0; i < group.num_channels; i++) {
+ index = i + (j * group.num_channels);
+ sniprintf(out_string, 128, chn_fmt_string, group.channels[i]);
+ print(out_string);
+
+ sniprintf(out_string, 128, raw_fmt_string, buffer[index]);
+ print(out_string);
+
+ if (group.channels[i] == 30) { /* internal temp sensor */
+ buffer[index] = adcMSP430XAdjustTemp(&group, buffer[index]);
+ }
+ else {
+ buffer[index] = adcMSP430XAdjustResult(&group, buffer[index]);
+ }
+
+ sniprintf(out_string, 128, cooked_fmt_string, buffer[index]);
+ print(out_string);
+ }
+ }
+
+ if (cb_arg == cb_expect) {
+ print(success_string);
+ }
+ else {
+ print(fail_string);
+ }
+}
+
+/*
+ * Thread 2.
+ */
+THD_WORKING_AREA(waThread1, 4096);
+THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+
+ /*
+ * Activate the serial driver 0 using the driver default configuration.
+ */
+ sdStart(&SD1, NULL);
+
+ /* Activate the ADC driver 1 using its config */
+ adcStart(&ADCD1, &config);
+
+ while (chnGetTimeout(&SD1, TIME_INFINITE)) {
+ print(start_msg);
+ chThdSleepMilliseconds(2000);
+
+ /* Test 1 - 1ch1d, no circular */
+ run_test(test_1_msg, 1, 1, false);
+
+ /* Test 2 - 1ch8d, no circular */
+ run_test(test_2_msg, 1, 8, false);
+
+ /* Test 3 - 4chd1, no circular */
+ run_test(test_3_msg, 4, 1, false);
+
+ /* Test 4 - 4ch8d, no circular */
+ run_test(test_4_msg, 4, 8, false);
+
+ /* Test 5 - 1ch1d, circular */
+ run_test(test_5_msg, 1, 1, true);
+
+ /* Test 6 - 1ch8d, circular */
+ run_test(test_6_msg, 1, 8, true);
+
+ /* Test 7 - 4ch1d, circular */
+ run_test(test_7_msg, 4, 1, true);
+
+ /* Test 8 - 4ch8d, circular */
+ run_test(test_8_msg, 4, 8, true);
+
+ /* Test 9 - 1ch1d, synchronous */
+ print(test_9_msg);
+ cb_arg = 0;
+
+ group.num_channels = 1;
+ group.circular = false;
+ group.end_cb = adc_callback;
+
+ cb_expect = 1;
+
+ adcConvert(&ADCD1, &group, buffer, 1);
+
+ while (ADCD1.state == ADC_ACTIVE) ;
+
+ sniprintf(out_string, 128, chn_fmt_string, group.channels[0]);
+ print(out_string);
+
+ sniprintf(out_string, 128, raw_fmt_string, buffer[0]);
+ print(out_string);
+
+ buffer[0] = adcMSP430XAdjustTemp(&group, buffer[0]);
+
+ sniprintf(out_string, 128, cooked_fmt_string, buffer[0]);
+ print(out_string);
+
+ if (cb_arg == cb_expect) {
+ print(success_string);
+ }
+ else {
+ print(fail_string);
+ }
+ }
+}
+
+/*
+ * Threads static table, one entry per thread. The number of entries must
+ * match NIL_CFG_NUM_THREADS.
+ */
+THD_TABLE_BEGIN
+ THD_TABLE_ENTRY(waThread1, "adc_test", Thread1, NULL)
+THD_TABLE_END
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ WDTCTL = WDTPW | WDTHOLD;
+
+ halInit();
+ chSysInit();
+
+ /* This is now the idle thread loop, you may perform here a low priority
+ task but you must never try to sleep or wait in this loop. Note that
+ this tasks runs at the lowest priority level so any instruction added
+ here will be executed after all other tasks have been started.*/
+ while (true) {
+ }
+}
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/mcuconf.h b/testhal/MSP430X/EXP430FR6989/ADC/mcuconf.h new file mode 100644 index 0000000..bcb0c69 --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/mcuconf.h @@ -0,0 +1,68 @@ +/*
+ ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * MSP430X drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the driver
+ * is enabled in halconf.h.
+ *
+ */
+
+#define MSP430X_MCUCONF
+
+/* HAL driver system settings */
+#define MSP430X_ACLK_SRC MSP430X_VLOCLK
+#define MSP430X_LFXTCLK_FREQ 0
+#define MSP430X_HFXTCLK_FREQ 0
+#define MSP430X_DCOCLK_FREQ 8000000
+#define MSP430X_MCLK_DIV 1
+#define MSP430X_SMCLK_DIV 32
+
+/*
+ * SERIAL driver system settings.
+ */
+#define MSP430X_SERIAL_USE_USART1 TRUE
+#define MSP430X_USART1_CLK_SRC MSP430X_SMCLK_SRC
+#define MSP430X_SERIAL_USE_USART0 FALSE
+#define MSP430X_SERIAL_USE_USART2 FALSE
+#define MSP430X_SERIAL_USE_USART3 FALSE
+
+/*
+ * ST driver system settings.
+ */
+#define MSP430X_ST_CLK_SRC MSP430X_SMCLK_SRC
+#define MSP430X_ST_TIMER_TYPE B
+#define MSP430X_ST_TIMER_INDEX 0
+
+/*
+ * SPI driver system settings.
+ */
+#define MSP430X_SPI_USE_SPIA1 FALSE
+#define MSP430X_SPI_USE_SPIB0 FALSE
+#define MSP430X_SPI_EXCLUSIVE_DMA FALSE
+
+/*
+ * ADC driver system settings
+ */
+#define MSP430X_ADC_EXCLUSIVE_DMA FALSE
+#define MSP430X_ADC1_FREQ 5000000 / 256
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/MSP430X/EXP430FR6989/ADC/msp_vectors.c b/testhal/MSP430X/EXP430FR6989/ADC/msp_vectors.c new file mode 100644 index 0000000..24e2a11 --- /dev/null +++ b/testhal/MSP430X/EXP430FR6989/ADC/msp_vectors.c @@ -0,0 +1,286 @@ +#include <msp430.h>
+
+__attribute__((interrupt(1)))
+void Vector1(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(2)))
+void Vector2(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(3)))
+void Vector3(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(4)))
+void Vector4(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(5)))
+void Vector5(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(6)))
+void Vector6(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(7)))
+void Vector7(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(8)))
+void Vector8(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(9)))
+void Vector9(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(10)))
+void Vector10(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(11)))
+void Vector11(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(12)))
+void Vector12(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(13)))
+void Vector13(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(14)))
+void Vector14(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(15)))
+void Vector15(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(16)))
+void Vector16(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(17)))
+void Vector17(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(18)))
+void Vector18(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(19)))
+void Vector19(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(20)))
+void Vector20(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(21)))
+void Vector21(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(22)))
+void Vector22(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(23)))
+void Vector23(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(24)))
+void Vector24(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(25)))
+void Vector25(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(26)))
+void Vector26(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(27)))
+void Vector27(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(28)))
+void Vector28(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(29)))
+void Vector29(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(30)))
+void Vector30(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(33)))
+void Vector33(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(34)))
+void Vector34(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(36)))
+void Vector36(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(37)))
+void Vector37(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(39)))
+void Vector39(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(40)))
+void Vector40(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(42)))
+void Vector42(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(44)))
+void Vector44(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(45)))
+void Vector45(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(47)))
+void Vector47(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(48)))
+void Vector48(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(49)))
+void Vector49(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(50)))
+void Vector50(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(51)))
+void Vector51(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(53)))
+void Vector53(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(54)))
+void Vector54(void) {
+
+ while (1) {
+ }
+}
+__attribute__((interrupt(55)))
+void Vector55(void) {
+
+ while (1) {
+ }
+}
+
+
diff --git a/testhal/STM32/STM32F0xx/crc/halconf_community.h b/testhal/STM32/STM32F0xx/crc/halconf_community.h index 2bc41bf..31ac01e 100644 --- a/testhal/STM32/STM32F0xx/crc/halconf_community.h +++ b/testhal/STM32/STM32F0xx/crc/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _HALCONF_COMMUNITY_H_
-#define _HALCONF_COMMUNITY_H_
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
@@ -113,6 +113,6 @@ #define CRC_USE_MUTUAL_EXCLUSION TRUE
#endif
-#endif /* _HALCONF_COMMUNITY_H_ */
+#endif /* HALCONF_COMMUNITY_H */
/** @} */
diff --git a/testhal/STM32/STM32F0xx/crc/mcuconf_community.h b/testhal/STM32/STM32F0xx/crc/mcuconf_community.h index 8df78ec..bbd2608 100644 --- a/testhal/STM32/STM32F0xx/crc/mcuconf_community.h +++ b/testhal/STM32/STM32F0xx/crc/mcuconf_community.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef _MCUCONF_COMMUNITY_H_ -#define _MCUCONF_COMMUNITY_H_ +#ifndef MCUCONF_COMMUNITY_H +#define MCUCONF_COMMUNITY_H /* * CRC driver system settings. @@ -30,4 +30,4 @@ #define CRCSW_CRC16_TABLE TRUE #define CRCSW_PROGRAMMABLE TRUE -#endif +#endif /* MCUCONF_COMMUNITY_H */ diff --git a/testhal/STM32/STM32F0xx/onewire/.project b/testhal/STM32/STM32F0xx/onewire/.project index 6599a83..8776e6e 100644 --- a/testhal/STM32/STM32F0xx/onewire/.project +++ b/testhal/STM32/STM32F0xx/onewire/.project @@ -25,6 +25,11 @@ </natures>
<linkedResources>
<link>
+ <name>hw_abstracted</name>
+ <type>2</type>
+ <locationURI>PARENT-3-PROJECT_LOC/hw_abstracted</locationURI>
+ </link>
+ <link>
<name>os-community</name>
<type>2</type>
<locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
diff --git a/testhal/STM32/STM32F0xx/onewire/Makefile b/testhal/STM32/STM32F0xx/onewire/Makefile index d121cee..de965e3 100644 --- a/testhal/STM32/STM32F0xx/onewire/Makefile +++ b/testhal/STM32/STM32F0xx/onewire/Makefile @@ -75,8 +75,9 @@ endif PROJECT = ch
# Imported source files and paths
-CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS = ../../../../../ChibiOS-RT
CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+TESTHAL = $(CHIBIOS_CONTRIB)/testhal/common/onewire
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk
# HAL-OSAL files (optional).
@@ -102,8 +103,8 @@ CSRC = $(STARTUPSRC) \ $(BOARDSRC) \
$(TESTSRC) \
main.c \
- onewire_test.c
-
+ $(TESTHAL)/testhal_onewire.c
+
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CPPSRC =
@@ -135,7 +136,8 @@ ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) INCDIR = $(CHIBIOS)/os/license \
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
- $(CHIBIOS)/os/various
+ $(CHIBIOS)/os/various \
+ $(TESTHAL)
#
# Project, sources and paths
diff --git a/testhal/STM32/STM32F4xx/onewire/onewire_test.h b/testhal/STM32/STM32F0xx/onewire/boarddef.h index 1bec2d0..fd9842b 100644 --- a/testhal/STM32/STM32F4xx/onewire/onewire_test.h +++ b/testhal/STM32/STM32F0xx/onewire/boarddef.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS/RT - Copyright (C) 2016 Uladzimir Pylinsky aka barthess Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,15 +14,15 @@ limitations under the License. */ -#ifndef ONEWIRE_TEST_H_ -#define ONEWIRE_TEST_H_ +#ifndef BOARDDEF_H_ +#define BOARDDEF_H_ -#ifdef __cplusplus -extern "C" { -#endif - void onewireTest(void); -#ifdef __cplusplus -} -#endif +#define ONEWIRE_PORT GPIOB +#define ONEWIRE_PIN GPIOB_PIN0 +#define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN) +#define search_led_off() (palClearPad(GPIOC, GPIOC_LED4)) +#define search_led_on() (palSetPad(GPIOC, GPIOC_LED4)) +#define ONEWIRE_MASTER_CHANNEL 2 +#define ONEWIRE_SAMPLE_CHANNEL 3 -#endif /* ONEWIRE_TEST_H_ */ +#endif /* BOARDDEF_H_ */ diff --git a/testhal/STM32/STM32F0xx/onewire/halconf.h b/testhal/STM32/STM32F0xx/onewire/halconf.h index c3b1671..64811a5 100644 --- a/testhal/STM32/STM32F0xx/onewire/halconf.h +++ b/testhal/STM32/STM32F0xx/onewire/halconf.h @@ -1,5 +1,5 @@ /*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -25,8 +25,8 @@ * @{
*/
-#ifndef _HALCONF_H_
-#define _HALCONF_H_
+#ifndef HALCONF_H
+#define HALCONF_H
#include "mcuconf.h"
@@ -45,17 +45,17 @@ #endif
/**
- * @brief Enables the DAC subsystem.
+ * @brief Enables the CAN subsystem.
*/
-#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
-#define HAL_USE_DAC FALSE
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
#endif
/**
- * @brief Enables the CAN subsystem.
+ * @brief Enables the DAC subsystem.
*/
-#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
-#define HAL_USE_CAN FALSE
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
#endif
/**
@@ -294,7 +294,7 @@ * @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
- * @note The default is 64 bytes for both the transmission and receive
+ * @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
@@ -309,13 +309,21 @@ * @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
- * @note The default is 64 bytes for both the transmission and receive
+ * @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
+/**
+ * @brief Serial over USB number of buffers.
+ * @note The default is 2 buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_NUMBER 2
+#endif
+
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
@@ -337,11 +345,43 @@ #endif
/*===========================================================================*/
+/* UART driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
+#define UART_USE_WAIT FALSE
+#endif
+
+/**
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define UART_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+/*===========================================================================*/
/* Community drivers's includes */
/*===========================================================================*/
#include "halconf_community.h"
-#endif /* _HALCONF_H_ */
+#endif /* HALCONF_H */
/** @} */
diff --git a/testhal/STM32/STM32F0xx/onewire/halconf_community.h b/testhal/STM32/STM32F0xx/onewire/halconf_community.h index 91dbfbc..0621fdb 100644 --- a/testhal/STM32/STM32F0xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F0xx/onewire/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _HALCONF_COMMUNITY_H_
-#define _HALCONF_COMMUNITY_H_
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
@@ -93,6 +93,6 @@ */
#define ONEWIRE_USE_SEARCH_ROM TRUE
-#endif /* _HALCONF_COMMUNITY_H_ */
+#endif /* HALCONF_COMMUNITY_H */
/** @} */
diff --git a/testhal/STM32/STM32F0xx/onewire/main.c b/testhal/STM32/STM32F0xx/onewire/main.c index 793bffe..5265edc 100644 --- a/testhal/STM32/STM32F0xx/onewire/main.c +++ b/testhal/STM32/STM32F0xx/onewire/main.c @@ -17,7 +17,7 @@ #include "ch.h"
#include "hal.h"
-#include "onewire_test.h"
+#include "testhal_onewire.h"
/*
* Application entry point.
diff --git a/testhal/STM32/STM32F0xx/onewire/mcuconf.h b/testhal/STM32/STM32F0xx/onewire/mcuconf.h index 89b0fd1..7773406 100644 --- a/testhal/STM32/STM32F0xx/onewire/mcuconf.h +++ b/testhal/STM32/STM32F0xx/onewire/mcuconf.h @@ -1,5 +1,5 @@ /*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -14,6 +14,9 @@ limitations under the License.
*/
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
/*
* STM32F0xx drivers configuration.
* The following settings override the default settings present in
@@ -156,6 +159,13 @@ #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG FALSE
+
+/*
* header for community drivers.
*/
#include "mcuconf_community.h"
+
+#endif /* MCUCONF_H */
diff --git a/testhal/STM32/STM32F0xx/onewire/onewire_test.c b/testhal/STM32/STM32F0xx/onewire/onewire_test.c deleted file mode 100644 index be20dbc..0000000 --- a/testhal/STM32/STM32F0xx/onewire/onewire_test.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include <string.h> - -#include "hal.h" - -/* - ****************************************************************************** - * DEFINES - ****************************************************************************** - */ - -#if defined(BOARD_ST_STM32F4_DISCOVERY) || \ - defined(BOARD_ST_STM32F0_DISCOVERY) || \ - defined(BOARD_ST_STM32F0308_DISCOVERY) - #if ONEWIRE_USE_STRONG_PULLUP - #error "This board has not enough voltage for this feature" - #endif -#endif - -#if defined(BOARD_ST_STM32F0308_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOC, GPIOC_LED4)) - #define search_led_on() (palSetPad(GPIOC, GPIOC_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_ST_STM32F4_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOD, GPIOD_LED4)) - #define search_led_on() (palSetPad(GPIOD, GPIOD_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_OLIMEX_STM32_103STK) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN 0 - #define ONEWIRE_PAD_MODE_IDLE PAL_MODE_INPUT - #define ONEWIRE_PAD_MODE_ACTIVE PAL_MODE_STM32_ALTERNATE_OPENDRAIN - #define search_led_on() (palClearPad(GPIOC, GPIOC_LED)) - #define search_led_off() (palSetPad(GPIOC, GPIOC_LED)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#else - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_TACHOMETER - #include "pads.h" - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_on red_led_on - #define search_led_off red_led_off - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#endif - -/* - ****************************************************************************** - * EXTERNS - ****************************************************************************** - */ - -/* - ****************************************************************************** - * PROTOTYPES - ****************************************************************************** - */ -/* - * Forward declarations - */ -#if ONEWIRE_USE_STRONG_PULLUP -static void strong_pullup_assert(void); -static void strong_pullup_release(void); -#endif - -/* - ****************************************************************************** - * GLOBAL VARIABLES - ****************************************************************************** - */ - -static uint8_t testbuf[12]; - -/* stores 3 temperature values in millicelsius */ -static int32_t temperature[3]; - -/* - * Config for underlied PWM driver. - * Note! It is NOT constant because 1-wire driver needs to change them - * during functioning. - */ -static PWMConfig pwm_cfg = { - 0, - 0, - NULL, - { - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL} - }, - 0, -#if STM32_PWM_USE_ADVANCED - 0, -#endif - 0 -}; - -/* - * - */ -static const onewireConfig ow_cfg = { - &PWMD3, - &pwm_cfg, - PWM_OUTPUT_ACTIVE_LOW, - ONEWIRE_MASTER_CHANNEL, - ONEWIRE_SAMPLE_CHANNEL, - ONEWIRE_PORT, - ONEWIRE_PIN, -#if defined(STM32F1XX) - ONEWIRE_PAD_MODE_IDLE, -#endif - ONEWIRE_PAD_MODE_ACTIVE, -#if ONEWIRE_USE_STRONG_PULLUP - strong_pullup_assert, - strong_pullup_release -#endif -}; - -/* - ****************************************************************************** - ****************************************************************************** - * LOCAL FUNCTIONS - ****************************************************************************** - ****************************************************************************** - */ - -#if ONEWIRE_USE_STRONG_PULLUP -/** - * - */ -static void strong_pullup_assert(void) { - palSetPadMode(ONEWIRE_PORT, ONEWIRE_PIN, PAL_MODE_STM32_ALTERNATE_PUSHPULL); -} - -/** - * - */ -static void strong_pullup_release(void) { - palSetPadMode(ONEWIRE_PORT, ONEWIRE_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); -} -#endif /* ONEWIRE_USE_STRONG_PULLUP */ - -/* - ****************************************************************************** - * EXPORTED FUNCTIONS - ****************************************************************************** - */ - -/** - * - */ -void onewireTest(void) { - - int16_t tmp; - uint8_t rombuf[24]; - size_t devices_on_bus = 0; - size_t i = 0; - bool presence; - - onewireObjectInit(&OWD1); - onewireStart(&OWD1, &ow_cfg); - -#if ONEWIRE_SYNTH_SEARCH_TEST - synthSearchRomTest(&OWD1); -#endif - - for (i=0; i<3; i++) - temperature[i] = -666; - - while (true) { - if (true == onewireReset(&OWD1)){ - - memset(rombuf, 0x55, sizeof(rombuf)); - search_led_on(); - devices_on_bus = onewireSearchRom(&OWD1, rombuf, 3); - search_led_off(); - osalDbgCheck(devices_on_bus <= 3); - osalDbgCheck(devices_on_bus > 0); - - if (1 == devices_on_bus){ - /* test read rom command */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - testbuf[0] = ONEWIRE_CMD_READ_ROM; - onewireWrite(&OWD1, testbuf, 1, 0); - onewireRead(&OWD1, testbuf, 8); - osalDbgCheck(testbuf[7] == onewireCRC(testbuf, 7)); - osalDbgCheck(0 == memcmp(rombuf, testbuf, 8)); - } - - /* start temperature measurement on all connected devices at once */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - testbuf[0] = ONEWIRE_CMD_SKIP_ROM; - testbuf[1] = ONEWIRE_CMD_CONVERT_TEMP; - -#if ONEWIRE_USE_STRONG_PULLUP - onewireWrite(&OWD1, testbuf, 2, MS2ST(750)); -#else - onewireWrite(&OWD1, testbuf, 2, 0); - /* poll bus waiting ready signal from all connected devices */ - testbuf[0] = 0; - while (testbuf[0] == 0){ - osalThreadSleepMilliseconds(50); - onewireRead(&OWD1, testbuf, 1); - } -#endif - - for (i=0; i<devices_on_bus; i++) { - /* read temperature device by device from their scratchpads */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - - testbuf[0] = ONEWIRE_CMD_MATCH_ROM; - memcpy(&testbuf[1], &rombuf[i*8], 8); - testbuf[9] = ONEWIRE_CMD_READ_SCRATCHPAD; - onewireWrite(&OWD1, testbuf, 10, 0); - - onewireRead(&OWD1, testbuf, 9); - osalDbgCheck(testbuf[8] == onewireCRC(testbuf, 8)); - memcpy(&tmp, &testbuf, 2); - temperature[i] = ((int32_t)tmp * 625) / 10; - } - } - else { - osalSysHalt("No devices found"); - } - osalThreadSleep(1); /* enforce ChibiOS's stack overflow check */ - } - - onewireStop(&OWD1); -} diff --git a/testhal/STM32/STM32F1xx/onewire/.cproject b/testhal/STM32/STM32F1xx/onewire/.cproject index 11b29ed..78e793f 100644 --- a/testhal/STM32/STM32F1xx/onewire/.cproject +++ b/testhal/STM32/STM32F1xx/onewire/.cproject @@ -52,4 +52,5 @@ </scannerConfigBuildInfo> </storageModule> <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="refreshScope"/> </cproject> diff --git a/testhal/STM32/STM32F1xx/onewire/.project b/testhal/STM32/STM32F1xx/onewire/.project index 9c1fc51..062afeb 100644 --- a/testhal/STM32/STM32F1xx/onewire/.project +++ b/testhal/STM32/STM32F1xx/onewire/.project @@ -1,6 +1,6 @@ <?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
- <name>STM32F1xx-onewire</name>
+ <name>STM32F1xx-1-Wire</name>
<comment></comment>
<projects>
</projects>
@@ -80,12 +80,18 @@ <link>
<name>os-community</name>
<type>2</type>
- <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
+ <locationURI>CHIBIOS_CONTRIB/os</locationURI>
</link>
<link>
<name>os-git</name>
<type>2</type>
- <locationURI>PARENT-5-PROJECT_LOC/ChibiOS-RT/os</locationURI>
+ <locationURI>copy_PARENT/ChibiOS-RT/os</locationURI>
</link>
</linkedResources>
+ <variableList>
+ <variable>
+ <name>copy_PARENT</name>
+ <value>$%7BPARENT-1-CHIBIOS%7D</value>
+ </variable>
+ </variableList>
</projectDescription>
diff --git a/testhal/STM32/STM32F1xx/onewire/Makefile b/testhal/STM32/STM32F1xx/onewire/Makefile index d2e25b1..e9d4238 100644 --- a/testhal/STM32/STM32F1xx/onewire/Makefile +++ b/testhal/STM32/STM32F1xx/onewire/Makefile @@ -82,6 +82,7 @@ PROJECT = ch # Imported source files and paths
CHIBIOS = ../../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+TESTHAL = $(CHIBIOS_CONTRIB)/testhal/common/onewire
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk
# HAL-OSAL files (optional).
@@ -109,7 +110,7 @@ CSRC = $(STARTUPSRC) \ $(BOARDSRC) \
$(TESTSRC) \
main.c \
- onewire_test.c
+ $(TESTHAL)/testhal_onewire.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -142,7 +143,8 @@ ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) INCDIR = $(CHIBIOS)/os/license \
$(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
- $(CHIBIOS)/os/various
+ $(CHIBIOS)/os/various \
+ $(TESTHAL)
#
# Project, sources and paths
diff --git a/testhal/STM32/STM32F1xx/onewire/boarddef.h b/testhal/STM32/STM32F1xx/onewire/boarddef.h new file mode 100644 index 0000000..2b1b466 --- /dev/null +++ b/testhal/STM32/STM32F1xx/onewire/boarddef.h @@ -0,0 +1,29 @@ +/* + ChibiOS/RT - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef BOARDDEF_H_ +#define BOARDDEF_H_ + +#define ONEWIRE_PORT GPIOB +#define ONEWIRE_PIN 0 +#define ONEWIRE_PAD_MODE_IDLE PAL_MODE_INPUT +#define ONEWIRE_PAD_MODE_ACTIVE PAL_MODE_STM32_ALTERNATE_OPENDRAIN +#define search_led_on() (palClearPad(GPIOC, GPIOC_LED)) +#define search_led_off() (palSetPad(GPIOC, GPIOC_LED)) +#define ONEWIRE_MASTER_CHANNEL 2 +#define ONEWIRE_SAMPLE_CHANNEL 3 + +#endif /* BOARDDEF_H_ */ diff --git a/testhal/STM32/STM32F1xx/onewire/halconf.h b/testhal/STM32/STM32F1xx/onewire/halconf.h index e6ce929..64811a5 100644 --- a/testhal/STM32/STM32F1xx/onewire/halconf.h +++ b/testhal/STM32/STM32F1xx/onewire/halconf.h @@ -1,5 +1,5 @@ /*
- ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -25,8 +25,8 @@ * @{
*/
-#ifndef _HALCONF_H_
-#define _HALCONF_H_
+#ifndef HALCONF_H
+#define HALCONF_H
#include "mcuconf.h"
@@ -45,17 +45,17 @@ #endif
/**
- * @brief Enables the DAC subsystem.
+ * @brief Enables the CAN subsystem.
*/
-#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
-#define HAL_USE_DAC FALSE
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
#endif
/**
- * @brief Enables the CAN subsystem.
+ * @brief Enables the DAC subsystem.
*/
-#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
-#define HAL_USE_CAN FALSE
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
#endif
/**
@@ -294,7 +294,7 @@ * @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
- * @note The default is 64 bytes for both the transmission and receive
+ * @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
@@ -309,13 +309,21 @@ * @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
- * @note The default is 64 bytes for both the transmission and receive
+ * @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
+/**
+ * @brief Serial over USB number of buffers.
+ * @note The default is 2 buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_NUMBER 2
+#endif
+
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
@@ -337,11 +345,43 @@ #endif
/*===========================================================================*/
+/* UART driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
+#define UART_USE_WAIT FALSE
+#endif
+
+/**
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define UART_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+/*===========================================================================*/
/* Community drivers's includes */
/*===========================================================================*/
#include "halconf_community.h"
-#endif /* _HALCONF_H_ */
+#endif /* HALCONF_H */
/** @} */
diff --git a/testhal/STM32/STM32F1xx/onewire/halconf_community.h b/testhal/STM32/STM32F1xx/onewire/halconf_community.h index 91dbfbc..0621fdb 100644 --- a/testhal/STM32/STM32F1xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F1xx/onewire/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _HALCONF_COMMUNITY_H_
-#define _HALCONF_COMMUNITY_H_
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
@@ -93,6 +93,6 @@ */
#define ONEWIRE_USE_SEARCH_ROM TRUE
-#endif /* _HALCONF_COMMUNITY_H_ */
+#endif /* HALCONF_COMMUNITY_H */
/** @} */
diff --git a/testhal/STM32/STM32F1xx/onewire/main.c b/testhal/STM32/STM32F1xx/onewire/main.c index 793bffe..5265edc 100644 --- a/testhal/STM32/STM32F1xx/onewire/main.c +++ b/testhal/STM32/STM32F1xx/onewire/main.c @@ -17,7 +17,7 @@ #include "ch.h"
#include "hal.h"
-#include "onewire_test.h"
+#include "testhal_onewire.h"
/*
* Application entry point.
diff --git a/testhal/STM32/STM32F1xx/onewire/real_roms.txt b/testhal/STM32/STM32F1xx/onewire/real_roms.txt deleted file mode 100644 index ea19c1a..0000000 --- a/testhal/STM32/STM32F1xx/onewire/real_roms.txt +++ /dev/null @@ -1,27 +0,0 @@ -rombuf[0] 0x28 -rombuf[1] 0xec -rombuf[2] 0xf5 -rombuf[3] 0x67 -rombuf[4] 0x5 -rombuf[5] 0x0 -rombuf[6] 0x0 -rombuf[7] 0x1d - -rombuf[8] 0x28 -rombuf[9] 0xbd -rombuf[10] 0x1a -rombuf[11] 0x60 -rombuf[12] 0x5 -rombuf[13] 0x0 -rombuf[14] 0x0 -rombuf[15] 0x37 - -rombuf[16] 0x28 -rombuf[17] 0x83 -rombuf[18] 0x7d -rombuf[19] 0x67 -rombuf[20] 0x5 -rombuf[21] 0x0 -rombuf[22] 0x0 -rombuf[23] 0xf - diff --git a/testhal/STM32/STM32F1xx/onewire/search_rom_synth.c b/testhal/STM32/STM32F1xx/onewire/search_rom_synth.c deleted file mode 100644 index cd2528f..0000000 --- a/testhal/STM32/STM32F1xx/onewire/search_rom_synth.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include <stdlib.h> - -/* - ****************************************************************************** - * DEFINES - ****************************************************************************** - */ - -/* do not set it more than 64 because of some fill_pattern functions - * will be broken.*/ -#define SYNTH_DEVICES_MAX 64 - -/* - * synthetic device - */ -typedef struct { - bool active; - uint64_t id; -} OWSynthDevice; - -/* - * synthetic bus - */ -typedef struct { - OWSynthDevice devices[SYNTH_DEVICES_MAX]; - size_t dev_present; - bool complement_bit; - ioline_t rom_bit; -} OWSynthBus; - -/* - ****************************************************************************** - * EXTERNS - ****************************************************************************** - */ - -/* - ****************************************************************************** - * PROTOTYPES - ****************************************************************************** - */ - -/* - ****************************************************************************** - * GLOBAL VARIABLES - ****************************************************************************** - */ - -static OWSynthBus synth_bus; - -/* - * local buffer for discovered ROMs - */ -static uint64_t detected_devices[SYNTH_DEVICES_MAX]; - -/* - ****************************************************************************** - ****************************************************************************** - * LOCAL FUNCTIONS - ****************************************************************************** - ****************************************************************************** - */ - -/* - ****************************************************************************** - * EXPORTED FUNCTIONS - ****************************************************************************** - */ - -/** - * - */ -void _synth_ow_write_bit(onewireDriver *owp, ioline_t bit) { - (void)owp; - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) { - if (((synth_bus.devices[i].id >> synth_bus.rom_bit) & 1U) != bit) { - synth_bus.devices[i].active = false; - } - } - synth_bus.rom_bit++; -} - -/** - * - */ -ioline_t _synth_ow_read_bit(void) { - ioline_t ret = 0xFF; - size_t i; - ioline_t bit; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) { - if (synth_bus.devices[i].active){ - bit = (synth_bus.devices[i].id >> synth_bus.rom_bit) & 1U; - if (synth_bus.complement_bit){ - bit ^= 1U; - } - if (0xFF == ret) - ret = bit; - else - ret &= bit; - } - } - synth_bus.complement_bit = !synth_bus.complement_bit; - return ret; -} - -/** - * - */ -static void synth_reset_pulse(void){ - size_t i; - - for (i=0; i<synth_bus.dev_present; i++){ - synth_bus.devices[i].active = true; - } -} - -/** - * - */ -static size_t synth_search_rom(onewireDriver *owp, uint8_t *result, size_t max_rom_cnt) { - - size_t i; - - search_clean_start(&owp->search_rom); - - do { - /* initialize buffer to store result */ - if (owp->search_rom.reg.devices_found >= max_rom_cnt) - owp->search_rom.retbuf = result + 8*(max_rom_cnt-1); - else - owp->search_rom.retbuf = result + 8*owp->search_rom.reg.devices_found; - memset(owp->search_rom.retbuf, 0, 8); - - /* clean iteration state */ - search_clean_iteration(&owp->search_rom); - - /**/ - synth_reset_pulse(); - synth_bus.rom_bit = 0; - synth_bus.complement_bit = false; - for (i=0; i<64*3 - 1; i++){ - ow_search_rom_cb(NULL, owp); - } - - if (ONEWIRE_SEARCH_ROM_ERROR != owp->search_rom.reg.result) { - /* store cached result for usage in next iteration */ - memcpy(owp->search_rom.prev_path, owp->search_rom.retbuf, 8); - } - } - while (ONEWIRE_SEARCH_ROM_SUCCESS == owp->search_rom.reg.result); - - /**/ - if (ONEWIRE_SEARCH_ROM_ERROR == owp->search_rom.reg.result) - return 0; - else - return owp->search_rom.reg.devices_found; -} - -/** - * - */ -static void fill_pattern_real_devices(void) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - synth_bus.devices[0].active = true; - synth_bus.devices[0].id = 0x1d00000567f5ec28; - - synth_bus.devices[1].active = true; - synth_bus.devices[1].id = 0x37000005601abd28; - - synth_bus.devices[2].active = true; - synth_bus.devices[2].id = 0x0f000005677d8328; -} - -/** - * - */ -static void fill_pattern_00(size_t devices, size_t start) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = (start + i); - } -} - -/** - * - */ -static void fill_pattern_01(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = (devices - i); - } -} - -/** - * - */ -static void fill_pattern_02(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = ((uint64_t)1 << i); - } -} - -/** - * - */ -static void fill_pattern_03(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = ((uint64_t)0x8000000000000000 >> i); - } -} - -/** - * @brief random pattern helper - */ -static bool is_id_uniq(const OWSynthDevice *dev, size_t n, uint64_t id) { - size_t i; - - for (i=0; i<n; i++) { - if (dev[i].id == id) - return false; - } - return true; -} - -/** - * - */ -static void fill_pattern_rand(size_t devices) { - size_t i; - uint64_t new_id; - - for (i=0; i<SYNTH_DEVICES_MAX; i++){ - synth_bus.devices[i].active = false; - synth_bus.devices[i].id = 0; - } - - for (i=0; i<devices; i++) { - do { - new_id = rand(); - new_id = (new_id << 32) | rand(); - } while (true != is_id_uniq(synth_bus.devices, i, new_id)); - - synth_bus.devices[i].id = new_id; - synth_bus.devices[i].active = true; - } -} - -/** - * - */ -static bool check_result(size_t detected) { - - size_t i,j; - bool match = false; - - for (i=0; i<detected; i++){ - match = false; - for (j=0; j<detected; j++){ - if (synth_bus.devices[i].id == detected_devices[j]){ - match = true; - break; - } - } - if (false == match) - return OSAL_FAILED; - } - return OSAL_SUCCESS; -} - -/** - * - */ -void synthSearchRomTest(onewireDriver *owp) { - - size_t detected = 0; - size_t i; - - synth_bus.dev_present = 3; - fill_pattern_real_devices(); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - for (i=1; i<=SYNTH_DEVICES_MAX; i++){ - synth_bus.dev_present = i; - - fill_pattern_00(synth_bus.dev_present, 0); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_00(synth_bus.dev_present, 1); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_01(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_02(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_03(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - } - - i = 0; - while (i < 1000) { - synth_bus.dev_present = 1 + (rand() & 63); - - fill_pattern_rand(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - i++; - } -} - - diff --git a/testhal/STM32/STM32F3xx/EEProm/halconf.h b/testhal/STM32/STM32F3xx/EEProm/halconf.h index 42c228e..53edc1b 100644 --- a/testhal/STM32/STM32F3xx/EEProm/halconf.h +++ b/testhal/STM32/STM32F3xx/EEProm/halconf.h @@ -1,5 +1,5 @@ /*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -25,8 +25,8 @@ * @{
*/
-#ifndef _HALCONF_H_
-#define _HALCONF_H_
+#ifndef HALCONF_H
+#define HALCONF_H
#include "mcuconf.h"
@@ -382,6 +382,6 @@ #include "halconf_community.h"
-#endif /* _HALCONF_H_ */
+#endif /* HALCONF_H */
/** @} */
diff --git a/testhal/STM32/STM32F3xx/EEProm/halconf_community.h b/testhal/STM32/STM32F3xx/EEProm/halconf_community.h index 3916efb..f0814c6 100644 --- a/testhal/STM32/STM32F3xx/EEProm/halconf_community.h +++ b/testhal/STM32/STM32F3xx/EEProm/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _HALCONF_COMMUNITY_H_
-#define _HALCONF_COMMUNITY_H_
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
@@ -100,7 +100,7 @@ */
#define ONEWIRE_USE_SEARCH_ROM TRUE
- /*===========================================================================*/
+/*===========================================================================*/
/* EEProm driver related settings. */
/*===========================================================================*/
@@ -109,13 +109,12 @@ * @note Disabling this option saves both code and data space.
*/
#define EEPROM_USE_EE24XX TRUE
- /**
+/**
* @brief Enables 25xx series SPI eeprom device driver.
* @note Disabling this option saves both code and data space.
*/
#define EEPROM_USE_EE25XX TRUE
-
-#endif /* _HALCONF_COMMUNITY_H_ */
+#endif /* HALCONF_COMMUNITY_H */
/** @} */
diff --git a/testhal/STM32/STM32F3xx/EEProm/mcuconf.h b/testhal/STM32/STM32F3xx/EEProm/mcuconf.h index 60b9854..badcd95 100644 --- a/testhal/STM32/STM32F3xx/EEProm/mcuconf.h +++ b/testhal/STM32/STM32F3xx/EEProm/mcuconf.h @@ -1,5 +1,5 @@ /*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _MCUCONF_H_
-#define _MCUCONF_H_
+#ifndef MCUCONF_H
+#define MCUCONF_H
/*
* STM32F3xx drivers configuration.
@@ -255,4 +255,4 @@ */
#include "mcuconf_community.h"
-#endif /* _MCUCONF_H_ */
+#endif /* MCUCONF_H */
diff --git a/testhal/STM32/STM32F3xx/TIMCAP/halconf.h b/testhal/STM32/STM32F3xx/TIMCAP/halconf.h index 9af6aca..93cc713 100644 --- a/testhal/STM32/STM32F3xx/TIMCAP/halconf.h +++ b/testhal/STM32/STM32F3xx/TIMCAP/halconf.h @@ -1,5 +1,5 @@ /*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -25,8 +25,8 @@ * @{
*/
-#ifndef _HALCONF_H_
-#define _HALCONF_H_
+#ifndef HALCONF_H
+#define HALCONF_H
#include "mcuconf.h"
@@ -382,6 +382,6 @@ #include "halconf_community.h"
-#endif /* _HALCONF_H_ */
+#endif /* HALCONF_H */
/** @} */
diff --git a/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h b/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h index 998080e..40070e6 100644 --- a/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h +++ b/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _HALCONF_COMMUNITY_H_
-#define _HALCONF_COMMUNITY_H_
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
@@ -107,7 +107,7 @@ */
#define ONEWIRE_USE_SEARCH_ROM TRUE
- /*===========================================================================*/
+/*===========================================================================*/
/* EEProm driver related settings. */
/*===========================================================================*/
@@ -122,7 +122,6 @@ */
#define EEPROM_USE_EE25XX TRUE
-
-#endif /* _HALCONF_COMMUNITY_H_ */
+#endif /* HALCONF_COMMUNITY_H */
/** @} */
diff --git a/testhal/STM32/STM32F3xx/TIMCAP/mcuconf.h b/testhal/STM32/STM32F3xx/TIMCAP/mcuconf.h index 60b9854..badcd95 100644 --- a/testhal/STM32/STM32F3xx/TIMCAP/mcuconf.h +++ b/testhal/STM32/STM32F3xx/TIMCAP/mcuconf.h @@ -1,5 +1,5 @@ /*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _MCUCONF_H_
-#define _MCUCONF_H_
+#ifndef MCUCONF_H
+#define MCUCONF_H
/*
* STM32F3xx drivers configuration.
@@ -255,4 +255,4 @@ */
#include "mcuconf_community.h"
-#endif /* _MCUCONF_H_ */
+#endif /* MCUCONF_H */
diff --git a/testhal/STM32/STM32F4xx/EICU/halconf_community.h b/testhal/STM32/STM32F4xx/EICU/halconf_community.h index e967c6a..42c8c5d 100644 --- a/testhal/STM32/STM32F4xx/EICU/halconf_community.h +++ b/testhal/STM32/STM32F4xx/EICU/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _HALCONF_COMMUNITY_H_
-#define _HALCONF_COMMUNITY_H_
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
@@ -93,6 +93,6 @@ */
#define ONEWIRE_USE_SEARCH_ROM FALSE
-#endif /* _HALCONF_COMMUNITY_H_ */
+#endif /* HALCONF_COMMUNITY_H */
/** @} */
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<scannerConfigBuildInfo instanceId="0.1570569554"> + <scannerConfigBuildInfo instanceId="0.114656749"> <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/> </scannerConfigBuildInfo> - <scannerConfigBuildInfo instanceId="0.1641850078"> - <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> - </scannerConfigBuildInfo> </storageModule> <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="refreshScope"/> </cproject> diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c index e36fbc9..3c60484 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c @@ -53,6 +53,7 @@ static const SPIConfig spicfg = { GPIOA, GPIOA_SPI1_NSS, 0, //SPI_CR1_BR_1 | SPI_CR1_BR_0 + 0 }; static uint32_t ints; diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h index e690d15..dbc1950 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h @@ -62,7 +62,7 @@ * @brief Enables the EXT subsystem. */ #if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT TRUE +#define HAL_USE_EXT FALSE #endif /** diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h index f480707..acbf837 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _HALCONF_COMMUNITY_H_
-#define _HALCONF_COMMUNITY_H_
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
@@ -93,6 +93,6 @@ */
#define ONEWIRE_USE_SEARCH_ROM TRUE
-#endif /* _HALCONF_COMMUNITY_H_ */
+#endif /* HALCONF_COMMUNITY_H */
/** @} */
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c index 2379a12..e75a937 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c @@ -56,8 +56,6 @@ ****************************************************************************** */ -#define USE_BAD_MAP TRUE - #define USE_KILL_BLOCK_TEST FALSE #define FSMCNAND_TIME_SET ((uint32_t) 2) //(8nS) @@ -74,7 +72,7 @@ #define NAND_COL_WRITE_CYCLES 2 #define NAND_TEST_START_BLOCK 1200 -#define NAND_TEST_END_BLOCK 1220 +#define NAND_TEST_END_BLOCK 1300 #if USE_KILL_BLOCK_TEST #define NAND_TEST_KILL_BLOCK 8000 @@ -88,6 +86,8 @@ #error "You should enable at least one NAND interface" #endif +#define BAD_MAP_LEN (NAND_BLOCKS_COUNT / (sizeof(bitmap_word_t) * 8)) + /* ****************************************************************************** * EXTERNS @@ -99,11 +99,6 @@ * PROTOTYPES ****************************************************************************** */ -#if STM32_NAND_USE_EXT_INT -static void ready_isr_enable(void); -static void ready_isr_disable(void); -static void nand_ready_cb(EXTDriver *extp, expchannel_t channel); -#endif /* ****************************************************************************** @@ -126,14 +121,14 @@ static time_measurement_t tmu_read_data; static time_measurement_t tmu_read_spare; static time_measurement_t tmu_driver_start; -#if USE_BAD_MAP -#define BAD_MAP_LEN (NAND_BLOCKS_COUNT / (sizeof(bitmap_word_t) * 8)) -static bitmap_word_t badblock_map_array[BAD_MAP_LEN]; +/* + * + */ +static bitmap_word_t badblock_map_array[BAD_MAP_LEN]; static bitmap_t badblock_map = { badblock_map_array, BAD_MAP_LEN }; -#endif /* * @@ -147,47 +142,11 @@ static const NANDConfig nandcfg = { NAND_COL_WRITE_CYCLES, /* stm32 specific fields */ ((FSMCNAND_TIME_HIZ << 24) | (FSMCNAND_TIME_HOLD << 16) | \ - (FSMCNAND_TIME_WAIT << 8) | FSMCNAND_TIME_SET), -#if STM32_NAND_USE_EXT_INT - ready_isr_enable, - ready_isr_disable -#endif + (FSMCNAND_TIME_WAIT << 8) | FSMCNAND_TIME_SET) }; -/** - * - */ -#if STM32_NAND_USE_EXT_INT -static const EXTConfig extcfg = { - { - {EXT_CH_MODE_DISABLED, NULL}, //0 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, //4 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_RISING_EDGE | EXT_MODE_GPIOD, nand_ready_cb}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, //8 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, //12 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, //16 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, //20 - {EXT_CH_MODE_DISABLED, NULL}, - {EXT_CH_MODE_DISABLED, NULL}, - } -}; -#endif /* STM32_NAND_USE_EXT_INT */ - static volatile uint32_t BackgroundThdCnt = 0; +static thread_reference_t background_thd_ptr = NULL; #if USE_KILL_BLOCK_TEST static uint32_t KillCycle = 0; @@ -202,25 +161,10 @@ static uint32_t KillCycle = 0; */ static void nand_wp_assert(void) {palClearPad(GPIOB, GPIOB_NAND_WP);} static void nand_wp_release(void) {palSetPad(GPIOB, GPIOB_NAND_WP);} -static void red_led_on(void) {palSetPad(GPIOI, GPIOI_LED_R);} +//static void red_led_on(void) {palSetPad(GPIOI, GPIOI_LED_R);} static void red_led_off(void) {palClearPad(GPIOI, GPIOI_LED_R);} - -#if STM32_NAND_USE_EXT_INT -static void nand_ready_cb(EXTDriver *extp, expchannel_t channel){ - (void)extp; - (void)channel; - - NAND.isr_handler(&NAND); -} - -static void ready_isr_enable(void) { - extChannelEnable(&EXTD1, GPIOD_NAND_RB_NWAIT); -} - -static void ready_isr_disable(void) { - extChannelDisable(&EXTD1, GPIOD_NAND_RB_NWAIT); -} -#endif /* STM32_NAND_USE_EXT_INT */ +static void red_led_toggle(void) {palTogglePad(GPIOI, GPIOI_LED_R);} +static void green_led_toggle(void) {palTogglePad(GPIOI, GPIOI_LED_G);} /** * @@ -467,8 +411,6 @@ static void general_test (NANDDriver *nandp, size_t first, uint8_t op_status; uint32_t recc, wecc; - red_led_on(); - /* initialize time measurement units */ chTMObjectInit(&tmu_erase); chTMObjectInit(&tmu_write_data); @@ -478,16 +420,38 @@ static void general_test (NANDDriver *nandp, size_t first, /* perform basic checks */ for (block=first; block<last; block++){ + red_led_toggle(); + if (!nandIsBad(nandp, block)){ + if (!is_erased(nandp, block)){ + op_status = nandErase(nandp, block); + osalDbgCheck(0 == (op_status & 1)); /* operation failed */ + } + } + } + + /* check fail status */ + for (block=first; block<last; block++){ if (!nandIsBad(nandp, block)){ if (!is_erased(nandp, block)){ op_status = nandErase(nandp, block); osalDbgCheck(0 == (op_status & 1)); /* operation failed */ } + pattern_fill(); + op_status = nandWritePageData(nandp, block, 0, + nand_buf, nandp->config->page_data_size, &wecc); + osalDbgCheck(0 == (op_status & 1)); + + pattern_fill(); + op_status = nandWritePageData(nandp, block, 0, + nand_buf, nandp->config->page_data_size, &wecc); + /* operation must failed here because of write in unerased space */ + osalDbgCheck(1 == (op_status & 1)); } } /* write block with pattern, read it back and compare */ for (block=first; block<last; block++){ + red_led_toggle(); if (!nandIsBad(nandp, block)){ for (page=0; page<nandp->config->pages_per_block; page++){ pattern_fill(); @@ -538,17 +502,10 @@ static void general_test (NANDDriver *nandp, size_t first, red_led_off(); } - /* - ****************************************************************************** - * EXPORTED FUNCTIONS - ****************************************************************************** - */ - -/* - * Application entry point. + * */ -int main(void) { +static void nand_test(bool use_badblock_map) { /* performance counters */ int32_t adc_ints = 0; @@ -560,40 +517,26 @@ int main(void) { uint32_t background_cnt = 0; systime_t T = 0; - /* - * System initializations. - * - HAL initialization, this also initializes the configured device drivers - * and performs the board-specific initializations. - * - Kernel initialization, the main() function becomes a thread and the - * RTOS is active. - */ - halInit(); - chSysInit(); - -#if STM32_NAND_USE_EXT_INT - extStart(&EXTD1, &extcfg); -#endif chTMObjectInit(&tmu_driver_start); chTMStartMeasurementX(&tmu_driver_start); -#if USE_BAD_MAP - nandStart(&NAND, &nandcfg, &badblock_map); -#else - nandStart(&NAND, &nandcfg, NULL); -#endif + if (use_badblock_map) { + nandStart(&NAND, &nandcfg, &badblock_map); + } + else { + nandStart(&NAND, &nandcfg, NULL); + } chTMStopMeasurementX(&tmu_driver_start); chThdSleepMilliseconds(4000); - chThdCreateStatic(BackgroundThreadWA, - sizeof(BackgroundThreadWA), - NORMALPRIO - 20, - BackgroundThread, - NULL); - - nand_wp_release(); + BackgroundThdCnt = 0; + if (NULL != background_thd_ptr) { + background_thd_ptr = chThdCreateStatic(BackgroundThreadWA, + sizeof(BackgroundThreadWA), NORMALPRIO - 10, BackgroundThread, NULL); + } /* - * run NAND test in parallel with DMA load and background thread + * run NAND test in parallel with DMA loads and background thread */ dma_storm_adc_start(); dma_storm_uart_start(); @@ -601,9 +544,9 @@ int main(void) { T = chVTGetSystemTimeX(); general_test(&NAND, NAND_TEST_START_BLOCK, NAND_TEST_END_BLOCK, 1); T = chVTGetSystemTimeX() - T; - adc_ints = dma_storm_adc_stop(); + adc_ints = dma_storm_adc_stop(); uart_ints = dma_storm_uart_stop(); - spi_ints = dma_storm_spi_stop(); + spi_ints = dma_storm_spi_stop(); chSysLock(); background_cnt = BackgroundThdCnt; BackgroundThdCnt = 0; @@ -632,6 +575,35 @@ int main(void) { * perform ECC calculation test */ ecc_test(&NAND, NAND_TEST_END_BLOCK); +} + +/* + ****************************************************************************** + * EXPORTED FUNCTIONS + ****************************************************************************** + */ + +/* + * Application entry point. + */ +int main(void) { + + + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + nand_wp_release(); + + nand_test(true); + nand_test(false); #if USE_KILL_BLOCK_TEST kill_block(&NAND, NAND_TEST_KILL_BLOCK); @@ -642,7 +614,9 @@ int main(void) { /* * Normal main() thread activity, in this demo it does nothing. */ + red_led_off(); while (true) { + green_led_toggle(); chThdSleepMilliseconds(500); } } diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h index 9638dbe..dd72e66 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h @@ -26,7 +26,6 @@ */ #define STM32_NAND_USE_FSMC_NAND1 TRUE #define STM32_NAND_USE_FSMC_NAND2 FALSE -#define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 #define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h index 606fed4..060481a 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _HALCONF_COMMUNITY_H_
-#define _HALCONF_COMMUNITY_H_
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
@@ -93,6 +93,6 @@ */
#define ONEWIRE_USE_SEARCH_ROM TRUE
-#endif /* _HALCONF_COMMUNITY_H_ */
+#endif /* HALCONF_COMMUNITY_H */
/** @} */
diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h index 606fed4..060481a 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _HALCONF_COMMUNITY_H_
-#define _HALCONF_COMMUNITY_H_
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
@@ -93,6 +93,6 @@ */
#define ONEWIRE_USE_SEARCH_ROM TRUE
-#endif /* _HALCONF_COMMUNITY_H_ */
+#endif /* HALCONF_COMMUNITY_H */
/** @} */
diff --git a/testhal/STM32/STM32F4xx/USB_HOST/Makefile b/testhal/STM32/STM32F4xx/USB_HOST/Makefile index 4946cba..0174baf 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/Makefile +++ b/testhal/STM32/STM32F4xx/USB_HOST/Makefile @@ -46,7 +46,7 @@ endif # If enabled, this option makes the build process faster by not compiling
# modules not used in the current configuration.
ifeq ($(USE_SMART_BUILD),)
- USE_SMART_BUILD = no
+ USE_SMART_BUILD = yes
endif
#
@@ -105,7 +105,7 @@ include $(CHIBIOS)/os/various/shell/shell.mk include $(CHIBIOS)/os/various/fatfs_bindings/fatfs.mk
# Define linker script file here
-LDSCRIPT = $(STARTUPLD)/STM32F407xG.ld
+LDSCRIPT= $(STARTUPLD)/STM32F407xG.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
diff --git a/testhal/STM32/STM32F4xx/USB_HOST/fatfs_diskio.c b/testhal/STM32/STM32F4xx/USB_HOST/fatfs_diskio.c index 98a7edf..41e3553 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/fatfs_diskio.c +++ b/testhal/STM32/STM32F4xx/USB_HOST/fatfs_diskio.c @@ -9,7 +9,6 @@ #include "ffconf.h"
#include "diskio.h"
-#include "usbh.h"
#include "usbh/dev/msd.h"
/*-----------------------------------------------------------------------*/
diff --git a/testhal/STM32/STM32F4xx/USB_HOST/ff.c b/testhal/STM32/STM32F4xx/USB_HOST/ff.c index 45e20ce..2edbe32 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/ff.c +++ b/testhal/STM32/STM32F4xx/USB_HOST/ff.c @@ -1,5 +1,5 @@ /*----------------------------------------------------------------------------/
-/ FatFs - FAT file system module R0.10c (C)ChaN, 2014
+/ FatFs - FAT file system module R0.10b (C)ChaN, 2014
/-----------------------------------------------------------------------------/
/ FatFs module is a generic FAT file system module for small embedded systems.
/ This is a free software that opened for education, research and commercial
@@ -113,10 +113,6 @@ / Fixed creation of an entry with LFN fails on too many SFN collisions.
/ May 19,'14 R0.10b Fixed a hard error in the disk I/O layer can collapse the directory entry.
/ Fixed LFN entry is not deleted on delete/rename an object with lossy converted SFN.
-/ Nov 09,'14 R0.10c Added a configuration option for the platforms without RTC. (_FS_NORTC)
-/ Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel().
-/ Fixed a potential problem of FAT access that can appear on disk error.
-/ Fixed null pointer dereference on attempting to delete the root direcotry.
/---------------------------------------------------------------------------*/
#include "ff.h" /* Declarations of FatFs API */
@@ -131,7 +127,7 @@ ---------------------------------------------------------------------------*/
-#if _FATFS != 80376 /* Revision ID */
+#if _FATFS != 8051 /* Revision ID */
#error Wrong include file (ff.h).
#endif
@@ -139,7 +135,7 @@ /* Reentrancy related */
#if _FS_REENTRANT
#if _USE_LFN == 1
-#error Static LFN work area cannot be used at thread-safe configuration
+#error Static LFN work area cannot be used at thread-safe configuration.
#endif
#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; }
#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; }
@@ -153,7 +149,7 @@ /* Definitions of sector size */
#if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096) || (_MIN_SS != 512 && _MIN_SS != 1024 && _MIN_SS != 2048 && _MIN_SS != 4096)
-#error Wrong sector size configuration
+#error Wrong sector size configuration.
#endif
#if _MAX_SS == _MIN_SS
#define SS(fs) ((UINT)_MAX_SS) /* Fixed sector size */
@@ -162,21 +158,10 @@ #endif
-/* Timestamp feature */
-#if _FS_NORTC == 1
-#if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < 1 || _NORTC_MDAY > 31
-#error Invalid _FS_NORTC settings
-#endif
-#define GET_FATTIME() ((DWORD)(_NORTC_YEAR - 1980) << 25 | (DWORD)_NORTC_MON << 21 | (DWORD)_NORTC_MDAY << 16)
-#else
-#define GET_FATTIME() get_fattime()
-#endif
-
-
/* File access control feature */
#if _FS_LOCK
#if _FS_READONLY
-#error _FS_LOCK must be 0 at read-only configuration
+#error _FS_LOCK must be 0 at read-only cfg.
#endif
typedef struct {
FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */
@@ -413,7 +398,7 @@ typedef struct { /* Name status flags */
-#define NSFLAG 11 /* Index of name status byte in fn[] */
+#define NS 11 /* Index of name status byte in fn[] */
#define NS_LOSS 0x01 /* Out of 8.3 format */
#define NS_LFN 0x02 /* Force to create LFN entry */
#define NS_LAST 0x04 /* Last segment */
@@ -422,16 +407,16 @@ typedef struct { #define NS_DOT 0x20 /* Dot entry */
-/* FAT sub-type boundaries (Differ from specs but correct for real DOS/Windows) */
-#define MIN_FAT16 4086U /* Minimum number of clusters as FAT16 */
-#define MIN_FAT32 65526U /* Minimum number of clusters as FAT32 */
+/* FAT sub-type boundaries */
+#define MIN_FAT16 4086U /* Minimum number of clusters for FAT16 */
+#define MIN_FAT32 65526U /* Minimum number of clusters for FAT32 */
/* FatFs refers the members in the FAT structures as byte array instead of
/ structure member because the structure is not binary compatible between
/ different platforms */
-#define BS_jmpBoot 0 /* x86 jump instruction (3) */
+#define BS_jmpBoot 0 /* Jump instruction (3) */
#define BS_OEMName 3 /* OEM name (8) */
#define BPB_BytsPerSec 11 /* Sector size [byte] (2) */
#define BPB_SecPerClus 13 /* Cluster size [sector] (1) */
@@ -497,53 +482,63 @@ typedef struct { /*------------------------------------------------------------*/
/* Module private work area */
/*------------------------------------------------------------*/
-/* Remark: Uninitialized variables with static duration are
-/ guaranteed zero/null at start-up. If not, either the linker
-/ or start-up routine being used is out of ANSI-C standard.
+/* Note that uninitialized variables with static duration are
+/ guaranteed zero/null as initial value. If not, either the
+/ linker or start-up routine is out of ANSI-C standard.
*/
-#if _VOLUMES < 1 || _VOLUMES > 9
-#error Wrong _VOLUMES setting
+#if _VOLUMES >= 1 || _VOLUMES <= 10
+static
+FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */
+#else
+#error Number of volumes must be 1 to 10.
#endif
-static FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */
-static WORD Fsid; /* File system mount ID */
+
+static
+WORD Fsid; /* File system mount ID */
#if _FS_RPATH && _VOLUMES >= 2
-static BYTE CurrVol; /* Current drive */
+static
+BYTE CurrVol; /* Current drive */
#endif
#if _FS_LOCK
-static FILESEM Files[_FS_LOCK]; /* Open object lock semaphores */
+static
+FILESEM Files[_FS_LOCK]; /* Open object lock semaphores */
#endif
-#if _USE_LFN == 0 /* Non LFN feature */
+#if _USE_LFN == 0 /* No LFN feature */
#define DEF_NAMEBUF BYTE sfn[12]
#define INIT_BUF(dobj) (dobj).fn = sfn
#define FREE_BUF()
-#else
-#if _MAX_LFN < 12 || _MAX_LFN > 255
-#error Wrong _MAX_LFN setting
-#endif
-#if _USE_LFN == 1 /* LFN feature with static working buffer */
-static WCHAR LfnBuf[_MAX_LFN+1];
+
+#elif _USE_LFN == 1 /* LFN feature with static working buffer */
+static
+WCHAR LfnBuf[_MAX_LFN+1];
#define DEF_NAMEBUF BYTE sfn[12]
#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; }
#define FREE_BUF()
+
#elif _USE_LFN == 2 /* LFN feature with dynamic working buffer on the stack */
#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1]
#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; }
#define FREE_BUF()
+
#elif _USE_LFN == 3 /* LFN feature with dynamic working buffer on the heap */
#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn
-#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); (dobj).lfn = lfn; (dobj).fn = sfn; }
+#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \
+ if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \
+ (dobj).lfn = lfn; (dobj).fn = sfn; }
#define FREE_BUF() ff_memfree(lfn)
+
#else
-#error Wrong _USE_LFN setting
-#endif
+#error Wrong LFN configuration.
#endif
+
#ifdef _EXCVT
-static const BYTE ExCvt[] = _EXCVT; /* Upper conversion table for extended characters */
+static
+const BYTE ExCvt[] = _EXCVT; /* Upper conversion table for extended characters */
#endif
@@ -763,24 +758,21 @@ FRESULT sync_window ( {
DWORD wsect;
UINT nf;
- FRESULT res = FR_OK;
if (fs->wflag) { /* Write back the sector if it is dirty */
wsect = fs->winsect; /* Current sector number */
- if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) {
- res = FR_DISK_ERR;
- } else {
- fs->wflag = 0;
- if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */
- for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */
- wsect += fs->fsize;
- disk_write(fs->drv, fs->win, wsect, 1);
- }
+ if (disk_write(fs->drv, fs->win, wsect, 1))
+ return FR_DISK_ERR;
+ fs->wflag = 0;
+ if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */
+ for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */
+ wsect += fs->fsize;
+ disk_write(fs->drv, fs->win, wsect, 1);
}
}
}
- return res;
+ return FR_OK;
}
#endif
@@ -791,22 +783,17 @@ FRESULT move_window ( DWORD sector /* Sector number to make appearance in the fs->win[] */
)
{
- FRESULT res = FR_OK;
-
-
- if (sector != fs->winsect) { /* Window offset changed? */
+ if (sector != fs->winsect) { /* Changed current window */
#if !_FS_READONLY
- res = sync_window(fs); /* Write-back changes */
+ if (sync_window(fs) != FR_OK)
+ return FR_DISK_ERR;
#endif
- if (res == FR_OK) { /* Fill sector window with new data */
- if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) {
- sector = 0xFFFFFFFF; /* Invalidate window if data is not reliable */
- res = FR_DISK_ERR;
- }
- fs->winsect = sector;
- }
+ if (disk_read(fs->drv, fs->win, sector, 1))
+ return FR_DISK_ERR;
+ fs->winsect = sector;
}
- return res;
+
+ return FR_OK;
}
@@ -855,7 +842,7 @@ FRESULT sync_fs ( /* FR_OK: successful, FR_DISK_ERR: failed */ /*-----------------------------------------------------------------------*/
/* Get sector# from cluster# */
/*-----------------------------------------------------------------------*/
-/* Hidden API for hacks and disk tools */
+
DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */
FATFS* fs, /* File system object */
@@ -863,7 +850,7 @@ DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ )
{
clst -= 2;
- if (clst >= fs->n_fatent - 2) return 0; /* Invalid cluster# */
+ if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */
return clst * fs->csize + fs->database;
}
@@ -873,52 +860,44 @@ DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ /*-----------------------------------------------------------------------*/
/* FAT access - Read value of a FAT entry */
/*-----------------------------------------------------------------------*/
-/* Hidden API for hacks and disk tools */
-DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x0FFFFFFF:Cluster status */
+
+DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */
FATFS* fs, /* File system object */
- DWORD clst /* FAT item index (cluster#) to get the value */
+ DWORD clst /* Cluster# to get the link information */
)
{
UINT wc, bc;
BYTE *p;
- DWORD val;
- if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
- val = 1; /* Internal error */
+ if (clst < 2 || clst >= fs->n_fatent) /* Check range */
+ return 1;
- } else {
- val = 0xFFFFFFFF; /* Default value falls on disk error */
+ switch (fs->fs_type) {
+ case FS_FAT12 :
+ bc = (UINT)clst; bc += bc / 2;
+ if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
+ wc = fs->win[bc % SS(fs)]; bc++;
+ if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
+ wc |= fs->win[bc % SS(fs)] << 8;
+ return clst & 1 ? wc >> 4 : (wc & 0xFFF);
- switch (fs->fs_type) {
- case FS_FAT12 :
- bc = (UINT)clst; bc += bc / 2;
- if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
- wc = fs->win[bc++ % SS(fs)];
- if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
- wc |= fs->win[bc % SS(fs)] << 8;
- val = clst & 1 ? wc >> 4 : (wc & 0xFFF);
- break;
+ case FS_FAT16 :
+ if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break;
+ p = &fs->win[clst * 2 % SS(fs)];
+ return LD_WORD(p);
- case FS_FAT16 :
- if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
- p = &fs->win[clst * 2 % SS(fs)];
- val = LD_WORD(p);
- break;
+ case FS_FAT32 :
+ if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break;
+ p = &fs->win[clst * 4 % SS(fs)];
+ return LD_DWORD(p) & 0x0FFFFFFF;
- case FS_FAT32 :
- if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
- p = &fs->win[clst * 4 % SS(fs)];
- val = LD_DWORD(p) & 0x0FFFFFFF;
- break;
-
- default:
- val = 1; /* Internal error */
- }
+ default:
+ return 1;
}
- return val;
+ return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */
}
@@ -927,12 +906,11 @@ DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x0FFFFFFF:Cluste /*-----------------------------------------------------------------------*/
/* FAT access - Change value of a FAT entry */
/*-----------------------------------------------------------------------*/
-/* Hidden API for hacks and disk tools */
-
#if !_FS_READONLY
+
FRESULT put_fat (
FATFS* fs, /* File system object */
- DWORD clst, /* FAT item index (cluster#) to be set */
+ DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */
DWORD val /* New value to mark the cluster */
)
{
@@ -950,14 +928,14 @@ FRESULT put_fat ( bc = (UINT)clst; bc += bc / 2;
res = move_window(fs, fs->fatbase + (bc / SS(fs)));
if (res != FR_OK) break;
- p = &fs->win[bc++ % SS(fs)];
+ p = &fs->win[bc % SS(fs)];
*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+ bc++;
fs->wflag = 1;
res = move_window(fs, fs->fatbase + (bc / SS(fs)));
if (res != FR_OK) break;
p = &fs->win[bc % SS(fs)];
*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
- fs->wflag = 1;
break;
case FS_FAT16 :
@@ -965,7 +943,6 @@ FRESULT put_fat ( if (res != FR_OK) break;
p = &fs->win[clst * 2 % SS(fs)];
ST_WORD(p, (WORD)val);
- fs->wflag = 1;
break;
case FS_FAT32 :
@@ -974,12 +951,12 @@ FRESULT put_fat ( p = &fs->win[clst * 4 % SS(fs)];
val |= LD_DWORD(p) & 0xF0000000;
ST_DWORD(p, val);
- fs->wflag = 1;
break;
default :
res = FR_INT_ERR;
}
+ fs->wflag = 1;
}
return res;
@@ -1001,7 +978,7 @@ FRESULT remove_chain ( {
FRESULT res;
DWORD nxt;
-#if _USE_TRIM
+#if _USE_ERASE
DWORD scl = clst, ecl = clst, rt[2];
#endif
@@ -1021,13 +998,13 @@ FRESULT remove_chain ( fs->free_clust++;
fs->fsi_flag |= 1;
}
-#if _USE_TRIM
+#if _USE_ERASE
if (ecl + 1 == nxt) { /* Is next cluster contiguous? */
ecl = nxt;
} else { /* End of contiguous clusters */
rt[0] = clust2sect(fs, scl); /* Start sector */
rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */
- disk_ioctl(fs->drv, CTRL_TRIM, rt); /* Erase the block */
+ disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt); /* Erase the block */
scl = ecl = nxt;
}
#endif
@@ -1269,8 +1246,8 @@ FRESULT dir_alloc ( do {
res = move_window(dp->fs, dp->sect);
if (res != FR_OK) break;
- if (dp->dir[0] == DDE || dp->dir[0] == 0) { /* Is it a free entry? */
- if (++n == nent) break; /* A block of contiguous free entries is found */
+ if (dp->dir[0] == DDE || dp->dir[0] == 0) { /* Is it a blank entry? */
+ if (++n == nent) break; /* A block of contiguous entries is found */
} else {
n = 0; /* Not a blank entry. Restart to search */
}
@@ -1549,7 +1526,7 @@ FRESULT dir_find ( }
} else { /* An SFN entry is found */
if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */
- if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dir, dp->fn, 11)) break; /* SFN matched? */
+ if (!(dp->fn[NS] & NS_LOSS) && !mem_cmp(dir, dp->fn, 11)) break; /* SFN matched? */
ord = 0xFF; dp->lfn_idx = 0xFFFF; /* Reset LFN sequence */
}
}
@@ -1591,7 +1568,7 @@ FRESULT dir_read ( if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
a = dir[DIR_Attr] & AM_MASK;
#if _USE_LFN /* LFN configuration */
- if (c == DDE || (!_FS_RPATH && c == '.') || (int)((a & ~AM_ARC) == AM_VOL) != vol) { /* An entry without valid data */
+ if (c == DDE || (!_FS_RPATH && c == '.') || (int)(a == AM_VOL) != vol) { /* An entry without valid data */
ord = 0xFF;
} else {
if (a == AM_LFN) { /* An LFN entry is found */
@@ -1609,7 +1586,7 @@ FRESULT dir_read ( }
}
#else /* Non LFN configuration */
- if (c != DDE && (_FS_RPATH || c != '.') && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol) /* Is it a valid entry? */
+ if (c != DDE && (_FS_RPATH || c != '.') && a != AM_LFN && (int)(a == AM_VOL) == vol) /* Is it a valid entry? */
break;
#endif
res = dir_next(dp, 0); /* Next entry */
@@ -1644,11 +1621,11 @@ FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many fn = dp->fn; lfn = dp->lfn;
mem_cpy(sn, fn, 12);
- if (_FS_RPATH && (sn[NSFLAG] & NS_DOT)) /* Cannot create dot entry */
+ if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */
return FR_INVALID_NAME;
- if (sn[NSFLAG] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */
- fn[NSFLAG] = 0; dp->lfn = 0; /* Find only SFN */
+ if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */
+ fn[NS] = 0; dp->lfn = 0; /* Find only SFN */
for (n = 1; n < 100; n++) {
gen_numname(fn, sn, lfn, n); /* Generate a numbered name */
res = dir_find(dp); /* Check if the name collides with existing SFN */
@@ -1656,10 +1633,10 @@ FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many }
if (n == 100) return FR_DENIED; /* Abort if too many collisions */
if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */
- fn[NSFLAG] = sn[NSFLAG]; dp->lfn = lfn;
+ fn[NS] = sn[NS]; dp->lfn = lfn;
}
- if (sn[NSFLAG] & NS_LFN) { /* When LFN is to be created, allocate entries for an SFN + LFNs. */
+ if (sn[NS] & NS_LFN) { /* When LFN is to be created, allocate entries for an SFN + LFNs. */
for (n = 0; lfn[n]; n++) ;
nent = (n + 25) / 13;
} else { /* Otherwise allocate an entry for an SFN */
@@ -1690,7 +1667,7 @@ FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many mem_set(dp->dir, 0, SZ_DIR); /* Clean the entry */
mem_cpy(dp->dir, dp->fn, 11); /* Put SFN */
#if _USE_LFN
- dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT); /* Put NT flag */
+ dp->dir[DIR_NTres] = dp->fn[NS] & (NS_BODY | NS_EXT); /* Put NT flag */
#endif
dp->fs->wflag = 1;
}
@@ -1946,7 +1923,7 @@ FRESULT create_name ( if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */
}
- dp->fn[NSFLAG] = cf; /* SFN is created */
+ dp->fn[NS] = cf; /* SFN is created */
return FR_OK;
@@ -1970,7 +1947,7 @@ FRESULT create_name ( }
if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
*path = &p[si]; /* Return pointer to the next segment */
- sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */
+ sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */
return FR_OK;
}
#endif
@@ -2021,7 +1998,7 @@ FRESULT create_name ( if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */
if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */
- sfn[NSFLAG] = c; /* Store NT flag, File name is created */
+ sfn[NS] = c; /* Store NT flag, File name is created */
return FR_OK;
#endif
@@ -2064,7 +2041,7 @@ FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ res = create_name(dp, &path); /* Get a segment name of the path */
if (res != FR_OK) break;
res = dir_find(dp); /* Find an object with the sagment name */
- ns = dp->fn[NSFLAG];
+ ns = dp->fn[NS];
if (res != FR_OK) { /* Failed to find the object */
if (res == FR_NO_FILE) { /* Object is not found */
if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, */
@@ -2306,7 +2283,7 @@ FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */ szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */
fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
}
- if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than the size needed) */
+ if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than needed) */
return FR_NO_FILESYSTEM;
#if !_FS_READONLY
@@ -2494,7 +2471,7 @@ FRESULT f_open ( }
}
if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */
- dw = GET_FATTIME(); /* Created time */
+ dw = get_fattime(); /* Created time */
ST_DWORD(dir+DIR_CrtTime, dw);
dir[DIR_Attr] = 0; /* Reset attribute */
ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */
@@ -2620,7 +2597,7 @@ FRESULT f_read ( if (cc) { /* Read maximum contiguous sectors directly */
if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
cc = fp->fs->csize - csect;
- if (disk_read(fp->fs->drv, rbuff, sect, cc) != RES_OK)
+ if (disk_read(fp->fs->drv, rbuff, sect, cc))
ABORT(fp->fs, FR_DISK_ERR);
#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */
#if _FS_TINY
@@ -2638,12 +2615,12 @@ FRESULT f_read ( if (fp->dsect != sect) { /* Load data sector if not in cache */
#if !_FS_READONLY
if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1))
ABORT(fp->fs, FR_DISK_ERR);
fp->flag &= ~FA__DIRTY;
}
#endif
- if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) /* Fill sector cache */
+ if (disk_read(fp->fs->drv, fp->buf, sect, 1)) /* Fill sector cache */
ABORT(fp->fs, FR_DISK_ERR);
}
#endif
@@ -2652,7 +2629,7 @@ FRESULT f_read ( rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */
if (rcnt > btr) rcnt = btr;
#if _FS_TINY
- if (move_window(fp->fs, fp->dsect) != FR_OK) /* Move sector window */
+ if (move_window(fp->fs, fp->dsect)) /* Move sector window */
ABORT(fp->fs, FR_DISK_ERR);
mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */
#else
@@ -2723,7 +2700,7 @@ FRESULT f_write ( ABORT(fp->fs, FR_DISK_ERR);
#else
if (fp->flag & FA__DIRTY) { /* Write-back sector cache */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1))
ABORT(fp->fs, FR_DISK_ERR);
fp->flag &= ~FA__DIRTY;
}
@@ -2735,7 +2712,7 @@ FRESULT f_write ( if (cc) { /* Write maximum contiguous sectors directly */
if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
cc = fp->fs->csize - csect;
- if (disk_write(fp->fs->drv, wbuff, sect, cc) != RES_OK)
+ if (disk_write(fp->fs->drv, wbuff, sect, cc))
ABORT(fp->fs, FR_DISK_ERR);
#if _FS_MINIMIZE <= 2
#if _FS_TINY
@@ -2761,7 +2738,7 @@ FRESULT f_write ( #else
if (fp->dsect != sect) { /* Fill sector cache with file data */
if (fp->fptr < fp->fsize &&
- disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)
+ disk_read(fp->fs->drv, fp->buf, sect, 1))
ABORT(fp->fs, FR_DISK_ERR);
}
#endif
@@ -2770,7 +2747,7 @@ FRESULT f_write ( wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */
if (wcnt > btw) wcnt = btw;
#if _FS_TINY
- if (move_window(fp->fs, fp->dsect) != FR_OK) /* Move sector window */
+ if (move_window(fp->fs, fp->dsect)) /* Move sector window */
ABORT(fp->fs, FR_DISK_ERR);
mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */
fp->fs->wflag = 1;
@@ -2808,7 +2785,7 @@ FRESULT f_sync ( /* Write-back dirty buffer */
#if !_FS_TINY
if (fp->flag & FA__DIRTY) {
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1))
LEAVE_FF(fp->fs, FR_DISK_ERR);
fp->flag &= ~FA__DIRTY;
}
@@ -2820,7 +2797,7 @@ FRESULT f_sync ( dir[DIR_Attr] |= AM_ARC; /* Set archive bit */
ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */
st_clust(dir, fp->sclust); /* Update start cluster */
- tm = GET_FATTIME(); /* Update updated time */
+ tm = get_fattime(); /* Update updated time */
ST_DWORD(dir+DIR_WrtTime, tm);
ST_WORD(dir+DIR_LstAccDate, 0);
fp->flag &= ~FA__WRITTEN;
@@ -3069,12 +3046,12 @@ FRESULT f_lseek ( #if !_FS_TINY
#if !_FS_READONLY
if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1))
ABORT(fp->fs, FR_DISK_ERR);
fp->flag &= ~FA__DIRTY;
}
#endif
- if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) /* Load current sector */
+ if (disk_read(fp->fs->drv, fp->buf, dsc, 1)) /* Load current sector */
ABORT(fp->fs, FR_DISK_ERR);
#endif
fp->dsect = dsc;
@@ -3144,12 +3121,12 @@ FRESULT f_lseek ( #if !_FS_TINY
#if !_FS_READONLY
if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1))
ABORT(fp->fs, FR_DISK_ERR);
fp->flag &= ~FA__DIRTY;
}
#endif
- if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK) /* Fill sector cache */
+ if (disk_read(fp->fs->drv, fp->buf, nsect, 1)) /* Fill sector cache */
ABORT(fp->fs, FR_DISK_ERR);
#endif
fp->dsect = nsect;
@@ -3440,7 +3417,7 @@ FRESULT f_truncate ( }
#if !_FS_TINY
if (res == FR_OK && (fp->flag & FA__DIRTY)) {
- if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1))
res = FR_DISK_ERR;
else
fp->flag &= ~FA__DIRTY;
@@ -3467,7 +3444,7 @@ FRESULT f_unlink ( FRESULT res;
DIR dj, sdj;
BYTE *dir;
- DWORD dclst = 0;
+ DWORD dclst;
DEF_NAMEBUF;
@@ -3476,46 +3453,45 @@ FRESULT f_unlink ( if (res == FR_OK) {
INIT_BUF(dj);
res = follow_path(&dj, path); /* Follow the file path */
- if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
res = FR_INVALID_NAME; /* Cannot remove dot entry */
#if _FS_LOCK
- if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open object */
+ if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */
#endif
if (res == FR_OK) { /* The object is accessible */
dir = dj.dir;
if (!dir) {
- res = FR_INVALID_NAME; /* Cannot remove the origin directory */
+ res = FR_INVALID_NAME; /* Cannot remove the start directory */
} else {
if (dir[DIR_Attr] & AM_RDO)
res = FR_DENIED; /* Cannot remove R/O object */
}
- //if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */
- if (res == FR_OK) {
- dclst = ld_clust(dj.fs, dir);
- if (dir[DIR_Attr] & AM_DIR) { /* Is it a sub-dir? */
- if (!dclst) {
- res = FR_INT_ERR;
- } else { /* Make sure the sub-directory is empty */
- mem_cpy(&sdj, &dj, sizeof (DIR));
- sdj.sclust = dclst;
- res = dir_sdi(&sdj, 2); /* Exclude dot entries */
- if (res == FR_OK) {
- res = dir_read(&sdj, 0); /* Read an item */
- if (res == FR_OK /* Not empty directory */
+ dclst = ld_clust(dj.fs, dir);
+ if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */
+ if (dclst < 2) {
+ res = FR_INT_ERR;
+ } else {
+ mem_cpy(&sdj, &dj, sizeof (DIR)); /* Check if the sub-directory is empty or not */
+ sdj.sclust = dclst;
+ res = dir_sdi(&sdj, 2); /* Exclude dot entries */
+ if (res == FR_OK) {
+ res = dir_read(&sdj, 0); /* Read an item */
+ if (res == FR_OK /* Not empty directory */
#if _FS_RPATH
- || dclst == dj.fs->cdir /* or current directory */
+ || dclst == dj.fs->cdir /* Current directory */
#endif
- ) res = FR_DENIED;
- if (res == FR_NO_FILE) res = FR_OK; /* It is empty */
- }
+ ) res = FR_DENIED;
+ if (res == FR_NO_FILE) res = FR_OK; /* Empty */
}
}
}
if (res == FR_OK) {
res = dir_remove(&dj); /* Remove the directory entry */
- if (res == FR_OK && dclst) /* Remove the cluster chain if exist */
- res = remove_chain(dj.fs, dclst);
- if (res == FR_OK) res = sync_fs(dj.fs);
+ if (res == FR_OK) {
+ if (dclst) /* Remove the cluster chain if exist */
+ res = remove_chain(dj.fs, dclst);
+ if (res == FR_OK) res = sync_fs(dj.fs);
+ }
}
}
FREE_BUF();
@@ -3538,7 +3514,7 @@ FRESULT f_mkdir ( FRESULT res;
DIR dj;
BYTE *dir, n;
- DWORD dsc, dcl, pcl, tm = GET_FATTIME();
+ DWORD dsc, dcl, pcl, tm = get_fattime();
DEF_NAMEBUF;
@@ -3548,7 +3524,7 @@ FRESULT f_mkdir ( INIT_BUF(dj);
res = follow_path(&dj, path); /* Follow the file path */
if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */
- if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT))
+ if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT))
res = FR_INVALID_NAME;
if (res == FR_NO_FILE) { /* Can create a new directory */
dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */
@@ -3623,7 +3599,7 @@ FRESULT f_chmod ( INIT_BUF(dj);
res = follow_path(&dj, path); /* Follow the file path */
FREE_BUF();
- if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
res = FR_INVALID_NAME;
if (res == FR_OK) {
dir = dj.dir;
@@ -3645,6 +3621,48 @@ FRESULT f_chmod ( /*-----------------------------------------------------------------------*/
+/* Change Timestamp */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+ const TCHAR* path, /* Pointer to the file/directory name */
+ const FILINFO* fno /* Pointer to the time stamp to be set */
+)
+{
+ FRESULT res;
+ DIR dj;
+ BYTE *dir;
+ DEF_NAMEBUF;
+
+
+ /* Get logical drive number */
+ res = find_volume(&dj.fs, &path, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ FREE_BUF();
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+ if (res == FR_OK) {
+ dir = dj.dir;
+ if (!dir) { /* Root directory */
+ res = FR_INVALID_NAME;
+ } else { /* File or sub-directory */
+ ST_WORD(dir+DIR_WrtTime, fno->ftime);
+ ST_WORD(dir+DIR_WrtDate, fno->fdate);
+ dj.fs->wflag = 1;
+ res = sync_fs(dj.fs);
+ }
+ }
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
/* Rename File/Directory */
/*-----------------------------------------------------------------------*/
@@ -3666,7 +3684,7 @@ FRESULT f_rename ( djn.fs = djo.fs;
INIT_BUF(djo);
res = follow_path(&djo, path_old); /* Check old object */
- if (_FS_RPATH && res == FR_OK && (djo.fn[NSFLAG] & NS_DOT))
+ if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT))
res = FR_INVALID_NAME;
#if _FS_LOCK
if (res == FR_OK) res = chk_lock(&djo, 2);
@@ -3678,19 +3696,19 @@ FRESULT f_rename ( mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except name */
mem_cpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */
if (get_ldnumber(&path_new) >= 0) /* Snip drive number off and ignore it */
- res = follow_path(&djn, path_new); /* and make sure if new object name is not conflicting */
+ res = follow_path(&djn, path_new); /* and check if new object is exist */
else
res = FR_INVALID_DRIVE;
if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */
- if (res == FR_NO_FILE) { /* It is a valid path and no name collision */
-/* Start of critical section that any interruption can cause a cross-link */
+ if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */
+/* Start critical section that any interruption can cause a cross-link */
res = dir_register(&djn); /* Register the new entry */
if (res == FR_OK) {
dir = djn.dir; /* Copy object information except name */
mem_cpy(dir+13, buf+2, 19);
dir[DIR_Attr] = buf[0] | AM_ARC;
djo.fs->wflag = 1;
- if ((dir[DIR_Attr] & AM_DIR) && djo.sclust != djn.sclust) { /* Update .. entry in the directory if needed */
+ if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */
dw = clust2sect(djo.fs, ld_clust(djo.fs, dir));
if (!dw) {
res = FR_INT_ERR;
@@ -3698,7 +3716,8 @@ FRESULT f_rename ( res = move_window(djo.fs, dw);
dir = djo.fs->win+SZ_DIR; /* .. entry */
if (res == FR_OK && dir[1] == '.') {
- st_clust(dir, djn.sclust);
+ dw = (djo.fs->fs_type == FS_FAT32 && djn.sclust == djo.fs->dirbase) ? 0 : djn.sclust;
+ st_clust(dir, dw);
djo.fs->wflag = 1;
}
}
@@ -3709,7 +3728,7 @@ FRESULT f_rename ( res = sync_fs(djo.fs);
}
}
-/* End of critical section */
+/* End critical section */
}
}
}
@@ -3719,48 +3738,6 @@ FRESULT f_rename ( LEAVE_FF(djo.fs, res);
}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Change Timestamp */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_utime (
- const TCHAR* path, /* Pointer to the file/directory name */
- const FILINFO* fno /* Pointer to the time stamp to be set */
-)
-{
- FRESULT res;
- DIR dj;
- BYTE *dir;
- DEF_NAMEBUF;
-
-
- /* Get logical drive number */
- res = find_volume(&dj.fs, &path, 1);
- if (res == FR_OK) {
- INIT_BUF(dj);
- res = follow_path(&dj, path); /* Follow the file path */
- FREE_BUF();
- if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT))
- res = FR_INVALID_NAME;
- if (res == FR_OK) {
- dir = dj.dir;
- if (!dir) { /* Root directory */
- res = FR_INVALID_NAME;
- } else { /* File or sub-directory */
- ST_WORD(dir+DIR_WrtTime, fno->ftime);
- ST_WORD(dir+DIR_WrtDate, fno->fdate);
- dj.fs->wflag = 1;
- res = sync_fs(dj.fs);
- }
- }
- }
-
- LEAVE_FF(dj.fs, res);
-}
-
#endif /* !_FS_READONLY */
#endif /* _FS_MINIMIZE == 0 */
#endif /* _FS_MINIMIZE <= 1 */
@@ -3894,7 +3871,7 @@ FRESULT f_setlabel ( if (res == FR_OK) { /* A volume label is found */
if (vn[0]) {
mem_cpy(dj.dir, vn, 11); /* Change the volume label name */
- tm = GET_FATTIME();
+ tm = get_fattime();
ST_DWORD(dj.dir+DIR_WrtTime, tm);
} else {
dj.dir[0] = DDE; /* Remove the volume label */
@@ -3910,7 +3887,7 @@ FRESULT f_setlabel ( mem_set(dj.dir, 0, SZ_DIR); /* Set volume label */
mem_cpy(dj.dir, vn, 11);
dj.dir[DIR_Attr] = AM_VOL;
- tm = GET_FATTIME();
+ tm = get_fattime();
ST_DWORD(dj.dir+DIR_WrtTime, tm);
dj.fs->wflag = 1;
res = sync_fs(dj.fs);
@@ -3973,7 +3950,7 @@ FRESULT f_forward ( sect = clust2sect(fp->fs, fp->clust); /* Get current data sector */
if (!sect) ABORT(fp->fs, FR_INT_ERR);
sect += csect;
- if (move_window(fp->fs, sect) != FR_OK) /* Move sector window */
+ if (move_window(fp->fs, sect)) /* Move sector window */
ABORT(fp->fs, FR_DISK_ERR);
fp->dsect = sect;
rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */
@@ -3993,13 +3970,13 @@ FRESULT f_forward ( /* Create File System on the Drive */
/*-----------------------------------------------------------------------*/
#define N_ROOTDIR 512 /* Number of root directory entries for FAT12/16 */
-#define N_FATS 1 /* Number of FATs (1 or 2) */
+#define N_FATS 1 /* Number of FAT copies (1 or 2) */
FRESULT f_mkfs (
const TCHAR* path, /* Logical drive number */
BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */
- UINT au /* Size of allocation unit in unit of byte or sector */
+ UINT au /* Allocation unit [bytes] */
)
{
static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0};
@@ -4015,9 +3992,10 @@ FRESULT f_mkfs ( /* Check mounted drive and clear work area */
- if (sfd > 1) return FR_INVALID_PARAMETER;
vol = get_ldnumber(&path);
if (vol < 0) return FR_INVALID_DRIVE;
+ if (sfd > 1) return FR_INVALID_PARAMETER;
+ if (au & (au - 1)) return FR_INVALID_PARAMETER;
fs = FatFs[vol];
if (!fs) return FR_NOT_ENABLED;
fs->fs_type = 0;
@@ -4034,7 +4012,7 @@ FRESULT f_mkfs ( #endif
if (_MULTI_PARTITION && part) {
/* Get partition information from partition table in the MBR */
- if (disk_read(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR;
+ if (disk_read(pdrv, fs->win, 0, 1)) return FR_DISK_ERR;
if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED;
tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
if (!tbl[4]) return FR_MKFS_ABORTED; /* No partition? */
@@ -4048,14 +4026,13 @@ FRESULT f_mkfs ( n_vol -= b_vol; /* Volume size */
}
- if (au & (au - 1)) au = 0;
- if (!au) { /* AU auto selection */
+ if (!au) { /* AU auto selection */
vs = n_vol / (2000 / (SS(fs) / 512));
for (i = 0; vs < vst[i]; i++) ;
au = cst[i];
}
- if (au >= _MIN_SS) au /= SS(fs); /* Number of sectors per cluster */
- if (!au) au = 1;
+ au /= SS(fs); /* Number of sectors per cluster */
+ if (au == 0) au = 1;
if (au > 128) au = 128;
/* Pre-compute number of clusters and FAT sub-type */
@@ -4112,7 +4089,7 @@ FRESULT f_mkfs ( /* Update system ID in the partition table */
tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
tbl[4] = sys;
- if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) /* Write it to teh MBR */
+ if (disk_write(pdrv, fs->win, 0, 1)) /* Write it to teh MBR */
return FR_DISK_ERR;
md = 0xF8;
} else {
@@ -4132,7 +4109,7 @@ FRESULT f_mkfs ( ST_DWORD(tbl+8, 63); /* Partition start in LBA */
ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */
ST_WORD(fs->win+BS_55AA, 0xAA55); /* MBR signature */
- if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) /* Write it to the MBR */
+ if (disk_write(pdrv, fs->win, 0, 1)) /* Write it to the MBR */
return FR_DISK_ERR;
md = 0xF8;
}
@@ -4158,7 +4135,7 @@ FRESULT f_mkfs ( ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */
ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */
ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */
- n = GET_FATTIME(); /* Use current time as VSN */
+ n = get_fattime(); /* Use current time as VSN */
if (fmt == FS_FAT32) {
ST_DWORD(tbl+BS_VolID32, n); /* VSN */
ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */
@@ -4176,7 +4153,7 @@ FRESULT f_mkfs ( mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */
}
ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */
- if (disk_write(pdrv, tbl, b_vol, 1) != RES_OK) /* Write it to the VBR sector */
+ if (disk_write(pdrv, tbl, b_vol, 1)) /* Write it to the VBR sector */
return FR_DISK_ERR;
if (fmt == FS_FAT32) /* Write backup VBR if needed (VBR+6) */
disk_write(pdrv, tbl, b_vol + 6, 1);
@@ -4195,11 +4172,11 @@ FRESULT f_mkfs ( ST_DWORD(tbl+4, 0xFFFFFFFF);
ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root directory */
}
- if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+ if (disk_write(pdrv, tbl, wsect++, 1))
return FR_DISK_ERR;
mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */
for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector writes */
- if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+ if (disk_write(pdrv, tbl, wsect++, 1))
return FR_DISK_ERR;
}
}
@@ -4207,16 +4184,16 @@ FRESULT f_mkfs ( /* Initialize root directory */
i = (fmt == FS_FAT32) ? au : (UINT)n_dir;
do {
- if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+ if (disk_write(pdrv, tbl, wsect++, 1))
return FR_DISK_ERR;
} while (--i);
-#if _USE_TRIM /* Erase data area if needed */
+#if _USE_ERASE /* Erase data area if needed */
{
DWORD eb[2];
eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1;
- disk_ioctl(pdrv, CTRL_TRIM, eb);
+ disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb);
}
#endif
@@ -4299,7 +4276,7 @@ FRESULT f_fdisk ( ST_WORD(p, 0xAA55);
/* Write it to the MBR */
- return (disk_write(pdrv, buf, 0, 1) != RES_OK || disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) ? FR_DISK_ERR : FR_OK;
+ return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK;
}
diff --git a/testhal/STM32/STM32F4xx/USB_HOST/ff.h b/testhal/STM32/STM32F4xx/USB_HOST/ff.h index 5eaad5f..9894921 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/ff.h +++ b/testhal/STM32/STM32F4xx/USB_HOST/ff.h @@ -1,5 +1,5 @@ /*---------------------------------------------------------------------------/
-/ FatFs - FAT file system module include file R0.10c (C)ChaN, 2014
+/ FatFs - FAT file system module include file R0.10b (C)ChaN, 2014
/----------------------------------------------------------------------------/
/ FatFs module is a generic FAT file system module for small embedded systems.
/ This is a free software that opened for education, research and commercial
@@ -15,7 +15,7 @@ /----------------------------------------------------------------------------*/
#ifndef _FATFS
-#define _FATFS 80376 /* Revision ID */
+#define _FATFS 8051 /* Revision ID */
#ifdef __cplusplus
extern "C" {
@@ -23,6 +23,7 @@ extern "C" { #include "integer.h" /* Basic integer types */
#include "ffconf.h" /* FatFs configuration options */
+
#if _FATFS != _FFCONF
#error Wrong configuration file (ffconf.h).
#endif
@@ -235,7 +236,7 @@ int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
-#define f_eof(fp) ((int)((fp)->fptr == (fp)->fsize))
+#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
#define f_error(fp) ((fp)->err)
#define f_tell(fp) ((fp)->fptr)
#define f_size(fp) ((fp)->fsize)
@@ -251,7 +252,7 @@ TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the fil /* Additional user defined functions */
/* RTC function */
-#if !_FS_READONLY && !_FS_NORTC
+#if !_FS_READONLY
DWORD get_fattime (void);
#endif
diff --git a/testhal/STM32/STM32F4xx/USB_HOST/ffconf.h b/testhal/STM32/STM32F4xx/USB_HOST/ffconf.h index 0ae6f01..2af5efe 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/ffconf.h +++ b/testhal/STM32/STM32F4xx/USB_HOST/ffconf.h @@ -1,31 +1,33 @@ +/* CHIBIOS FIX */
+#include "ch.h"
+
/*---------------------------------------------------------------------------/
-/ FatFs - FAT file system module configuration file R0.10c (C)ChaN, 2014
+/ FatFs - FAT file system module configuration file R0.10b (C)ChaN, 2014
/---------------------------------------------------------------------------*/
-#include "ch.h"
-#define _FFCONF 80376 /* Revision ID */
+#ifndef _FFCONF
+#define _FFCONF 8051 /* Revision ID */
+
/*---------------------------------------------------------------------------/
/ Functions and Buffer Configurations
/---------------------------------------------------------------------------*/
-#define _FS_TINY 0
-/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
-/ At the tiny configuration, size of the file object (FIL) is reduced _MAX_SS
-/ bytes. Instead of private sector buffer eliminated from the file object,
-/ common sector buffer in the file system object (FATFS) is used for the file
-/ data transfer. */
+#define _FS_TINY 0 /* 0:Normal or 1:Tiny */
+/* When _FS_TINY is set to 1, it reduces memory consumption _MAX_SS bytes each
+/ file object. For file data transfer, FatFs uses the common sector buffer in
+/ the file system object (FATFS) instead of private sector buffer eliminated
+/ from the file object (FIL). */
-#define _FS_READONLY 0
-/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
-/ Read-only configuration removes basic writing API functions, f_write(),
-/ f_sync(), f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(),
-/ f_getfree() and optional writing functions as well. */
+#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */
+/* Setting _FS_READONLY to 1 defines read only configuration. This removes
+/ writing functions, f_write(), f_sync(), f_unlink(), f_mkdir(), f_chmod(),
+/ f_rename(), f_truncate() and useless f_getfree(). */
-#define _FS_MINIMIZE 0
-/* This option defines minimization level to remove some API functions.
+#define _FS_MINIMIZE 0 /* 0 to 3 */
+/* The _FS_MINIMIZE option defines minimization level to remove API functions.
/
/ 0: All basic functions are enabled.
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_chmod(), f_utime(),
@@ -34,40 +36,32 @@ / 3: f_lseek() function is removed in addition to 2. */
-#define _USE_STRFUNC 0
-/* This option switches string functions, f_gets(), f_putc(), f_puts() and
-/ f_printf().
-/
-/ 0: Disable string functions.
-/ 1: Enable without LF-CRLF conversion.
-/ 2: Enable with LF-CRLF conversion. */
+#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */
+/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
-#define _USE_MKFS 0
-/* This option switches f_mkfs() function. (0:Disable or 1:Enable)
-/ To enable it, also _FS_READONLY need to be set to 0. */
+#define _USE_MKFS 0 /* 0:Disable or 1:Enable */
+/* To enable f_mkfs() function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
-#define _USE_FASTSEEK 0
-/* This option switches fast seek feature. (0:Disable or 1:Enable) */
+#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
+/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
-#define _USE_LABEL 0
-/* This option switches volume label functions, f_getlabel() and f_setlabel().
-/ (0:Disable or 1:Enable) */
+#define _USE_LABEL 0 /* 0:Disable or 1:Enable */
+/* To enable volume label functions, set _USE_LAVEL to 1 */
-#define _USE_FORWARD 0
-/* This option switches f_forward() function. (0:Disable or 1:Enable) */
-/* To enable it, also _FS_TINY need to be set to 1. */
+#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
+/* To enable f_forward() function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
/*---------------------------------------------------------------------------/
/ Locale and Namespace Configurations
/---------------------------------------------------------------------------*/
-#define _CODE_PAGE 437
-/* This option specifies the OEM code page to be used on the target system.
+#define _CODE_PAGE 1252
+/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
/ Incorrect setting of the code page can cause a file open failure.
/
/ 932 - Japanese Shift_JIS (DBCS, OEM, Windows)
@@ -95,11 +89,11 @@ / 857 - Turkish (OEM)
/ 862 - Hebrew (OEM)
/ 874 - Thai (OEM, Windows)
-/ 1 - ASCII (No extended character. Valid for only non-LFN configuration.) */
+/ 1 - ASCII (Valid for only non-LFN configuration) */
-#define _USE_LFN 0
-#define _MAX_LFN 255
+#define _USE_LFN 3 /* 0 to 3 */
+#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
/* The _USE_LFN option switches the LFN feature.
/
/ 0: Disable LFN feature. _MAX_LFN has no effect.
@@ -107,86 +101,77 @@ / 2: Enable LFN with dynamic working buffer on the STACK.
/ 3: Enable LFN with dynamic working buffer on the HEAP.
/
-/ When enable the LFN feature, Unicode handling functions (option/unicode.c) must
-/ be added to the project. The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes.
-/ When use stack for the working buffer, take care on stack overflow. When use heap
-/ memory for the working buffer, memory management functions, ff_memalloc() and
-/ ff_memfree(), must be added to the project. */
+/ When enable LFN feature, Unicode handling functions ff_convert() and ff_wtoupper()
+/ function must be added to the project.
+/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. When use stack for the
+/ working buffer, take care on stack overflow. When use heap memory for the working
+/ buffer, memory management functions, ff_memalloc() and ff_memfree(), must be added
+/ to the project. */
-#define _LFN_UNICODE 0
-/* This option switches character encoding on the API. (0:ANSI/OEM or 1:Unicode)
-/ To use Unicode string for the path name, enable LFN feature and set _LFN_UNICODE
-/ to 1. This option also affects behavior of string I/O functions. */
+#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
+/* To switch the character encoding on the FatFs API (TCHAR) to Unicode, enable LFN
+/ feature and set _LFN_UNICODE to 1. This option affects behavior of string I/O
+/ functions. This option must be 0 when LFN feature is not enabled. */
-#define _STRF_ENCODE 3
-/* When _LFN_UNICODE is 1, this option selects the character encoding on the file to
-/ be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
-/
-/ 0: ANSI/OEM
-/ 1: UTF-16LE
-/ 2: UTF-16BE
-/ 3: UTF-8
-/
-/ When _LFN_UNICODE is 0, this option has no effect. */
+#define _STRF_ENCODE 3 /* 0:ANSI/OEM, 1:UTF-16LE, 2:UTF-16BE, 3:UTF-8 */
+/* When Unicode API is enabled by _LFN_UNICODE option, this option selects the character
+/ encoding on the file to be read/written via string I/O functions, f_gets(), f_putc(),
+/ f_puts and f_printf(). This option has no effect when Unicode API is not enabled. */
-#define _FS_RPATH 0
-/* This option configures relative path feature.
+#define _FS_RPATH 0 /* 0 to 2 */
+/* The _FS_RPATH option configures relative path feature.
/
/ 0: Disable relative path feature and remove related functions.
-/ 1: Enable relative path feature. f_chdir() and f_chdrive() are available.
+/ 1: Enable relative path. f_chdrive() and f_chdir() function are available.
/ 2: f_getcwd() function is available in addition to 1.
/
-/ Note that directory items read via f_readdir() are affected by this option. */
+/ Note that output of the f_readdir() fnction is affected by this option. */
/*---------------------------------------------------------------------------/
/ Drive/Volume Configurations
/---------------------------------------------------------------------------*/
-#define _VOLUMES 1
+#define _VOLUMES 1
/* Number of volumes (logical drives) to be used. */
-#define _STR_VOLUME_ID 0
-#define _VOLUME_STRS "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
-/* _STR_VOLUME_ID option switches string volume ID feature.
-/ When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
-/ number in the path name. _VOLUME_STRS defines the drive ID strings for each
-/ logical drives. Number of items must be equal to _VOLUMES. Valid characters for
-/ the drive ID strings are: A-Z and 0-9. */
+#define _STR_VOLUME_ID 0 /* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */
+#define _VOLUME_STRS "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
+/* When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
+/ number in the path name. _VOLUME_STRS defines the drive ID strings for each logical
+/ drives. Number of items must be equal to _VOLUMES. Valid characters for the drive ID
+/ strings are: 0-9 and A-Z. */
-#define _MULTI_PARTITION 0
-/* This option switches multi-partition feature. By default (0), each logical drive
-/ number is bound to the same physical drive number and only an FAT volume found on
-/ the physical drive will be mounted. When multi-partition feature is enabled (1),
-/ each logical drive number is bound to arbitrary physical drive and partition
-/ listed in the VolToPart[]. Also f_fdisk() funciton will be enabled. */
+#define _MULTI_PARTITION 0 /* 0:Single partition, 1:Enable multiple partition */
+/* By default(0), each logical drive number is bound to the same physical drive number
+/ and only a FAT volume found on the physical drive is mounted. When it is set to 1,
+/ each logical drive number is bound to arbitrary drive/partition listed in VolToPart[].
+*/
-#define _MIN_SS 512
-#define _MAX_SS 512
-/* These options configure the range of sector size to be supported. (512, 1024,
-/ 2048 or 4096) Always set both 512 for most systems, all type of memory cards and
-/ harddisk. But a larger value may be required for on-board flash memory and some
-/ type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
-/ to variable sector size and GET_SECTOR_SIZE command must be implemented to the
-/ disk_ioctl() function. */
+#define _MIN_SS 512
+#define _MAX_SS 512
+/* These options configure the range of sector size to be supported. (512, 1024, 2048 or
+/ 4096) Always set both 512 for most systems, all memory card and harddisk. But a larger
+/ value may be required for on-board flash memory and some type of optical media.
+/ When _MAX_SS is larger than _MIN_SS, FatFs is configured to variable sector size and
+/ GET_SECTOR_SIZE command must be implemented to the disk_ioctl() function. */
-#define _USE_TRIM 0
-/* This option switches ATA-TRIM feature. (0:Disable or 1:Enable)
-/ To enable Trim feature, also CTRL_TRIM command should be implemented to the
-/ disk_ioctl() function. */
+#define _USE_ERASE 0 /* 0:Disable or 1:Enable */
+/* To enable sector erase feature, set _USE_ERASE to 1. Also CTRL_ERASE_SECTOR command
+/ should be added to the disk_ioctl() function. */
-#define _FS_NOFSINFO 0
-/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
-/ option, and f_getfree() function at first time after volume mount will force
-/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+#define _FS_NOFSINFO 0 /* 0 to 3 */
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this option
+/ and f_getfree() function at first time after volume mount will force a full FAT scan.
+/ Bit 1 controls the last allocated cluster number as bit 0.
/
/ bit0=0: Use free cluster count in the FSINFO if available.
/ bit0=1: Do not trust free cluster count in the FSINFO.
@@ -200,72 +185,46 @@ / System Configurations
/---------------------------------------------------------------------------*/
-#define _FS_NORTC 0
-#define _NORTC_MON 11
-#define _NORTC_MDAY 9
-#define _NORTC_YEAR 2014
-/* The _FS_NORTC option switches timestamp feature. If the system does not have
-/ an RTC function or valid timestamp is not needed, set _FS_NORTC to 1 to disable
-/ the timestamp feature. All objects modified by FatFs will have a fixed timestamp
-/ defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR.
-/ When timestamp feature is enabled (_FS_NORTC == 0), get_fattime() function need
-/ to be added to the project to read current time form RTC. _NORTC_MON,
-/ _NORTC_MDAY and _NORTC_YEAR have no effect.
-/ These options have no effect at read-only configuration (_FS_READONLY == 1). */
-
-
-#define _FS_LOCK 0
-/* The _FS_LOCK option switches file lock feature to control duplicated file open
-/ and illegal operation to open objects. This option must be 0 when _FS_READONLY
-/ is 1.
-/
-/ 0: Disable file lock feature. To avoid volume corruption, application program
-/ should avoid illegal open, remove and rename to the open objects.
-/ >0: Enable file lock feature. The value defines how many files/sub-directories
-/ can be opened simultaneously under file lock control. Note that the file
-/ lock feature is independent of re-entrancy. */
-
-
-#define _FS_REENTRANT 0
-#define _FS_TIMEOUT S2ST(10)
-typedef semaphore_t * _SYNC_t;
-/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs
-/ module itself. Note that regardless of this option, file access to different
-/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
-/ and f_fdisk() function, are always not re-entrant. Only file/directory access
-/ to the same volume is under control of this feature.
+#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */
+/* To enable file lock control feature, set _FS_LOCK to non-zero value.
+/ The value defines how many files/sub-directories can be opened simultaneously
+/ with file lock control. This feature uses bss _FS_LOCK * 12 bytes. */
+
+
+#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
+#define _FS_TIMEOUT MS2ST(1000) /* Timeout period in unit of time tick */
+#define _SYNC_t semaphore_t* /* O/S dependent sync object type. e.g. HANDLE, OS_EVENT*, ID, SemaphoreHandle_t and etc.. */
+/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs module.
/
/ 0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
-/ function, must be added to the project. Samples are available in
-/ option/syscall.c.
-/
-/ The _FS_TIMEOUT defines timeout period in unit of time tick.
-/ The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
-/ SemaphoreHandle_t and etc.. */
+/ function must be added to the project.
+*/
-#define _WORD_ACCESS 0
+#define _WORD_ACCESS 0 /* 0 or 1 */
/* The _WORD_ACCESS option is an only platform dependent option. It defines
/ which access method is used to the word data on the FAT volume.
/
/ 0: Byte-by-byte access. Always compatible with all platforms.
/ 1: Word access. Do not choose this unless under both the following conditions.
/
-/ * Address misaligned memory access is always allowed to ALL instructions.
+/ * Address misaligned memory access is always allowed for ALL instructions.
/ * Byte order on the memory is little-endian.
/
-/ If it is the case, _WORD_ACCESS can also be set to 1 to reduce code size.
-/ Following table shows allowable settings of some processor types.
+/ If it is the case, _WORD_ACCESS can also be set to 1 to improve performance and
+/ reduce code size. Following table shows an example of some processor types.
/
-/ ARM7TDMI 0 ColdFire 0 V850E 0
+/ ARM7TDMI 0 ColdFire 0 V850E2 0
/ Cortex-M3 0 Z80 0/1 V850ES 0/1
-/ Cortex-M0 0 x86 0/1 TLCS-870 0/1
-/ AVR 0/1 RX600(LE) 0/1 TLCS-900 0/1
+/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1
+/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1
/ AVR32 0 RL78 0 R32C 0
/ PIC18 0/1 SH-2 0 M16C 0/1
/ PIC24 0 H8S 0 MSP430 0
-/ PIC32 0 H8/300H 0 8051 0/1
+/ PIC32 0 H8/300H 0 x86 0/1
*/
+
+#endif /* _FFCONF */
diff --git a/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h b/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h index 49db499..807d741 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h +++ b/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _HALCONF_COMMUNITY_H_
-#define _HALCONF_COMMUNITY_H_
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
@@ -190,6 +190,6 @@ */
#define ONEWIRE_USE_SEARCH_ROM TRUE
-#endif /* _HALCONF_COMMUNITY_H_ */
+#endif /* HALCONF_COMMUNITY_H */
/** @} */
diff --git a/testhal/STM32/STM32F4xx/USB_HOST/main.c b/testhal/STM32/STM32F4xx/USB_HOST/main.c index bfb318f..23470b8 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/main.c +++ b/testhal/STM32/STM32F4xx/USB_HOST/main.c @@ -17,14 +17,12 @@ #include "ch.h"
#include "hal.h"
#include "ff.h"
-#include "usbh.h"
#include <string.h>
#if HAL_USBH_USE_FTDI
#include "usbh/dev/ftdi.h"
-#include "test.h"
#include "shell.h"
#include "chprintf.h"
@@ -51,56 +49,6 @@ static uint8_t buf[] = "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef";
-static void cmd_mem(BaseSequentialStream *chp, int argc, char *argv[]) {
- size_t n, size;
-
- (void)argv;
- if (argc > 0) {
- chprintf(chp, "Usage: mem\r\n");
- return;
- }
- n = chHeapStatus(NULL, &size);
- chprintf(chp, "core free memory : %u bytes\r\n", chCoreGetStatusX());
- chprintf(chp, "heap fragments : %u\r\n", n);
- chprintf(chp, "heap free total : %u bytes\r\n", size);
-}
-
-static void cmd_threads(BaseSequentialStream *chp, int argc, char *argv[]) {
- static const char *states[] = {CH_STATE_NAMES};
- thread_t *tp;
-
- (void)argv;
- if (argc > 0) {
- chprintf(chp, "Usage: threads\r\n");
- return;
- }
- chprintf(chp, " addr stack prio refs state\r\n");
- tp = chRegFirstThread();
- do {
- chprintf(chp, "%08lx %08lx %4lu %4lu %9s\r\n",
- (uint32_t)tp, (uint32_t)tp->p_ctx.r13,
- (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1),
- states[tp->p_state]);
- tp = chRegNextThread(tp);
- } while (tp != NULL);
-}
-
-static void cmd_test(BaseSequentialStream *chp, int argc, char *argv[]) {
- thread_t *tp;
-
- (void)argv;
- if (argc > 0) {
- chprintf(chp, "Usage: test\r\n");
- return;
- }
- tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriorityX(),
- TestThread, chp);
- if (tp == NULL) {
- chprintf(chp, "out of memory\r\n");
- return;
- }
- chThdWait(tp);
-}
static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) {
@@ -115,15 +63,12 @@ static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) { }
while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) {
- chSequentialStreamWrite(&FTDIPD[0], buf, sizeof buf - 1);
+ streamWrite(&FTDIPD[0], buf, sizeof buf - 1);
}
chprintf(chp, "\r\n\nstopped\r\n");
}
static const ShellCommand commands[] = {
- {"mem", cmd_mem},
- {"threads", cmd_threads},
- {"test", cmd_test},
{"write", cmd_write},
{NULL, NULL}
};
@@ -159,12 +104,12 @@ start: //loopback
if (0) {
for(;;) {
- msg_t m = chSequentialStreamGet(ftdipp);
+ msg_t m = streamGet(ftdipp);
if (m < MSG_OK) {
usbDbgPuts("FTDI: Disconnected");
goto start;
}
- chSequentialStreamPut(ftdipp, (uint8_t)m);
+ streamPut(ftdipp, (uint8_t)m);
if (m == 'q')
break;
}
@@ -177,7 +122,7 @@ start: if (ftdipp->state != USBHFTDIP_STATE_READY)
goto start;
if (!shelltp) {
- shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
+ shelltp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, "shell", NORMALPRIO, shellThread, (void *) &shell_cfg1);
} else if (chThdTerminatedX(shelltp)) {
chThdRelease(shelltp);
if (ftdipp->state != USBHFTDIP_STATE_READY)
@@ -191,7 +136,7 @@ start: //FTDI uart RX to debug TX bridge
if (0) {
for(;;) {
- msg_t m = chSequentialStreamGet(ftdipp);
+ msg_t m = streamGet(ftdipp);
if (m < MSG_OK) {
usbDbgPuts("FTDI: Disconnected");
goto start;
@@ -215,14 +160,14 @@ start: uint32_t times = bytes / 1024;
st = chVTGetSystemTimeX();
while (times--) {
- if (chSequentialStreamWrite(ftdipp, buf, 1024) < 1024) {
+ if (streamWrite(ftdipp, buf, 1024) < 1024) {
usbDbgPuts("FTDI: Disconnected");
goto start;
}
bytes -= 1024;
}
if (bytes) {
- if (chSequentialStreamWrite(ftdipp, buf, bytes) < bytes) {
+ if (streamWrite(ftdipp, buf, bytes) < bytes) {
usbDbgPuts("FTDI: Disconnected");
goto start;
}
@@ -235,7 +180,7 @@ start: //single character write test (tests the timer)
if (0) {
for (;;) {
- if (chSequentialStreamPut(ftdipp, 'A') != MSG_OK) {
+ if (streamPut(ftdipp, 'A') != MSG_OK) {
usbDbgPuts("FTDI: Disconnected");
goto start;
}
diff --git a/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h b/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h index 56775af..5cb823a 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h @@ -48,19 +48,19 @@ /* * USBH driver system settings. */ -#define STM32_OTG1_CHANNELS_NUMBER 8 -#define STM32_OTG2_CHANNELS_NUMBER 12 +#define STM32_OTG1_CHANNELS_NUMBER 8 +#define STM32_OTG2_CHANNELS_NUMBER 12 -#define STM32_USBH_USE_OTG1 1 -#define STM32_OTG1_RXFIFO_SIZE 1024 -#define STM32_OTG1_PTXFIFO_SIZE 128 -#define STM32_OTG1_NPTXFIFO_SIZE 128 +#define STM32_USBH_USE_OTG1 1 +#define STM32_OTG1_RXFIFO_SIZE 1024 +#define STM32_OTG1_PTXFIFO_SIZE 128 +#define STM32_OTG1_NPTXFIFO_SIZE 128 -#define STM32_USBH_USE_OTG2 0 -#define STM32_OTG2_RXFIFO_SIZE 2048 -#define STM32_OTG2_PTXFIFO_SIZE 1024 -#define STM32_OTG2_NPTXFIFO_SIZE 1024 +#define STM32_USBH_USE_OTG2 0 +#define STM32_OTG2_RXFIFO_SIZE 2048 +#define STM32_OTG2_PTXFIFO_SIZE 1024 +#define STM32_OTG2_NPTXFIFO_SIZE 1024 -#define STM32_USBH_MIN_QSPACE 4 -#define STM32_USBH_CHANNELS_NP 4 +#define STM32_USBH_MIN_QSPACE 4 +#define STM32_USBH_CHANNELS_NP 4 diff --git a/testhal/STM32/STM32F4xx/onewire/.cproject b/testhal/STM32/STM32F4xx/onewire/.cproject index f6e2450..d2cdbd2 100644 --- a/testhal/STM32/STM32F4xx/onewire/.cproject +++ b/testhal/STM32/STM32F4xx/onewire/.cproject @@ -49,4 +49,5 @@ </scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="refreshScope"/>
</cproject>
diff --git a/testhal/STM32/STM32F4xx/onewire/.project b/testhal/STM32/STM32F4xx/onewire/.project index 30d6ff3..a82f065 100644 --- a/testhal/STM32/STM32F4xx/onewire/.project +++ b/testhal/STM32/STM32F4xx/onewire/.project @@ -1,6 +1,6 @@ <?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
- <name>STM32F4xx-onewire</name>
+ <name>STM32F4xx-1-Wire</name>
<comment></comment>
<projects>
</projects>
@@ -80,12 +80,18 @@ <link>
<name>os-community</name>
<type>2</type>
- <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
+ <locationURI>CHIBIOS_CONTRIB/os</locationURI>
</link>
<link>
<name>os-git</name>
<type>2</type>
- <locationURI>PARENT-5-PROJECT_LOC/ChibiOS-RT/os</locationURI>
+ <locationURI>copy_PARENT/ChibiOS-RT/os</locationURI>
</link>
</linkedResources>
+ <variableList>
+ <variable>
+ <name>copy_PARENT</name>
+ <value>$%7BPARENT-1-CHIBIOS%7D</value>
+ </variable>
+ </variableList>
</projectDescription>
diff --git a/testhal/STM32/STM32F4xx/onewire/Makefile b/testhal/STM32/STM32F4xx/onewire/Makefile index 02ab018..092b023 100644 --- a/testhal/STM32/STM32F4xx/onewire/Makefile +++ b/testhal/STM32/STM32F4xx/onewire/Makefile @@ -88,6 +88,7 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../../../ChibiOS-RT CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +TESTHAL = $(CHIBIOS_CONTRIB)/testhal/common/onewire # Startup files. include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk # HAL-OSAL files (optional). @@ -113,7 +114,7 @@ CSRC = $(STARTUPSRC) \ $(BOARDSRC) \ $(TESTSRC) \ main.c \ - onewire_test.c + $(TESTHAL)/testhal_onewire.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -146,7 +147,8 @@ ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) INCDIR = $(CHIBIOS)/os/license \ $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ - $(CHIBIOS)/os/various + $(CHIBIOS)/os/various \ + $(TESTHAL) # # Project, sources and paths diff --git a/testhal/STM32/STM32F4xx/onewire/boarddef.h b/testhal/STM32/STM32F4xx/onewire/boarddef.h new file mode 100644 index 0000000..a048dcb --- /dev/null +++ b/testhal/STM32/STM32F4xx/onewire/boarddef.h @@ -0,0 +1,28 @@ +/* + ChibiOS/RT - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef BOARDDEF_H_ +#define BOARDDEF_H_ + +#define ONEWIRE_PORT GPIOB +#define ONEWIRE_PIN GPIOB_PIN0 +#define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) +#define search_led_off() (palClearPad(GPIOD, GPIOD_LED4)) +#define search_led_on() (palSetPad(GPIOD, GPIOD_LED4)) +#define ONEWIRE_MASTER_CHANNEL 2 +#define ONEWIRE_SAMPLE_CHANNEL 3 + +#endif /* BOARDDEF_H_ */ diff --git a/testhal/STM32/STM32F4xx/onewire/halconf_community.h b/testhal/STM32/STM32F4xx/onewire/halconf_community.h index 91dbfbc..0621fdb 100644 --- a/testhal/STM32/STM32F4xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F4xx/onewire/halconf_community.h @@ -14,8 +14,8 @@ limitations under the License.
*/
-#ifndef _HALCONF_COMMUNITY_H_
-#define _HALCONF_COMMUNITY_H_
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
/**
* @brief Enables the community overlay.
@@ -93,6 +93,6 @@ */
#define ONEWIRE_USE_SEARCH_ROM TRUE
-#endif /* _HALCONF_COMMUNITY_H_ */
+#endif /* HALCONF_COMMUNITY_H */
/** @} */
diff --git a/testhal/STM32/STM32F4xx/onewire/main.c b/testhal/STM32/STM32F4xx/onewire/main.c index 793bffe..5265edc 100644 --- a/testhal/STM32/STM32F4xx/onewire/main.c +++ b/testhal/STM32/STM32F4xx/onewire/main.c @@ -17,7 +17,7 @@ #include "ch.h"
#include "hal.h"
-#include "onewire_test.h"
+#include "testhal_onewire.h"
/*
* Application entry point.
diff --git a/testhal/STM32/STM32F4xx/onewire/onewire_test.c b/testhal/STM32/STM32F4xx/onewire/onewire_test.c deleted file mode 100644 index be20dbc..0000000 --- a/testhal/STM32/STM32F4xx/onewire/onewire_test.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include <string.h> - -#include "hal.h" - -/* - ****************************************************************************** - * DEFINES - ****************************************************************************** - */ - -#if defined(BOARD_ST_STM32F4_DISCOVERY) || \ - defined(BOARD_ST_STM32F0_DISCOVERY) || \ - defined(BOARD_ST_STM32F0308_DISCOVERY) - #if ONEWIRE_USE_STRONG_PULLUP - #error "This board has not enough voltage for this feature" - #endif -#endif - -#if defined(BOARD_ST_STM32F0308_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOC, GPIOC_LED4)) - #define search_led_on() (palSetPad(GPIOC, GPIOC_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_ST_STM32F4_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOD, GPIOD_LED4)) - #define search_led_on() (palSetPad(GPIOD, GPIOD_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_OLIMEX_STM32_103STK) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN 0 - #define ONEWIRE_PAD_MODE_IDLE PAL_MODE_INPUT - #define ONEWIRE_PAD_MODE_ACTIVE PAL_MODE_STM32_ALTERNATE_OPENDRAIN - #define search_led_on() (palClearPad(GPIOC, GPIOC_LED)) - #define search_led_off() (palSetPad(GPIOC, GPIOC_LED)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#else - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_TACHOMETER - #include "pads.h" - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_on red_led_on - #define search_led_off red_led_off - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#endif - -/* - ****************************************************************************** - * EXTERNS - ****************************************************************************** - */ - -/* - ****************************************************************************** - * PROTOTYPES - ****************************************************************************** - */ -/* - * Forward declarations - */ -#if ONEWIRE_USE_STRONG_PULLUP -static void strong_pullup_assert(void); -static void strong_pullup_release(void); -#endif - -/* - ****************************************************************************** - * GLOBAL VARIABLES - ****************************************************************************** - */ - -static uint8_t testbuf[12]; - -/* stores 3 temperature values in millicelsius */ -static int32_t temperature[3]; - -/* - * Config for underlied PWM driver. - * Note! It is NOT constant because 1-wire driver needs to change them - * during functioning. - */ -static PWMConfig pwm_cfg = { - 0, - 0, - NULL, - { - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL}, - {PWM_OUTPUT_DISABLED, NULL} - }, - 0, -#if STM32_PWM_USE_ADVANCED - 0, -#endif - 0 -}; - -/* - * - */ -static const onewireConfig ow_cfg = { - &PWMD3, - &pwm_cfg, - PWM_OUTPUT_ACTIVE_LOW, - ONEWIRE_MASTER_CHANNEL, - ONEWIRE_SAMPLE_CHANNEL, - ONEWIRE_PORT, - ONEWIRE_PIN, -#if defined(STM32F1XX) - ONEWIRE_PAD_MODE_IDLE, -#endif - ONEWIRE_PAD_MODE_ACTIVE, -#if ONEWIRE_USE_STRONG_PULLUP - strong_pullup_assert, - strong_pullup_release -#endif -}; - -/* - ****************************************************************************** - ****************************************************************************** - * LOCAL FUNCTIONS - ****************************************************************************** - ****************************************************************************** - */ - -#if ONEWIRE_USE_STRONG_PULLUP -/** - * - */ -static void strong_pullup_assert(void) { - palSetPadMode(ONEWIRE_PORT, ONEWIRE_PIN, PAL_MODE_STM32_ALTERNATE_PUSHPULL); -} - -/** - * - */ -static void strong_pullup_release(void) { - palSetPadMode(ONEWIRE_PORT, ONEWIRE_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); -} -#endif /* ONEWIRE_USE_STRONG_PULLUP */ - -/* - ****************************************************************************** - * EXPORTED FUNCTIONS - ****************************************************************************** - */ - -/** - * - */ -void onewireTest(void) { - - int16_t tmp; - uint8_t rombuf[24]; - size_t devices_on_bus = 0; - size_t i = 0; - bool presence; - - onewireObjectInit(&OWD1); - onewireStart(&OWD1, &ow_cfg); - -#if ONEWIRE_SYNTH_SEARCH_TEST - synthSearchRomTest(&OWD1); -#endif - - for (i=0; i<3; i++) - temperature[i] = -666; - - while (true) { - if (true == onewireReset(&OWD1)){ - - memset(rombuf, 0x55, sizeof(rombuf)); - search_led_on(); - devices_on_bus = onewireSearchRom(&OWD1, rombuf, 3); - search_led_off(); - osalDbgCheck(devices_on_bus <= 3); - osalDbgCheck(devices_on_bus > 0); - - if (1 == devices_on_bus){ - /* test read rom command */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - testbuf[0] = ONEWIRE_CMD_READ_ROM; - onewireWrite(&OWD1, testbuf, 1, 0); - onewireRead(&OWD1, testbuf, 8); - osalDbgCheck(testbuf[7] == onewireCRC(testbuf, 7)); - osalDbgCheck(0 == memcmp(rombuf, testbuf, 8)); - } - - /* start temperature measurement on all connected devices at once */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - testbuf[0] = ONEWIRE_CMD_SKIP_ROM; - testbuf[1] = ONEWIRE_CMD_CONVERT_TEMP; - -#if ONEWIRE_USE_STRONG_PULLUP - onewireWrite(&OWD1, testbuf, 2, MS2ST(750)); -#else - onewireWrite(&OWD1, testbuf, 2, 0); - /* poll bus waiting ready signal from all connected devices */ - testbuf[0] = 0; - while (testbuf[0] == 0){ - osalThreadSleepMilliseconds(50); - onewireRead(&OWD1, testbuf, 1); - } -#endif - - for (i=0; i<devices_on_bus; i++) { - /* read temperature device by device from their scratchpads */ - presence = onewireReset(&OWD1); - osalDbgCheck(true == presence); - - testbuf[0] = ONEWIRE_CMD_MATCH_ROM; - memcpy(&testbuf[1], &rombuf[i*8], 8); - testbuf[9] = ONEWIRE_CMD_READ_SCRATCHPAD; - onewireWrite(&OWD1, testbuf, 10, 0); - - onewireRead(&OWD1, testbuf, 9); - osalDbgCheck(testbuf[8] == onewireCRC(testbuf, 8)); - memcpy(&tmp, &testbuf, 2); - temperature[i] = ((int32_t)tmp * 625) / 10; - } - } - else { - osalSysHalt("No devices found"); - } - osalThreadSleep(1); /* enforce ChibiOS's stack overflow check */ - } - - onewireStop(&OWD1); -} diff --git a/testhal/STM32/STM32F4xx/onewire/real_roms.txt b/testhal/STM32/STM32F4xx/onewire/real_roms.txt deleted file mode 100644 index ea19c1a..0000000 --- a/testhal/STM32/STM32F4xx/onewire/real_roms.txt +++ /dev/null @@ -1,27 +0,0 @@ -rombuf[0] 0x28 -rombuf[1] 0xec -rombuf[2] 0xf5 -rombuf[3] 0x67 -rombuf[4] 0x5 -rombuf[5] 0x0 -rombuf[6] 0x0 -rombuf[7] 0x1d - -rombuf[8] 0x28 -rombuf[9] 0xbd -rombuf[10] 0x1a -rombuf[11] 0x60 -rombuf[12] 0x5 -rombuf[13] 0x0 -rombuf[14] 0x0 -rombuf[15] 0x37 - -rombuf[16] 0x28 -rombuf[17] 0x83 -rombuf[18] 0x7d -rombuf[19] 0x67 -rombuf[20] 0x5 -rombuf[21] 0x0 -rombuf[22] 0x0 -rombuf[23] 0xf - diff --git a/testhal/STM32/STM32F4xx/onewire/search_rom_synth.c b/testhal/STM32/STM32F4xx/onewire/search_rom_synth.c deleted file mode 100644 index cd2528f..0000000 --- a/testhal/STM32/STM32F4xx/onewire/search_rom_synth.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include <stdlib.h> - -/* - ****************************************************************************** - * DEFINES - ****************************************************************************** - */ - -/* do not set it more than 64 because of some fill_pattern functions - * will be broken.*/ -#define SYNTH_DEVICES_MAX 64 - -/* - * synthetic device - */ -typedef struct { - bool active; - uint64_t id; -} OWSynthDevice; - -/* - * synthetic bus - */ -typedef struct { - OWSynthDevice devices[SYNTH_DEVICES_MAX]; - size_t dev_present; - bool complement_bit; - ioline_t rom_bit; -} OWSynthBus; - -/* - ****************************************************************************** - * EXTERNS - ****************************************************************************** - */ - -/* - ****************************************************************************** - * PROTOTYPES - ****************************************************************************** - */ - -/* - ****************************************************************************** - * GLOBAL VARIABLES - ****************************************************************************** - */ - -static OWSynthBus synth_bus; - -/* - * local buffer for discovered ROMs - */ -static uint64_t detected_devices[SYNTH_DEVICES_MAX]; - -/* - ****************************************************************************** - ****************************************************************************** - * LOCAL FUNCTIONS - ****************************************************************************** - ****************************************************************************** - */ - -/* - ****************************************************************************** - * EXPORTED FUNCTIONS - ****************************************************************************** - */ - -/** - * - */ -void _synth_ow_write_bit(onewireDriver *owp, ioline_t bit) { - (void)owp; - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) { - if (((synth_bus.devices[i].id >> synth_bus.rom_bit) & 1U) != bit) { - synth_bus.devices[i].active = false; - } - } - synth_bus.rom_bit++; -} - -/** - * - */ -ioline_t _synth_ow_read_bit(void) { - ioline_t ret = 0xFF; - size_t i; - ioline_t bit; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) { - if (synth_bus.devices[i].active){ - bit = (synth_bus.devices[i].id >> synth_bus.rom_bit) & 1U; - if (synth_bus.complement_bit){ - bit ^= 1U; - } - if (0xFF == ret) - ret = bit; - else - ret &= bit; - } - } - synth_bus.complement_bit = !synth_bus.complement_bit; - return ret; -} - -/** - * - */ -static void synth_reset_pulse(void){ - size_t i; - - for (i=0; i<synth_bus.dev_present; i++){ - synth_bus.devices[i].active = true; - } -} - -/** - * - */ -static size_t synth_search_rom(onewireDriver *owp, uint8_t *result, size_t max_rom_cnt) { - - size_t i; - - search_clean_start(&owp->search_rom); - - do { - /* initialize buffer to store result */ - if (owp->search_rom.reg.devices_found >= max_rom_cnt) - owp->search_rom.retbuf = result + 8*(max_rom_cnt-1); - else - owp->search_rom.retbuf = result + 8*owp->search_rom.reg.devices_found; - memset(owp->search_rom.retbuf, 0, 8); - - /* clean iteration state */ - search_clean_iteration(&owp->search_rom); - - /**/ - synth_reset_pulse(); - synth_bus.rom_bit = 0; - synth_bus.complement_bit = false; - for (i=0; i<64*3 - 1; i++){ - ow_search_rom_cb(NULL, owp); - } - - if (ONEWIRE_SEARCH_ROM_ERROR != owp->search_rom.reg.result) { - /* store cached result for usage in next iteration */ - memcpy(owp->search_rom.prev_path, owp->search_rom.retbuf, 8); - } - } - while (ONEWIRE_SEARCH_ROM_SUCCESS == owp->search_rom.reg.result); - - /**/ - if (ONEWIRE_SEARCH_ROM_ERROR == owp->search_rom.reg.result) - return 0; - else - return owp->search_rom.reg.devices_found; -} - -/** - * - */ -static void fill_pattern_real_devices(void) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - synth_bus.devices[0].active = true; - synth_bus.devices[0].id = 0x1d00000567f5ec28; - - synth_bus.devices[1].active = true; - synth_bus.devices[1].id = 0x37000005601abd28; - - synth_bus.devices[2].active = true; - synth_bus.devices[2].id = 0x0f000005677d8328; -} - -/** - * - */ -static void fill_pattern_00(size_t devices, size_t start) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = (start + i); - } -} - -/** - * - */ -static void fill_pattern_01(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = (devices - i); - } -} - -/** - * - */ -static void fill_pattern_02(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = ((uint64_t)1 << i); - } -} - -/** - * - */ -static void fill_pattern_03(size_t devices) { - size_t i; - - for (i=0; i<SYNTH_DEVICES_MAX; i++) - synth_bus.devices[i].active = false; - - for (i=0; i<devices; i++){ - synth_bus.devices[i].active = true; - synth_bus.devices[i].id = ((uint64_t)0x8000000000000000 >> i); - } -} - -/** - * @brief random pattern helper - */ -static bool is_id_uniq(const OWSynthDevice *dev, size_t n, uint64_t id) { - size_t i; - - for (i=0; i<n; i++) { - if (dev[i].id == id) - return false; - } - return true; -} - -/** - * - */ -static void fill_pattern_rand(size_t devices) { - size_t i; - uint64_t new_id; - - for (i=0; i<SYNTH_DEVICES_MAX; i++){ - synth_bus.devices[i].active = false; - synth_bus.devices[i].id = 0; - } - - for (i=0; i<devices; i++) { - do { - new_id = rand(); - new_id = (new_id << 32) | rand(); - } while (true != is_id_uniq(synth_bus.devices, i, new_id)); - - synth_bus.devices[i].id = new_id; - synth_bus.devices[i].active = true; - } -} - -/** - * - */ -static bool check_result(size_t detected) { - - size_t i,j; - bool match = false; - - for (i=0; i<detected; i++){ - match = false; - for (j=0; j<detected; j++){ - if (synth_bus.devices[i].id == detected_devices[j]){ - match = true; - break; - } - } - if (false == match) - return OSAL_FAILED; - } - return OSAL_SUCCESS; -} - -/** - * - */ -void synthSearchRomTest(onewireDriver *owp) { - - size_t detected = 0; - size_t i; - - synth_bus.dev_present = 3; - fill_pattern_real_devices(); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - for (i=1; i<=SYNTH_DEVICES_MAX; i++){ - synth_bus.dev_present = i; - - fill_pattern_00(synth_bus.dev_present, 0); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_00(synth_bus.dev_present, 1); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_01(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_02(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - - fill_pattern_03(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - } - - i = 0; - while (i < 1000) { - synth_bus.dev_present = 1 + (rand() & 63); - - fill_pattern_rand(synth_bus.dev_present); - detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX); - osalDbgCheck(synth_bus.dev_present == detected); - osalDbgCheck(OSAL_SUCCESS == check_result(detected)); - i++; - } -} - - diff --git a/testhal/STM32/STM32F7xx/USB_MSD/.cproject b/testhal/STM32/STM32F7xx/USB_MSD/.cproject new file mode 100644 index 0000000..e263f01 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/.cproject @@ -0,0 +1,50 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> 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superClass="org.eclipse.cdt.build.core.settings.holder"> + <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.154285937" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> + </tool> + </toolChain> + </folderInfo> + </configuration> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> + </cconfiguration> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <project id="STM32F7xx-USB_RAW.null.1373754647" name="STM32F7xx-USB_RAW"/> + </storageModule> + <storageModule moduleId="scannerConfiguration"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> + <scannerConfigBuildInfo instanceId="0.1487191575"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/> + </scannerConfigBuildInfo> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="refreshScope"/> +</cproject> diff --git a/testhal/STM32/STM32F7xx/USB_MSD/.project b/testhal/STM32/STM32F7xx/USB_MSD/.project new file mode 100644 index 0000000..ac40e79 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/.project @@ -0,0 +1,43 @@ +<?xml version="1.0" encoding="UTF-8"?> +<projectDescription> + <name>STM32F7xx-USB_MSD</name> + <comment></comment> + <projects> + </projects> + <buildSpec> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> + <triggers>clean,full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> + <triggers>full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + </buildSpec> + <natures> + <nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> + <linkedResources> + <link> + <name>os</name> + <type>2</type> + <locationURI>CHIBIOS/os</locationURI> + </link> + <link> + <name>os-contrib</name> + <type>2</type> + <locationURI>CHIBIOS_CONTRIB/os</locationURI> + </link> + <link> + <name>test</name> + <type>2</type> + <locationURI>CHIBIOS/test</locationURI> + </link> + </linkedResources> +</projectDescription> diff --git a/testhal/STM32/STM32F7xx/USB_MSD/Makefile b/testhal/STM32/STM32F7xx/USB_MSD/Makefile new file mode 100644 index 0000000..912a555 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/Makefile @@ -0,0 +1,233 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-sp-d16 -fsingle-precision-constant +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib + +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/test/rt/test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32F76xxI.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + $(STREAMSSRC) \ + $(SHELLSRC) \ + $(CHIBIOS_CONTRIB)/os/various/ramdisk.c \ + $(CHIBIOS_CONTRIB)/os/various/lib_scsi.c \ + usbcfg.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = +ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(CHIBIOS)/os/license \ + $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(STREAMSINC) $(SHELLINC) \ + $(CHIBIOS_CONTRIB)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m7 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = ccache $(TRGT)gcc +CPPC = ccache $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/STM32/STM32F7xx/USB_MSD/chconf.h b/testhal/STM32/STM32F7xx/USB_MSD/chconf.h new file mode 100644 index 0000000..8bdd9f2 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/chconf.h @@ -0,0 +1,522 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK TRUE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS TRUE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS TRUE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK TRUE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS TRUE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#define CORTEX_VTOR_INIT 0x00200000U + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/STM32/STM32F7xx/USB_MSD/halconf.h b/testhal/STM32/STM32F7xx/USB_MSD/halconf.h new file mode 100644 index 0000000..bf1b023 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/halconf.h @@ -0,0 +1,401 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM TRUE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the QSPI subsystem. + */ +#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) +#define HAL_USE_QSPI FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 115200 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 80 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* Community drivers's includes */ +/*===========================================================================*/ + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h b/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h new file mode 100644 index 0000000..943992f --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h @@ -0,0 +1,105 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _HALCONF_COMMUNITY_H_ +#define _HALCONF_COMMUNITY_H_ + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD TRUE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +#endif /* _HALCONF_COMMUNITY_H_ */ + +/** @} */ diff --git a/testhal/STM32/STM32F7xx/USB_MSD/main.c b/testhal/STM32/STM32F7xx/USB_MSD/main.c new file mode 100644 index 0000000..cae2b74 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/main.c @@ -0,0 +1,126 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include <stdio.h> +#include <string.h> + +#include "ch.h" +#include "hal.h" + +#include "usbcfg.h" +#include "hal_usb_msd.h" + +#include "ramdisk.h" +#include "romfs_img.h" + +#define RAMDISK_BLOCK_SIZE 512U +#define RAMDISK_BLOCK_CNT 700U + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + systime_t time; + + time = USBD1.state == USB_ACTIVE ? 100 : 500; + palSetPad(GPIOB, GPIOB_LED1); + chThdSleepMilliseconds(time); + palClearPad(GPIOB, GPIOB_LED1); + chThdSleepMilliseconds(time); + } +} + +RamDisk ramdisk; +__attribute__((section("DATA_RAM"))) static uint8_t ramdisk_storage[RAMDISK_BLOCK_SIZE * RAMDISK_BLOCK_CNT]; +static uint8_t blkbuf[RAMDISK_BLOCK_SIZE]; + +BaseSequentialStream *GlobalDebugChannel; + +static const SerialConfig sercfg = { + 115200, + 0, + 0, + 0 +}; + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + sdStart(&SD3, &sercfg); + GlobalDebugChannel = (BaseSequentialStream *)&SD3; + + /* + * Activates the USB driver and then the USB bus pull-up on D+. + * Note, a delay is inserted in order to not have to disconnect the cable + * after a reset. + */ + usbDisconnectBus(&USBD1); + chThdSleepMilliseconds(1500); + usbStart(&USBD1, &usbcfg); + + /* + * start RAM disk + */ + ramdiskObjectInit(&ramdisk); + memset(ramdisk_storage, 0x55, sizeof(ramdisk_storage)); + osalDbgCheck(sizeof(ramdisk_storage) >= romfs_bin_len); + memcpy(ramdisk_storage, romfs_bin, romfs_bin_len); + ramdiskStart(&ramdisk, ramdisk_storage, RAMDISK_BLOCK_SIZE, + RAMDISK_BLOCK_CNT, false); + + /* + * start mass storage + */ + msdObjectInit(&USBMSD1); + msdStart(&USBMSD1, &USBD1, (BaseBlockDevice *)&ramdisk, blkbuf, NULL); + + /* + * + */ + usbConnectBus(&USBD1); + + /* + * Starting threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + chThdSleepMilliseconds(1000); + } + + msdStop(&USBMSD1); +} diff --git a/testhal/STM32/STM32F7xx/USB_MSD/mcuconf.h b/testhal/STM32/STM32F7xx/USB_MSD/mcuconf.h new file mode 100644 index 0000000..c7bf7a1 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/mcuconf.h @@ -0,0 +1,386 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ diff --git a/testhal/STM32/STM32F7xx/USB_MSD/readme.txt b/testhal/STM32/STM32F7xx/USB_MSD/readme.txt new file mode 100644 index 0000000..ba23a07 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/HAL - USB MSD driver demo for STM32. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST NUCLEO144-F767ZI board. + +** The Demo ** + +The application demonstrates the use of the STM32 USB (OTG) driver as +a mass storage device. + +** Build Procedure ** + +The demo has been tested using the free Codesourcery GCC-based toolchain +and YAGARTO. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/testhal/STM32/STM32F7xx/USB_MSD/romfs_img.h b/testhal/STM32/STM32F7xx/USB_MSD/romfs_img.h new file mode 100644 index 0000000..2755b37 --- /dev/null +++ b/testhal/STM32/STM32F7xx/USB_MSD/romfs_img.h @@ -0,0 +1,3775 @@ +/* + ChibiOS/HAL - Copyright (C) 2016 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +const uint8_t romfs_bin[] = { + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0xb0, 0x00, + 0x5a, 0xbe, 0xcd, 0xd1, 0x72, 0x6f, 0x6d, 0x20, 0x35, 0x37, 0x66, 0x63, + 0x61, 0x39, 0x36, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x24, 0xc9, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x2a, 0x25, 0xf9, 0xd7, 0x74, 0x65, 0x78, 0x6d, 0x61, 0x74, 0x68, 0x73, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#include "hal_usb_cdc.h" +#include "hal_usb_msd.h" +#include "usbcfg.h" + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(0x0020, /* wTotalLength. */ + 0x01, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 0x32), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x08, /* bInterfaceClass (Mass Storage) */ + 0x06, /* bInterfaceSubClass (SCSI + Transparent storage class) */ + 0x50, /* bInterfaceProtocol (Bulk Only) */ + 0), /* iInterface. (none) */ + /* Mass Storage Data In Endpoint Descriptor.*/ + USB_DESC_ENDPOINT (USB_MSD_DATA_EP | 0x80, + 0x02, /* bmAttributes (Bulk). */ + USB_MSD_EP_SIZE, /* wMaxPacketSize. */ + 0x00), /* bInterval. 1ms */ + /* Mass Storage Data Out Endpoint Descriptor.*/ + USB_DESC_ENDPOINT (USB_MSD_DATA_EP, + 0x02, /* bmAttributes (Bulk). */ + USB_MSD_EP_SIZE, /* wMaxPacketSize. */ + 0x00) /* bInterval. 1ms */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + +/* + * Vendor string. + */ +static const uint8_t vcom_string1[] = { + USB_DESC_BYTE(38), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0, + 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0, + 'c', 0, 's', 0 +}; + +/* + * Device Description string. + */ +static const uint8_t vcom_string2[] = { + USB_DESC_BYTE(62), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0, + 'R', 0, 'T', 0, ' ', 0, 'M', 0, 'a', 0, 's', 0, 's', 0, ' ', 0, + 'S', 0, 't', 0, 'o', 0, 'r', 0, 'a', 0, 'g', 0, 'e', 0, ' ', 0, + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0 +}; + +static const uint8_t vcom_string3[] = { + USB_DESC_BYTE(26), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + 'A', 0, 'E', 0, 'C', 0, 'C', 0, 'E', 0, 'C', 0, 'C', 0, 'C', 0, 'C', 0, + '0' + CH_KERNEL_MAJOR, 0, + '0' + CH_KERNEL_MINOR, 0, + '0' + CH_KERNEL_PATCH, 0 +}; + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof vcom_string1, vcom_string1}, + {sizeof vcom_string2, vcom_string2}, + {sizeof vcom_string3, vcom_string3} +}; + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + return &vcom_strings[dindex]; + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + NULL, + NULL, + USB_MSD_EP_SIZE, + USB_MSD_EP_SIZE, + &ep1instate, + &ep1outstate, + 4, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + + switch (event) { + case USB_EVENT_RESET: + return; + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + chSysUnlockFromISR(); + return; + case USB_EVENT_UNCONFIGURED: + return; + case USB_EVENT_SUSPEND: + return; + case USB_EVENT_WAKEUP: + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + msd_request_hook, + NULL +}; + diff --git a/testhal/STM32/STM32F1xx/onewire/onewire_test.h b/testhal/STM32/STM32F7xx/USB_MSD/usbcfg.h index 1bec2d0..496f478 100644 --- a/testhal/STM32/STM32F1xx/onewire/onewire_test.h +++ b/testhal/STM32/STM32F7xx/USB_MSD/usbcfg.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,15 +14,15 @@ limitations under the License. */ -#ifndef ONEWIRE_TEST_H_ -#define ONEWIRE_TEST_H_ +#ifndef USBCFG_H +#define USBCFG_H -#ifdef __cplusplus -extern "C" { -#endif - void onewireTest(void); -#ifdef __cplusplus -} -#endif +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 -#endif /* ONEWIRE_TEST_H_ */ +extern const USBConfig usbcfg; + +#endif /* USBCFG_H */ + +/** @} */ diff --git a/testhal/TIVA/TM4C123x/EXT/Makefile b/testhal/TIVA/TM4C123x/EXT/Makefile index f587083..f2833ec 100644 --- a/testhal/TIVA/TM4C123x/EXT/Makefile +++ b/testhal/TIVA/TM4C123x/EXT/Makefile @@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no endif +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + # # Build global options ############################################################################## diff --git a/testhal/TIVA/TM4C123x/EXT/mcuconf.h b/testhal/TIVA/TM4C123x/EXT/mcuconf.h index 74a4da3..447a40d 100644 --- a/testhal/TIVA/TM4C123x/EXT/mcuconf.h +++ b/testhal/TIVA/TM4C123x/EXT/mcuconf.h @@ -30,15 +30,15 @@ /* * HAL driver system settings. */ -#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO #define TIVA_MOSC_ENABLE TRUE #define TIVA_DIV400_VALUE 1 #define TIVA_SYSDIV_VALUE 2 #define TIVA_USESYSDIV_ENABLE FALSE #define TIVA_SYSDIV2LSB_ENABLE FALSE #define TIVA_BYPASS_VALUE 0 -#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \ - TIVA_RCC_PWMDIV_8) +#define TIVA_PWM_FIELDS (SYSCTL_RCC_USEPWMDIV | \ + SYSCTL_RCC_PWMDIV_8) /* * GPIO driver system settings. diff --git a/testhal/TIVA/TM4C123x/GPT/.cproject b/testhal/TIVA/TM4C123x/GPT/.cproject index 93c394e..4b65a3d 100644 --- a/testhal/TIVA/TM4C123x/GPT/.cproject +++ b/testhal/TIVA/TM4C123x/GPT/.cproject @@ -1,6 +1,5 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?> -<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> +<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> <storageModule moduleId="org.eclipse.cdt.core.settings"> <cconfiguration id="0.114656749"> <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.114656749" moduleId="org.eclipse.cdt.core.settings" name="Default"> @@ -22,12 +21,30 @@ <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.579570726" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/> <tool id="org.eclipse.cdt.build.core.settings.holder.libs.2143276802" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/> <tool id="org.eclipse.cdt.build.core.settings.holder.1873650595" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.1549829577" name="Undefined Include Paths" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C123x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1337802279" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> <tool id="org.eclipse.cdt.build.core.settings.holder.1707090075" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.714763797" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C123x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.338985256" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> <tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.283012868" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C123x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> </toolChain> diff --git a/testhal/TIVA/TM4C123x/GPT/Makefile b/testhal/TIVA/TM4C123x/GPT/Makefile index f587083..f2833ec 100644 --- a/testhal/TIVA/TM4C123x/GPT/Makefile +++ b/testhal/TIVA/TM4C123x/GPT/Makefile @@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no endif +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + # # Build global options ############################################################################## diff --git a/testhal/TIVA/TM4C123x/GPT/mcuconf.h b/testhal/TIVA/TM4C123x/GPT/mcuconf.h index b193fa9..aabe6c5 100644 --- a/testhal/TIVA/TM4C123x/GPT/mcuconf.h +++ b/testhal/TIVA/TM4C123x/GPT/mcuconf.h @@ -30,15 +30,15 @@ /* * HAL driver system settings. */ -#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO #define TIVA_MOSC_ENABLE TRUE #define TIVA_DIV400_VALUE 1 #define TIVA_SYSDIV_VALUE 2 #define TIVA_USESYSDIV_ENABLE FALSE #define TIVA_SYSDIV2LSB_ENABLE FALSE #define TIVA_BYPASS_VALUE 0 -#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \ - TIVA_RCC_PWMDIV_8) +#define TIVA_PWM_FIELDS (SYSCTL_RCC_USEPWMDIV | \ + SYSCTL_RCC_PWMDIV_8) /* * GPIO driver system settings. diff --git a/testhal/TIVA/TM4C123x/I2C/.cproject b/testhal/TIVA/TM4C123x/I2C/.cproject index 31b2a7f..cce9e96 100644 --- a/testhal/TIVA/TM4C123x/I2C/.cproject +++ b/testhal/TIVA/TM4C123x/I2C/.cproject @@ -1,6 +1,5 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?> -<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> +<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> <storageModule moduleId="org.eclipse.cdt.core.settings"> <cconfiguration id="0.114656749"> <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.114656749" moduleId="org.eclipse.cdt.core.settings" name="Default"> @@ -22,12 +21,30 @@ <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.579570726" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/> <tool 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value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> </toolChain> diff --git a/testhal/TIVA/TM4C123x/I2C/Makefile b/testhal/TIVA/TM4C123x/I2C/Makefile index 32abbee..d4d1334 100644 --- a/testhal/TIVA/TM4C123x/I2C/Makefile +++ b/testhal/TIVA/TM4C123x/I2C/Makefile @@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no endif +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + # # Build global options ############################################################################## diff --git a/testhal/TIVA/TM4C123x/I2C/mcuconf.h b/testhal/TIVA/TM4C123x/I2C/mcuconf.h index 81555ed..45bee44 100644 --- a/testhal/TIVA/TM4C123x/I2C/mcuconf.h +++ b/testhal/TIVA/TM4C123x/I2C/mcuconf.h @@ -30,15 +30,15 @@ /* * HAL driver system settings. */ -#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO #define TIVA_MOSC_ENABLE TRUE #define TIVA_DIV400_VALUE 1 #define TIVA_SYSDIV_VALUE 2 #define TIVA_USESYSDIV_ENABLE FALSE #define TIVA_SYSDIV2LSB_ENABLE FALSE #define TIVA_BYPASS_VALUE 0 -#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \ - TIVA_RCC_PWMDIV_8) +#define TIVA_PWM_FIELDS (SYSCTL_RCC_USEPWMDIV | \ + SYSCTL_RCC_PWMDIV_8) /* * GPIO driver system settings. diff --git a/testhal/TIVA/TM4C123x/PWM/.cproject b/testhal/TIVA/TM4C123x/PWM/.cproject index b1141bf..52b9a8b 100644 --- a/testhal/TIVA/TM4C123x/PWM/.cproject +++ b/testhal/TIVA/TM4C123x/PWM/.cproject @@ -1,6 +1,5 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?> -<cproject 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sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> <tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.1093029639" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C123x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> </toolChain> diff --git a/testhal/TIVA/TM4C123x/PWM/Makefile b/testhal/TIVA/TM4C123x/PWM/Makefile index f587083..f2833ec 100644 --- a/testhal/TIVA/TM4C123x/PWM/Makefile +++ b/testhal/TIVA/TM4C123x/PWM/Makefile @@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no endif +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + # # Build global options ############################################################################## diff --git a/testhal/TIVA/TM4C123x/PWM/mcuconf.h b/testhal/TIVA/TM4C123x/PWM/mcuconf.h index 9584bf8..159cb8c 100644 --- a/testhal/TIVA/TM4C123x/PWM/mcuconf.h +++ b/testhal/TIVA/TM4C123x/PWM/mcuconf.h @@ -30,15 +30,15 @@ /* * HAL driver system settings. */ -#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO #define TIVA_MOSC_ENABLE TRUE #define TIVA_DIV400_VALUE 1 #define TIVA_SYSDIV_VALUE 2 #define TIVA_USESYSDIV_ENABLE FALSE #define TIVA_SYSDIV2LSB_ENABLE FALSE #define TIVA_BYPASS_VALUE 0 -#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \ - TIVA_RCC_PWMDIV_8) +#define TIVA_PWM_FIELDS (SYSCTL_RCC_USEPWMDIV | \ + SYSCTL_RCC_PWMDIV_8) /* * GPIO driver system settings. diff --git a/testhal/TIVA/TM4C123x/SPI/.cproject b/testhal/TIVA/TM4C123x/SPI/.cproject index d3a2482..2e8f6a8 100644 --- a/testhal/TIVA/TM4C123x/SPI/.cproject +++ b/testhal/TIVA/TM4C123x/SPI/.cproject @@ -21,12 +21,30 @@ <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.579570726" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/> <tool id="org.eclipse.cdt.build.core.settings.holder.libs.2143276802" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/> <tool id="org.eclipse.cdt.build.core.settings.holder.1873650595" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.972953796" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C123x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1337802279" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> <tool id="org.eclipse.cdt.build.core.settings.holder.1707090075" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.959676881" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C123x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.338985256" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> <tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.1617159785" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C123x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> </toolChain> diff --git a/testhal/TIVA/TM4C123x/SPI/Makefile b/testhal/TIVA/TM4C123x/SPI/Makefile index f587083..f2833ec 100644 --- a/testhal/TIVA/TM4C123x/SPI/Makefile +++ b/testhal/TIVA/TM4C123x/SPI/Makefile @@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no endif +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + # # Build global options ############################################################################## diff --git a/testhal/TIVA/TM4C123x/SPI/main.c b/testhal/TIVA/TM4C123x/SPI/main.c index f04cdbf..7fa05ee 100644 --- a/testhal/TIVA/TM4C123x/SPI/main.c +++ b/testhal/TIVA/TM4C123x/SPI/main.c @@ -31,7 +31,7 @@ static const SPIConfig hs_spicfg = NULL, GPIOA, 3, - TIVA_CR0_DSS(8) | /*TIVA_CR0_SPH | TIVA_CR_SPO |*/ TIVA_CR0_SRC(0), + SSI_CR0_DSS_8 | /*SSI_CR0_SPH | SSI_CR0_SPO |*/ SSI_CR0_SCR(0), 16 }; @@ -43,7 +43,7 @@ static const SPIConfig ls_spicfg = NULL, GPIOA, 3, - TIVA_CR0_DSS(8) | /*TIVA_CR0_SPH | TIVA_CR_SPO |*/ TIVA_CR0_SRC(0), + SSI_CR0_DSS_8 | /*SSI_CR0_SPH | SSI_CR0_SPO |*/ SSI_CR0_SCR(0), 80 }; diff --git a/testhal/TIVA/TM4C123x/SPI/mcuconf.h b/testhal/TIVA/TM4C123x/SPI/mcuconf.h index 74a4da3..447a40d 100644 --- a/testhal/TIVA/TM4C123x/SPI/mcuconf.h +++ b/testhal/TIVA/TM4C123x/SPI/mcuconf.h @@ -30,15 +30,15 @@ /* * HAL driver system settings. */ -#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO #define TIVA_MOSC_ENABLE TRUE #define TIVA_DIV400_VALUE 1 #define TIVA_SYSDIV_VALUE 2 #define TIVA_USESYSDIV_ENABLE FALSE #define TIVA_SYSDIV2LSB_ENABLE FALSE #define TIVA_BYPASS_VALUE 0 -#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \ - TIVA_RCC_PWMDIV_8) +#define TIVA_PWM_FIELDS (SYSCTL_RCC_USEPWMDIV | \ + SYSCTL_RCC_PWMDIV_8) /* * GPIO driver system settings. diff --git a/testhal/TIVA/TM4C123x/WDG/.cproject b/testhal/TIVA/TM4C123x/WDG/.cproject index f9404f1..c91dcb7 100644 --- a/testhal/TIVA/TM4C123x/WDG/.cproject +++ b/testhal/TIVA/TM4C123x/WDG/.cproject @@ -1,6 +1,5 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?> -<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> +<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> <storageModule moduleId="org.eclipse.cdt.core.settings"> <cconfiguration id="0.114656749"> <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.114656749" moduleId="org.eclipse.cdt.core.settings" name="Default"> @@ -22,12 +21,30 @@ <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.579570726" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/> <tool id="org.eclipse.cdt.build.core.settings.holder.libs.2143276802" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/> <tool id="org.eclipse.cdt.build.core.settings.holder.1873650595" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.1980249997" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C123x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1337802279" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> <tool id="org.eclipse.cdt.build.core.settings.holder.1707090075" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.5941192" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C123x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.338985256" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> <tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder"> + <option id="org.eclipse.cdt.build.core.settings.holder.undef.incpaths.1566770389" superClass="org.eclipse.cdt.build.core.settings.holder.undef.incpaths" valueType="undefIncludePath"> + <listOptionValue builtIn="false" value="C:/ChibiStudio/ChibiOS-Contrib/os/common/ports/ARMCMx/devices/TM4C123x"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/ext/CMSIS/include"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx/compilers/GCC"/> + <listOptionValue builtIn="false" value="C:/ChibiStudio/chibios161/os/rt/ports/ARMCMx"/> + </option> <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/> </tool> </toolChain> diff --git a/testhal/TIVA/TM4C123x/WDG/Makefile b/testhal/TIVA/TM4C123x/WDG/Makefile index 5ae01c9..f2833ec 100644 --- a/testhal/TIVA/TM4C123x/WDG/Makefile +++ b/testhal/TIVA/TM4C123x/WDG/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C specific options here (added to USE_OPT). @@ -43,6 +43,12 @@ ifeq ($(USE_VERBOSE_COMPILE),) USE_VERBOSE_COMPILE = no endif +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + # # Build global options ############################################################################## diff --git a/testhal/TIVA/TM4C123x/WDG/main.c b/testhal/TIVA/TM4C123x/WDG/main.c index da08cfb..d5fa9e6 100644 --- a/testhal/TIVA/TM4C123x/WDG/main.c +++ b/testhal/TIVA/TM4C123x/WDG/main.c @@ -36,7 +36,7 @@ static const WDGConfig wdgcfg = { TIVA_SYSCLK, watchdog_timeout, - TEST_STALL + WDT_TEST_STALL }; /* diff --git a/testhal/TIVA/TM4C123x/WDG/mcuconf.h b/testhal/TIVA/TM4C123x/WDG/mcuconf.h index 4136b0a..2ccd4c3 100644 --- a/testhal/TIVA/TM4C123x/WDG/mcuconf.h +++ b/testhal/TIVA/TM4C123x/WDG/mcuconf.h @@ -33,15 +33,15 @@ /* * HAL driver system settings. */ -#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO #define TIVA_MOSC_ENABLE TRUE #define TIVA_DIV400_VALUE 1 #define TIVA_SYSDIV_VALUE 2 #define TIVA_USESYSDIV_ENABLE FALSE #define TIVA_SYSDIV2LSB_ENABLE FALSE #define TIVA_BYPASS_VALUE 0 -#define TIVA_PWM_FIELDS (TIVA_RCC_USEPWMDIV | \ - TIVA_RCC_PWMDIV_8) +#define TIVA_PWM_FIELDS (SYSCTL_RCC_USEPWMDIV | \ + SYSCTL_RCC_PWMDIV_8) /* * GPIO driver system settings. diff --git a/testhal/STM32/STM32F0xx/onewire/real_roms.txt b/testhal/common/onewire/real_roms.txt index ea19c1a..ea19c1a 100644 --- a/testhal/STM32/STM32F0xx/onewire/real_roms.txt +++ b/testhal/common/onewire/real_roms.txt diff --git a/testhal/STM32/STM32F0xx/onewire/search_rom_synth.c b/testhal/common/onewire/synth_searchrom.c index cd2528f..53d4a30 100644 --- a/testhal/STM32/STM32F0xx/onewire/search_rom_synth.c +++ b/testhal/common/onewire/synth_searchrom.c @@ -23,7 +23,7 @@ */ /* do not set it more than 64 because of some fill_pattern functions - * will be broken.*/ + will be broken.*/ #define SYNTH_DEVICES_MAX 64 /* @@ -83,7 +83,7 @@ static uint64_t detected_devices[SYNTH_DEVICES_MAX]; ****************************************************************************** */ -/** +/* * */ void _synth_ow_write_bit(onewireDriver *owp, ioline_t bit) { @@ -98,7 +98,7 @@ void _synth_ow_write_bit(onewireDriver *owp, ioline_t bit) { synth_bus.rom_bit++; } -/** +/* * */ ioline_t _synth_ow_read_bit(void) { @@ -122,7 +122,7 @@ ioline_t _synth_ow_read_bit(void) { return ret; } -/** +/* * */ static void synth_reset_pulse(void){ @@ -133,7 +133,7 @@ static void synth_reset_pulse(void){ } } -/** +/* * */ static size_t synth_search_rom(onewireDriver *owp, uint8_t *result, size_t max_rom_cnt) { @@ -175,7 +175,7 @@ static size_t synth_search_rom(onewireDriver *owp, uint8_t *result, size_t max_r return owp->search_rom.reg.devices_found; } -/** +/* * */ static void fill_pattern_real_devices(void) { @@ -194,7 +194,7 @@ static void fill_pattern_real_devices(void) { synth_bus.devices[2].id = 0x0f000005677d8328; } -/** +/* * */ static void fill_pattern_00(size_t devices, size_t start) { @@ -209,7 +209,7 @@ static void fill_pattern_00(size_t devices, size_t start) { } } -/** +/* * */ static void fill_pattern_01(size_t devices) { @@ -224,7 +224,7 @@ static void fill_pattern_01(size_t devices) { } } -/** +/* * */ static void fill_pattern_02(size_t devices) { @@ -239,7 +239,7 @@ static void fill_pattern_02(size_t devices) { } } -/** +/* * */ static void fill_pattern_03(size_t devices) { @@ -254,8 +254,8 @@ static void fill_pattern_03(size_t devices) { } } -/** - * @brief random pattern helper +/* + * Random pattern helper */ static bool is_id_uniq(const OWSynthDevice *dev, size_t n, uint64_t id) { size_t i; @@ -267,7 +267,7 @@ static bool is_id_uniq(const OWSynthDevice *dev, size_t n, uint64_t id) { return true; } -/** +/* * */ static void fill_pattern_rand(size_t devices) { @@ -290,7 +290,7 @@ static void fill_pattern_rand(size_t devices) { } } -/** +/* * */ static bool check_result(size_t detected) { @@ -312,7 +312,7 @@ static bool check_result(size_t detected) { return OSAL_SUCCESS; } -/** +/* * */ void synthSearchRomTest(onewireDriver *owp) { diff --git a/testhal/STM32/STM32F1xx/onewire/onewire_test.c b/testhal/common/onewire/testhal_onewire.c index be20dbc..93dcc31 100644 --- a/testhal/STM32/STM32F1xx/onewire/onewire_test.c +++ b/testhal/common/onewire/testhal_onewire.c @@ -17,10 +17,11 @@ #include <string.h> #include "hal.h" +#include "boarddef.h" /* ****************************************************************************** - * DEFINES + * ERROR CHECKS ****************************************************************************** */ @@ -32,41 +33,11 @@ #endif #endif -#if defined(BOARD_ST_STM32F0308_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOC, GPIOC_LED4)) - #define search_led_on() (palSetPad(GPIOC, GPIOC_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_ST_STM32F4_DISCOVERY) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_PIN0 - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_off() (palClearPad(GPIOD, GPIOD_LED4)) - #define search_led_on() (palSetPad(GPIOD, GPIOD_LED4)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#elif defined(BOARD_OLIMEX_STM32_103STK) - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN 0 - #define ONEWIRE_PAD_MODE_IDLE PAL_MODE_INPUT - #define ONEWIRE_PAD_MODE_ACTIVE PAL_MODE_STM32_ALTERNATE_OPENDRAIN - #define search_led_on() (palClearPad(GPIOC, GPIOC_LED)) - #define search_led_off() (palSetPad(GPIOC, GPIOC_LED)) - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#else - #define ONEWIRE_PORT GPIOB - #define ONEWIRE_PIN GPIOB_TACHOMETER - #include "pads.h" - #define ONEWIRE_PAD_MODE_ACTIVE (PAL_MODE_ALTERNATE(2) | PAL_STM32_OTYPE_OPENDRAIN) - #define search_led_on red_led_on - #define search_led_off red_led_off - #define ONEWIRE_MASTER_CHANNEL 2 - #define ONEWIRE_SAMPLE_CHANNEL 3 -#endif +/* + ****************************************************************************** + * DEFINES + ****************************************************************************** + */ /* ****************************************************************************** @@ -99,7 +70,7 @@ static uint8_t testbuf[12]; static int32_t temperature[3]; /* - * Config for underlied PWM driver. + * Config for underlying PWM driver. * Note! It is NOT constant because 1-wire driver needs to change them * during functioning. */ @@ -171,7 +142,7 @@ static void strong_pullup_release(void) { ****************************************************************************** */ -/** +/* * */ void onewireTest(void) { diff --git a/testhal/STM32/STM32F0xx/onewire/onewire_test.h b/testhal/common/onewire/testhal_onewire.h index 1bec2d0..181e09f 100644 --- a/testhal/STM32/STM32F0xx/onewire/onewire_test.h +++ b/testhal/common/onewire/testhal_onewire.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef ONEWIRE_TEST_H_ -#define ONEWIRE_TEST_H_ +#ifndef TESTHAL_ONEWIRE_H_ +#define TESTHAL_ONEWIRE_H_ #ifdef __cplusplus extern "C" { @@ -25,4 +25,4 @@ extern "C" { } #endif -#endif /* ONEWIRE_TEST_H_ */ +#endif /* TESTHAL_ONEWIRE_H_ */ |