# TCL File Generated by Component Editor 13.0sp1 # Mon Oct 14 21:26:59 BST 2013 # DO NOT MODIFY # # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 # 2013.10.14.21:26:59 # # # # request TCL package from ACDS 13.1 # package require -exact qsys 13.1 # # module async_8bit_bus_adapter # set_module_property DESCRIPTION "" set_module_property NAME async_8bit_bus_adapter set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP my_lib set_module_property AUTHOR "" set_module_property DISPLAY_NAME async_8bit_bus_adapter set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property ANALYZE_HDL AUTO set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false # # file sets # add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_8bit_bus_adapter set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false add_fileset_file async_8bit_bus_adapter.vhd VHDL PATH hdl/async_8bit_bus_adapter.vhd TOP_LEVEL_FILE add_fileset SIM_VHDL SIM_VHDL "" "" set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false add_fileset_file async_8bit_bus_adapter_hw.tcl OTHER PATH async_8bit_bus_adapter_hw.tcl # # parameters # # # display items # # # connection point clock # add_interface clock clock end set_interface_property clock clockRate 0 set_interface_property clock ENABLED true set_interface_property clock EXPORT_OF "" set_interface_property clock PORT_NAME_MAP "" set_interface_property clock SVD_ADDRESS_GROUP "" add_interface_port clock clk clk Input 1 # # connection point reset # add_interface reset reset end set_interface_property reset associatedClock clock set_interface_property reset synchronousEdges DEASSERT set_interface_property reset ENABLED true set_interface_property reset EXPORT_OF "" set_interface_property reset PORT_NAME_MAP "" set_interface_property reset SVD_ADDRESS_GROUP "" add_interface_port reset rst_n reset_n Input 1 # # connection point avalon_slave # add_interface avalon_slave avalon end set_interface_property avalon_slave addressUnits WORDS set_interface_property avalon_slave associatedClock clock set_interface_property avalon_slave associatedReset reset set_interface_property avalon_slave bitsPerSymbol 8 set_interface_property avalon_slave burstOnBurstBoundariesOnly false set_interface_property avalon_slave burstcountUnits WORDS set_interface_property avalon_slave explicitAddressSpan 0 set_interface_property avalon_slave holdTime 0 set_interface_property avalon_slave linewrapBursts false set_interface_property avalon_slave maximumPendingReadTransactions 0 set_interface_property avalon_slave readLatency 0 set_interface_property avalon_slave readWaitTime 1 set_interface_property avalon_slave setupTime 0 set_interface_property avalon_slave timingUnits Cycles set_interface_property avalon_slave writeWaitTime 0 set_interface_property avalon_slave ENABLED true set_interface_property avalon_slave EXPORT_OF "" set_interface_property avalon_slave PORT_NAME_MAP "" set_interface_property avalon_slave SVD_ADDRESS_GROUP "" add_interface_port avalon_slave cs_n chipselect_n Input 1 add_interface_port avalon_slave address address Input 16 add_interface_port avalon_slave writedata writedata Input 8 add_interface_port avalon_slave wr_n write_n Input 1 add_interface_port avalon_slave rd_n read_n Input 1 add_interface_port avalon_slave wait_n waitrequest_n Output 1 add_interface_port avalon_slave readdata readdata Output 8 add_interface_port avalon_slave byte_enable_n byteenable_n Input 1 set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 # # connection point eight_bit_bus # add_interface eight_bit_bus conduit end set_interface_property eight_bit_bus associatedClock clock set_interface_property eight_bit_bus associatedReset "" set_interface_property eight_bit_bus ENABLED true set_interface_property eight_bit_bus EXPORT_OF "" set_interface_property eight_bit_bus PORT_NAME_MAP "" set_interface_property eight_bit_bus SVD_ADDRESS_GROUP "" add_interface_port eight_bit_bus b_cs_n export Output 1 add_interface_port eight_bit_bus b_rnw export Output 1 add_interface_port eight_bit_bus b_done_n export Input 1 add_interface_port eight_bit_bus b_addr export Output 16 add_interface_port eight_bit_bus b_data_in export Input 8 add_interface_port eight_bit_bus b_data_out export Output 8 add_interface_port eight_bit_bus b_reset_n export Output 1