From 142b5c54c6feb6110093f6eb128d74e0707f2e11 Mon Sep 17 00:00:00 2001 From: James Date: Tue, 15 Oct 2013 03:21:29 +0100 Subject: missingbit --- .../async_8bit_bus_adapter_hw.tcl | 144 +++++++++++++++++++++ .../hdl/async_8bit_bus_adapter.vhd | 104 +++++++++++++++ 2 files changed, 248 insertions(+) create mode 100644 async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl create mode 100644 async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl new file mode 100644 index 0000000..bbe656e --- /dev/null +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl @@ -0,0 +1,144 @@ +# TCL File Generated by Component Editor 13.0sp1 +# Mon Oct 14 21:26:59 BST 2013 +# DO NOT MODIFY + + +# +# async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 +# 2013.10.14.21:26:59 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module async_8bit_bus_adapter +# +set_module_property DESCRIPTION "" +set_module_property NAME async_8bit_bus_adapter +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP my_lib +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME async_8bit_bus_adapter +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_8bit_bus_adapter +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file async_8bit_bus_adapter.vhd VHDL PATH hdl/async_8bit_bus_adapter.vhd TOP_LEVEL_FILE + +add_fileset SIM_VHDL SIM_VHDL "" "" +set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter +set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file async_8bit_bus_adapter_hw.tcl OTHER PATH async_8bit_bus_adapter_hw.tcl + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset rst_n reset_n Input 1 + + +# +# connection point avalon_slave +# +add_interface avalon_slave avalon end +set_interface_property avalon_slave addressUnits WORDS +set_interface_property avalon_slave associatedClock clock +set_interface_property avalon_slave associatedReset reset +set_interface_property avalon_slave bitsPerSymbol 8 +set_interface_property avalon_slave burstOnBurstBoundariesOnly false +set_interface_property avalon_slave burstcountUnits WORDS +set_interface_property avalon_slave explicitAddressSpan 0 +set_interface_property avalon_slave holdTime 0 +set_interface_property avalon_slave linewrapBursts false +set_interface_property avalon_slave maximumPendingReadTransactions 0 +set_interface_property avalon_slave readLatency 0 +set_interface_property avalon_slave readWaitTime 1 +set_interface_property avalon_slave setupTime 0 +set_interface_property avalon_slave timingUnits Cycles +set_interface_property avalon_slave writeWaitTime 0 +set_interface_property avalon_slave ENABLED true +set_interface_property avalon_slave EXPORT_OF "" +set_interface_property avalon_slave PORT_NAME_MAP "" +set_interface_property avalon_slave SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave cs_n chipselect_n Input 1 +add_interface_port avalon_slave address address Input 16 +add_interface_port avalon_slave writedata writedata Input 8 +add_interface_port avalon_slave wr_n write_n Input 1 +add_interface_port avalon_slave rd_n read_n Input 1 +add_interface_port avalon_slave wait_n waitrequest_n Output 1 +add_interface_port avalon_slave readdata readdata Output 8 +add_interface_port avalon_slave byte_enable_n byteenable_n Input 1 + +set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point eight_bit_bus +# +add_interface eight_bit_bus conduit end +set_interface_property eight_bit_bus associatedClock clock +set_interface_property eight_bit_bus associatedReset "" +set_interface_property eight_bit_bus ENABLED true +set_interface_property eight_bit_bus EXPORT_OF "" +set_interface_property eight_bit_bus PORT_NAME_MAP "" +set_interface_property eight_bit_bus SVD_ADDRESS_GROUP "" + +add_interface_port eight_bit_bus b_cs_n export Output 1 +add_interface_port eight_bit_bus b_rnw export Output 1 +add_interface_port eight_bit_bus b_done_n export Input 1 +add_interface_port eight_bit_bus b_addr export Output 16 +add_interface_port eight_bit_bus b_data_in export Input 8 +add_interface_port eight_bit_bus b_data_out export Output 8 +add_interface_port eight_bit_bus b_reset_n export Output 1 + diff --git a/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd new file mode 100644 index 0000000..2f70731 --- /dev/null +++ b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd @@ -0,0 +1,104 @@ +-- async_8bit_bus_adapter.vhd + +-- This file was auto-generated as a prototype implementation of a module +-- created in component editor. It ties off all outputs to ground and +-- ignores all inputs. It needs to be edited to make it do something +-- useful. +-- +-- This file will not be automatically regenerated. You should check it in +-- to your version control system if you want to keep it. + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity async_8bit_bus_adapter is + generic ( + AUTO_CLOCK_CLOCK_RATE : string := "-1" + ); + port ( + clk : in std_logic := '0'; -- clock.clk + rst_n : in std_logic := '0'; -- reset.reset_n + cs_n : in std_logic := '0'; -- avalon_slave.chipselect_n + address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address + writedata : in std_logic_vector(7 downto 0) := (others => '0'); -- .writedata + wr_n : in std_logic := '0'; -- .write_n + rd_n : in std_logic := '0'; -- .read_n + byte_enable_n : in std_logic := '0'; -- .byte_enable_n + wait_n : out std_logic; -- .waitrequest_n + readdata : out std_logic_vector(7 downto 0); -- .readdata + b_reset_n : out std_logic; -- eight_bit_bus.export + b_cs_n : out std_logic; -- .export + b_rnw : out std_logic; -- .export + b_done_n : in std_logic := '0'; -- .export + b_addr : out std_logic_vector(15 downto 0); -- .export + b_data_in : in std_logic_vector(7 downto 0) := (others => '0'); -- .export + b_data_out : out std_logic_vector(7 downto 0) -- .export + ); +end entity async_8bit_bus_adapter; + +architecture rtl of async_8bit_bus_adapter is + +signal state:std_logic_vector(3 downto 0); +begin + + --readdata <= b_data_in; + b_reset_n <= rst_n; + + -- the avalon bus is a little miserable in that it doesn't cycle CS for each transfer. + -- it does seem to honor the wait for the 2nd transfer so long as you assert it in the + -- correct cycle. + + -- this fsm converts to a more usual asynchronus bus each cycle looks exactly like this + + -- the slave sets b_done_n high + -- time passes + -- the master drops b_cs_n: b_addr, b_rnw and b_data_out are now valid and will remain so until b_cs_n goes high + -- time passes + -- the slave sets b_done_n low: b_data_in show be valid if b_rnw was high + -- time passes + -- the master raises b_cs_n + + + bus_fsm: process (rst_n,clk,cs_n,wr_n,rd_n,b_done_n) begin + if (rst_n ='0') then + state <= "1000"; + wait_n <= '1'; + b_cs_n <='1'; + readdata <= "10101111"; + elsif rising_edge(clk) then + if state = "0001" then + readdata <="00010001"; + if cs_n='0' and b_done_n='1' then + -- so it turns out avalon lies, address isn't valid this cycle + readdata <="00100010"; + state <="0010"; + end if; + elsif state = "0010" then + --address b_rnw and b_dat_out now valid + b_addr <=address; + b_data_out <= writedata; + b_rnw <= wr_n; + b_cs_n<='0'; + readdata <="00110011"; + state <= "0100"; + elsif state = "0100" then + readdata <="01000100"; + if b_done_n ='0' then + b_cs_n <= '1'; + -- data is read during this cycle + readdata <=b_data_in; + wait_n<='1'; + state <="1000"; + end if; + elsif state = "1000" then + wait_n <= '0'; + state <="0001"; + else + state <="1000"; + end if; + end if; + end process; + + +end architecture rtl; -- of async_8bit_bus_adapter -- cgit v1.2.3