diff options
| -rw-r--r-- | async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl | 145 | ||||
| -rw-r--r-- | async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd | 54 |
2 files changed, 0 insertions, 199 deletions
diff --git a/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl b/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl deleted file mode 100644 index 4223d10..0000000 --- a/async_16bit_bus_adapter_hw/async_16bit_bus_adapter_hw.tcl +++ /dev/null @@ -1,145 +0,0 @@ -# TCL File Generated by Component Editor 13.0sp1 -# Mon Oct 14 20:32:15 BST 2013 -# DO NOT MODIFY - - -# -# async_16bit_bus_adapter "async_16bit_bus_adapter" v1.0 -# 2013.10.14.20:32:15 -# -# - -# -# request TCL package from ACDS 13.1 -# -package require -exact qsys 13.1 - - -# -# module async_16bit_bus_adapter -# -set_module_property DESCRIPTION "" -set_module_property NAME async_16bit_bus_adapter -set_module_property VERSION 1.0 -set_module_property INTERNAL false -set_module_property OPAQUE_ADDRESS_MAP true -set_module_property GROUP my_lib -set_module_property AUTHOR "" -set_module_property DISPLAY_NAME async_16bit_bus_adapter -set_module_property INSTANTIATE_IN_SYSTEM_MODULE true -set_module_property EDITABLE true -set_module_property ANALYZE_HDL AUTO -set_module_property REPORT_TO_TALKBACK false -set_module_property ALLOW_GREYBOX_GENERATION false - - -# -# file sets -# -add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" -set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_16bit_bus_adapter -set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -add_fileset_file async_16bit_bus_adapter.vhd VHDL PATH hdl/async_16bit_bus_adapter.vhd TOP_LEVEL_FILE - - -# -# parameters -# -add_parameter AUTO_CLOCK_CLOCK_RATE STRING -1 "" -set_parameter_property AUTO_CLOCK_CLOCK_RATE DEFAULT_VALUE -1 -set_parameter_property AUTO_CLOCK_CLOCK_RATE DISPLAY_NAME AUTO_CLOCK_CLOCK_RATE -set_parameter_property AUTO_CLOCK_CLOCK_RATE WIDTH "" -set_parameter_property AUTO_CLOCK_CLOCK_RATE TYPE STRING -set_parameter_property AUTO_CLOCK_CLOCK_RATE UNITS None -set_parameter_property AUTO_CLOCK_CLOCK_RATE DESCRIPTION "" -set_parameter_property AUTO_CLOCK_CLOCK_RATE HDL_PARAMETER true - - -# -# display items -# - - -# -# connection point clock -# -add_interface clock clock end -set_interface_property clock clockRate 0 -set_interface_property clock ENABLED true -set_interface_property clock EXPORT_OF "" -set_interface_property clock PORT_NAME_MAP "" -set_interface_property clock SVD_ADDRESS_GROUP "" - -add_interface_port clock clk clk Input 1 - - -# -# connection point avalon_slave -# -add_interface avalon_slave avalon end -set_interface_property avalon_slave addressUnits WORDS -set_interface_property avalon_slave associatedClock clock -set_interface_property avalon_slave associatedReset reset -set_interface_property avalon_slave bitsPerSymbol 8 -set_interface_property avalon_slave burstOnBurstBoundariesOnly false -set_interface_property avalon_slave burstcountUnits WORDS -set_interface_property avalon_slave explicitAddressSpan 0 -set_interface_property avalon_slave holdTime 0 -set_interface_property avalon_slave linewrapBursts false -set_interface_property avalon_slave maximumPendingReadTransactions 0 -set_interface_property avalon_slave readLatency 0 -set_interface_property avalon_slave readWaitTime 1 -set_interface_property avalon_slave setupTime 0 -set_interface_property avalon_slave timingUnits Cycles -set_interface_property avalon_slave writeWaitTime 0 -set_interface_property avalon_slave ENABLED true -set_interface_property avalon_slave EXPORT_OF "" -set_interface_property avalon_slave PORT_NAME_MAP "" -set_interface_property avalon_slave SVD_ADDRESS_GROUP "" - -add_interface_port avalon_slave cs_n chipselect_n Input 1 -add_interface_port avalon_slave address address Input 16 -add_interface_port avalon_slave writedata writedata Input 16 -add_interface_port avalon_slave wr_n write_n Input 1 -add_interface_port avalon_slave rd_n read_n Input 1 -add_interface_port avalon_slave wait_n waitrequest_n Output 1 -add_interface_port avalon_slave readdata readdata Output 16 -set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 -set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 -set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 -set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 - - -# -# connection point sbb -# -add_interface sbb conduit end -set_interface_property sbb associatedClock clock -set_interface_property sbb associatedReset "" -set_interface_property sbb ENABLED true -set_interface_property sbb EXPORT_OF "" -set_interface_property sbb PORT_NAME_MAP "" -set_interface_property sbb SVD_ADDRESS_GROUP "" - -add_interface_port sbb b_reset_n export Output 1 -add_interface_port sbb b_cs_n export Output 1 -add_interface_port sbb b_rnw export Output 1 -add_interface_port sbb b_wait_n export Input 1 -add_interface_port sbb b_addr export Output 16 -add_interface_port sbb b_data_in export Input 16 -add_interface_port sbb b_data_out export Output 16 - - -# -# connection point reset -# -add_interface reset reset end -set_interface_property reset associatedClock clock -set_interface_property reset synchronousEdges DEASSERT -set_interface_property reset ENABLED true -set_interface_property reset EXPORT_OF "" -set_interface_property reset PORT_NAME_MAP "" -set_interface_property reset SVD_ADDRESS_GROUP "" - -add_interface_port reset rst_n reset_n Input 1 - diff --git a/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd b/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd deleted file mode 100644 index 715123f..0000000 --- a/async_16bit_bus_adapter_hw/hdl/async_16bit_bus_adapter.vhd +++ /dev/null @@ -1,54 +0,0 @@ --- async_16bit_bus_adapter.vhd - --- This file was auto-generated as a prototype implementation of a module --- created in component editor. It ties off all outputs to ground and --- ignores all inputs. It needs to be edited to make it do something --- useful. --- --- This file will not be automatically regenerated. You should check it in --- to your version control system if you want to keep it. - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity async_16bit_bus_adapter is - generic ( - AUTO_CLOCK_CLOCK_RATE : string := "-1" - ); - port ( - clk : in std_logic := '0'; -- clock.clk - rst_n : in std_logic := '0'; -- reset.reset_n - cs_n : in std_logic := '0'; -- avalon_slave.chipselect_n - address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address - writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata - wr_n : in std_logic := '0'; -- .write_n - rd_n : in std_logic := '0'; -- .read_n - wait_n : out std_logic; -- .waitrequest_n - readdata : out std_logic_vector(15 downto 0); -- .readdata - b_reset_n : out std_logic; -- eight_bit_bus.export - b_cs_n : out std_logic; -- .export - b_rnw : out std_logic; -- .export - b_wait_n : in std_logic := '0'; -- .export - b_addr : out std_logic_vector(15 downto 0); -- .export - b_data_in : in std_logic_vector(15 downto 0) := (others => '0'); -- .export - b_data_out : out std_logic_vector(15 downto 0) -- .export - ); -end entity async_16bit_bus_adapter; - -architecture rtl of async_16bit_bus_adapter is - -signal state:std_logic_vector(2 downto 0); -begin - - b_addr <= address; - readdata <= b_data_in; - b_data_out <= writedata; - - b_reset_n <= rst_n; - b_cs_n <= cs_n or ( wr_n and rd_n ); - b_rnw <= wr_n; - wait_n <= b_wait_n; - - -end architecture rtl; -- of async_16bit_bus_adapter |