library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity sdram_ctrl is
port
(	
	clock_50	:	in std_logic;
	reset_n		:	in std_logic;

	b_cs_n		:	in std_logic;
	b_rd_n		:	in std_logic;
	b_wr_n		:	in std_logic;

	b_wait_n	:	out std_logic;

	b_addr		:	in std_logic_vector(15 downto 0);
	b_data		:	inout std_logic_vector(7 downto 0);


	sdram_clk	:	out std_logic;

	sdram_cs_n	:	out std_logic;
	sdram_cas_n	:	out std_logic;
	sdram_ras_n	:	out std_logic;
	sdram_we_n	:	out std_logic;
	sdram_cke	:	out std_logic;

	sdram_addr	:	out std_logic_vector(12 downto 0);
	sdram_ba	:	out std_logic_vector(1 downto 0);

	sdram_dq	:	inout std_logic_vector(15 downto 0);
	sdram_dqm	:	out std_logic_vector(1 downto 0)
);
end entity;

architecture rtl of sdram_ctrl is


begin

sdram_clk <=clock_50;

end;