library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity sdram is
port (
	clock_50	:	in	std_logic;	
	reset_n		:	in	std_logic;
	seven_seg	:	out 	std_logic_vector(7 downto 0);

	sdram_clk	:	out std_logic;

	sdram_cs_n	:	out std_logic;
	sdram_cas_n	:	out std_logic;
	sdram_ras_n	:	out std_logic;
	sdram_we_n	:	out std_logic;
	sdram_cke	:	out std_logic;

	sdram_addr	:	out std_logic_vector(12 downto 0);
	sdram_ba	:	out std_logic_vector(1 downto 0);

	sdram_dq	:	inout std_logic_vector(15 downto 0);
	sdram_dqm	:	out std_logic_vector(1 downto 0)
);
end entity;

architecture rtl of sdram is

component pll50125 IS
        PORT
        (
                areset          : IN STD_LOGIC  := '0';
                inclk0          : IN STD_LOGIC  := '0';
                c0              : OUT STD_LOGIC ;
                locked          : OUT STD_LOGIC
        );
end component;



component sdram_mcu is
	port (
		clk_clk		: in    std_logic                     := 'X';             -- clk
		reset_reset_n	: in    std_logic                     := 'X';             -- reset_n
		pio_0_d_export	: out   std_logic_vector(7 downto 0);                     -- export
		ebb_0_cs_n	: out   std_logic;                                        -- cs_n
		ebb_0_rd_n	: out   std_logic;                                        -- rd_n
		ebb_0_wr_n	: out   std_logic;                                        -- wr_n
		ebb_0_wait_n	: in    std_logic                     := 'X';             -- wait_n
		ebb_0_addr	: out   std_logic_vector(15 downto 0);                    -- addr
		ebb_0_data	: inout std_logic_vector(7 downto 0)  := (others => 'X')  -- data
	);
end component sdram_mcu;


component sdram_ctrl is
	port
	(	
		clock_50	:	in std_logic;
		reset_n		:	in std_logic;

		b_cs_n		:	in std_logic;
		b_rd_n		:	in std_logic;
		b_wr_n		:	in std_logic;

		b_wait_n	:	out std_logic;

		b_addr		:	in std_logic_vector(15 downto 0);
		b_data		:	inout std_logic_vector(7 downto 0);


		sdram_clk	:	out std_logic;

		sdram_cs_n	:	out std_logic;
		sdram_cas_n	:	out std_logic;
		sdram_ras_n	:	out std_logic;
		sdram_we_n	:	out std_logic;
		sdram_cke	:	out std_logic;

		sdram_addr	:	out std_logic_vector(12 downto 0);
		sdram_ba	:	out std_logic_vector(1 downto 0);

		sdram_dq	:	inout std_logic_vector(15 downto 0);
		sdram_dqm	:	out std_logic_vector(1 downto 0)
	);
end component;

signal b_addr : std_logic_vector(15 downto 0);
signal b_data : std_logic_vector(7 downto 0);
signal b_cs_n : std_logic;
signal b_rd_n : std_logic;
signal b_wr_n : std_logic;
signal b_wait_n : std_logic;

signal pll_reset : std_logic;
signal clock_100 : std_logic;
signal pll_locked : std_logic;

signal global_reset_n : std_logic;


begin

        pll:   pll50125 port map (
                pll_reset,
                clock_50,
                clock_100,
                pll_locked );

   	u0 : component sdram_mcu port map (
		clk_clk        => clock_50,        --     clk.clk
		reset_reset_n  => global_reset_n,  --   reset.reset_n
		pio_0_d_export => seven_seg, -- pio_0_d.export
		ebb_0_cs_n      => b_cs_n,      --    ebb_0.cs_n
		ebb_0_rd_n      => b_rd_n,      --        .rd_n
		ebb_0_wr_n      => b_wr_n,      --        .wr_n
		ebb_0_wait_n    => b_wait_n,    --        .wait_n
		ebb_0_addr      => b_addr,      --        .addr
		ebb_0_data      => b_data       --        .data
	);


	sdram_ctrl0: sdram_ctrl port map (
		clock_50,
		global_reset_n,

		b_cs_n,
		b_rd_n,
		b_wr_n,

		b_wait_n,

		b_addr,
		b_data,

		sdram_clk,

		sdram_cs_n,
		sdram_cas_n,
		sdram_ras_n,
		sdram_we_n,
		sdram_cke,

		sdram_addr,
		sdram_ba,

		sdram_dq,
		sdram_dqm
	);

	pll_reset <= '0';
	global_reset_n <= reset_n and pll_locked;
	
end architecture;