From 7fbec04d3aaca8909f89b325e125e46fe218e3be Mon Sep 17 00:00:00 2001 From: James Date: Sun, 13 Oct 2013 12:40:04 +0100 Subject: fish --- sdram.vhd | 145 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 128 insertions(+), 17 deletions(-) (limited to 'sdram.vhd') diff --git a/sdram.vhd b/sdram.vhd index 6ca4721..4dd27b2 100644 --- a/sdram.vhd +++ b/sdram.vhd @@ -1,17 +1,128 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity sdram is -port ( - clock_50 : in std_logic; - DI : in std_logic_vector(6 downto 0); - fish : out std_logic; - ); -end entity; - -architecture rtl of saa5050 is - -begin - fish <= clock_50; -end architecture; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity sdram is +port ( + clock_50 : in std_logic; + reset_n : in std_logic; + seven_seg : out std_logic_vector(7 downto 0); + + sdram_clk : out std_logic; + + sdram_cs_n : out std_logic; + sdram_cas_n : out std_logic; + sdram_ras_n : out std_logic; + sdram_we_n : out std_logic; + sdram_cke : out std_logic; + + sdram_addr : out std_logic_vector(12 downto 0); + sdram_ba : out std_logic_vector(1 downto 0); + + sdram_dq : inout std_logic_vector(15 downto 0); + sdram_dqm : out std_logic_vector(1 downto 0) +); +end entity; + +architecture rtl of sdram is + + +component sdram_mcu is + port ( + clk_clk : in std_logic := 'X'; -- clk + reset_reset_n : in std_logic := 'X'; -- reset_n + pio_0_d_export : out std_logic_vector(7 downto 0); -- export + ebb_0_cs_n : out std_logic; -- cs_n + ebb_0_rd_n : out std_logic; -- rd_n + ebb_0_wr_n : out std_logic; -- wr_n + ebb_0_wait_n : in std_logic := 'X'; -- wait_n + ebb_0_addr : out std_logic_vector(15 downto 0); -- addr + ebb_0_data : inout std_logic_vector(7 downto 0) := (others => 'X') -- data + ); +end component sdram_mcu; + + +component sdram_ctrl is + port + ( + clock_50 : in std_logic; + reset_n : in std_logic; + + b_cs_n : in std_logic; + b_rd_n : in std_logic; + b_wr_n : in std_logic; + + b_wait_n : out std_logic; + + b_addr : in std_logic_vector(15 downto 0); + b_data : inout std_logic_vector(7 downto 0); + + + sdram_clk : out std_logic; + + sdram_cs_n : out std_logic; + sdram_cas_n : out std_logic; + sdram_ras_n : out std_logic; + sdram_we_n : out std_logic; + sdram_cke : out std_logic; + + sdram_addr : out std_logic_vector(12 downto 0); + sdram_ba : out std_logic_vector(1 downto 0); + + sdram_dq : inout std_logic_vector(15 downto 0); + sdram_dqm : out std_logic_vector(1 downto 0) + ); +end component; + +signal b_addr : std_logic_vector(15 downto 0); +signal b_data : std_logic_vector(7 downto 0); +signal b_cs_n : std_logic; +signal b_rd_n : std_logic; +signal b_wr_n : std_logic; +signal b_wait_n : std_logic; + +begin + + + u0 : component sdram_mcu port map ( + clk_clk => clock_50, -- clk.clk + reset_reset_n => reset_n, -- reset.reset_n + pio_0_d_export => seven_seg, -- pio_0_d.export + ebb_0_cs_n => b_cs_n, -- ebb_0.cs_n + ebb_0_rd_n => b_rd_n, -- .rd_n + ebb_0_wr_n => b_wr_n, -- .wr_n + ebb_0_wait_n => b_wait_n, -- .wait_n + ebb_0_addr => b_addr, -- .addr + ebb_0_data => b_data -- .data + ); + + + sdram_ctrl0: sdram_ctrl port map ( + clock_50, + reset_n, + + b_cs_n, + b_rd_n, + b_wr_n, + + b_wait_n, + + b_addr, + b_data, + + sdram_clk, + + sdram_cs_n, + sdram_cas_n, + sdram_ras_n, + sdram_we_n, + sdram_cke, + + sdram_addr, + sdram_ba, + + sdram_dq, + sdram_dqm + ); + +end architecture; -- cgit v1.2.3