From 53023c205537e8f4da07f01d8ecf0e9edbcb94a6 Mon Sep 17 00:00:00 2001
From: James <james.mckenzie@citrix.com>
Date: Mon, 14 Oct 2013 15:05:12 +0100
Subject: fish

---
 sdram.vhd | 68 +++++++++++++++++++++++++++++++++------------------------------
 1 file changed, 36 insertions(+), 32 deletions(-)

(limited to 'sdram.vhd')

diff --git a/sdram.vhd b/sdram.vhd
index 9acff22..f899f17 100644
--- a/sdram.vhd
+++ b/sdram.vhd
@@ -2,6 +2,9 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
+library work;
+use work.sdram_util.ALL;
+
 entity sdram is
 port (
 	clock_50	:	in	std_logic;	
@@ -53,43 +56,43 @@ component sdram_mcu is
 end component sdram_mcu;
 
 
-component sdram_ctrl is
-	port
-	(	
-		clock_50	:	in std_logic;
-		reset_n		:	in std_logic;
+entity sdram_ctrl is
+  port
+  (  
+    clock_100  :  in std_logic;
+    reset_n    :  in std_logic;
 
-		b_cs_n		:	in std_logic;
-		b_rd_n		:	in std_logic;
-		b_wr_n		:	in std_logic;
+    bus_cs_n    :  in std_logic;
+    bus_rnw    :  in std_logic;
 
-		b_wait_n	:	out std_logic;
+    bus_wait_n  :  out std_logic;
 
-		b_addr		:	in std_logic_vector(15 downto 0);
-		b_data		:	inout std_logic_vector(7 downto 0);
+    bus_addr    :  in addr_t;
+    bus_data_in    :  in data_t;
+    bus_data_out    :  out data_t;
 
+    sdram_clk  :  out std_logic;
+    sdram_cke  :  out std_logic;
 
-		sdram_clk	:	out std_logic;
+    sdram_cs_n  :  out std_logic;
 
-		sdram_cs_n	:	out std_logic;
-		sdram_cas_n	:	out std_logic;
-		sdram_ras_n	:	out std_logic;
-		sdram_we_n	:	out std_logic;
-		sdram_cke	:	out std_logic;
+    sdram_cas_n  :  out std_logic;
+    sdram_ras_n  :  out std_logic;
+    sdram_we_n  :  out std_logic;
 
-		sdram_addr	:	out std_logic_vector(12 downto 0);
-		sdram_ba	:	out std_logic_vector(1 downto 0);
+    sdram_addr  :  out std_logic_vector(12 downto 0);
+    sdram_ba  :  out std_logic_vector(1 downto 0);
 
-		sdram_dq	:	inout std_logic_vector(15 downto 0);
-		sdram_dqm	:	out std_logic_vector(1 downto 0)
-	);
-end component;
+    sdram_dq  :  inout data_t;
+    sdram_dqm  :  out dqm_t
+  );
+end entity;
 
-signal b_addr : std_logic_vector(15 downto 0);
-signal b_data : std_logic_vector(7 downto 0);
+
+signal b_addr : addr_t;
+signal b_data : data_t;
 signal b_cs_n : std_logic;
-signal b_rd_n : std_logic;
-signal b_wr_n : std_logic;
+signal b_rnw : std_logic;
 signal b_wait_n : std_logic;
 
 signal pll_reset : std_logic;
@@ -121,25 +124,26 @@ begin
 
 
 	sdram_ctrl0: sdram_ctrl port map (
-		clock_50,
+		clock_100,
 		global_reset_n,
 
 		b_cs_n,
-		b_rd_n,
-		b_wr_n,
+		b_rnw,
 
 		b_wait_n,
+		sdram_cke,
 
 		b_addr,
-		b_data,
+		b_data_in,
+		b_data_out,
 
 		sdram_clk,
+		sdram_cke,
 
 		sdram_cs_n,
 		sdram_cas_n,
 		sdram_ras_n,
 		sdram_we_n,
-		sdram_cke,
 
 		sdram_addr,
 		sdram_ba,
-- 
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