From 16af4b953306063c2aed52ab2ecde07e0bc6b5e4 Mon Sep 17 00:00:00 2001
From: James <james.mckenzie@citrix.com>
Date: Mon, 14 Oct 2013 19:06:11 +0100
Subject: works!

---
 sdram.vhd | 49 ++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 40 insertions(+), 9 deletions(-)

(limited to 'sdram.vhd')

diff --git a/sdram.vhd b/sdram.vhd
index e9373da..f363ea3 100644
--- a/sdram.vhd
+++ b/sdram.vhd
@@ -45,13 +45,14 @@ component sdram_mcu is
 	port (
 		clk_clk		: in    std_logic                     := 'X';             -- clk
 		reset_reset_n	: in    std_logic                     := 'X';             -- reset_n
-		pio_0_d_export	: out   std_logic_vector(7 downto 0);                     -- export
+--		pio_0_d_export	: out   std_logic_vector(7 downto 0);                     -- export
 		ebb_0_cs_n	: out   std_logic;                                        -- cs_n
 		ebb_0_rnw	: out   std_logic;                                        -- rnw
 		ebb_0_wait_n	: in    std_logic                     := 'X';             -- wait_n
 		ebb_0_addr	: out   std_logic_vector(15 downto 0);                    -- addr
 		ebb_0_data_in	: in    std_logic_vector(7 downto 0)  := (others => 'X'); -- data_in
-		ebb_0_data_out	: out   std_logic_vector(7 downto 0)                      -- data_out
+		ebb_0_data_out	: out   std_logic_vector(7 downto 0);                     -- data_out
+		ebb_0_reset_n	: out   std_logic                                        -- reset_n
 	);
 end component sdram_mcu;
 
@@ -83,7 +84,9 @@ component sdram_ctrl is
     sdram_ba  :  out std_logic_vector(1 downto 0);
 
     sdram_dq  :  inout data_t;
-    sdram_dqm  :  out dqm_t
+    sdram_dqm  :  out dqm_t;
+
+    debug  :  out std_logic_vector(7 downto 0)
   );
 end component;
 
@@ -99,10 +102,15 @@ signal b_rnw : std_logic;
 signal b_wait_n : std_logic;
 
 signal pll_reset : std_logic;
+signal mcu_clock : std_logic;
 signal clock_100 : std_logic;
 signal pll_locked : std_logic;
+signal debug : std_logic_vector(7 downto 0);
 
 signal global_reset_n : std_logic;
+signal b_reset_n : std_logic;
+
+signal buf8 : std_logic_vector(7 downto 0);
 
 
 begin
@@ -113,16 +121,19 @@ begin
                 clock_100,
                 pll_locked );
 
+	mcu_clock <= clock_50;
+
    	u0 : component sdram_mcu port map (
-		clk_clk        => clock_100,        --     clk.clk
+		clk_clk        => mcu_clock,        --     clk.clk
 		reset_reset_n  => global_reset_n,  --   reset.reset_n
-		pio_0_d_export => seven_seg, -- pio_0_d.export
+--		pio_0_d_export => seven_seg, -- pio_0_d.export
 		ebb_0_cs_n      => b_cs_n,      --    ebb_0.cs_n
 		ebb_0_rnw       => b_rnw,      --        .rnw
 		ebb_0_wait_n    => b_wait_n,    --        .wait_n
 		ebb_0_addr      => b_addr16,      --        .addr
 		ebb_0_data_in   => b_data_in8,   --        .data
-		ebb_0_data_out  => b_data_out8   --        .data
+		ebb_0_data_out  => b_data_out8,   --        .data
+		ebb_0_reset_n   => b_reset_n  
 	);
 
  	-- bodge buses together
@@ -130,14 +141,32 @@ begin
 	b_data_in(7 downto 0) <= b_data_out8;
 	b_data_in(15 downto 8) <= (others =>'0');
 
+
+	ss_process: process (global_reset_n,b_rnw,b_cs_n,b_addr16) begin
+		if l2b_al(global_reset_n) then
+			buf8<=(others => '0');
+		elsif falling_edge(b_cs_n) and l2b_al(b_rnw) then
+			buf8 <= b_data_out8;
+		end if;
+	end process;
+
+--	seven_seg <= buf8;
+
+	seven_seg <= debug;
+	--b_data_in8 <= buf8;
+	--b_wait_n <= '1';
  	b_data_in8  <= b_data_out(7 downto 0);
+	--seven_seg <= b_data_in8;	
+  	--b_data_in8 <= "01011010";
+
 	b_addr(15 downto 0) <= b_addr16;
 	b_addr(23 downto 16) <= (others => '0');
 
 
+
 	sdram_ctrl0: sdram_ctrl port map (
-		clock_100 => clock_100,
-		reset_n => global_reset_n,
+		clock_100 => clock_50,
+		reset_n => b_reset_n,
 
 		bus_cs_n => b_cs_n,
 		bus_rnw => b_rnw,
@@ -160,7 +189,9 @@ begin
 		sdram_ba => sdram_ba,
 
 		sdram_dq => sdram_dq,
-		sdram_dqm => sdram_dqm
+		sdram_dqm => sdram_dqm,
+
+		debug => debug
 	);
 
 	pll_reset <= '0';
-- 
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