From 7fbec04d3aaca8909f89b325e125e46fe218e3be Mon Sep 17 00:00:00 2001 From: James Date: Sun, 13 Oct 2013 12:40:04 +0100 Subject: fish --- async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v | 44 +++++++ .../async_8bit_bus_adapter.vhd | 53 ++++++++ .../async_8bit_bus_adapter_hw.tcl | 141 +++++++++++++++++++++ .../async_8bit_bus_adapter_hw.tcl~ | 136 ++++++++++++++++++++ 4 files changed, 374 insertions(+) create mode 100644 async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v create mode 100644 async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd create mode 100644 async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl create mode 100644 async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ (limited to 'async_8bit_bus_adapter_hw') diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v new file mode 100644 index 0000000..bfd69c3 --- /dev/null +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v @@ -0,0 +1,44 @@ +// async_8bit_bus_adapter.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module async_8bit_bus_adapter #( + parameter AUTO_CLOCK_CLOCK_RATE = "-1" + ) ( + input wire clk, // clock.clk + input wire rst_n, // reset.reset_n + input wire cs_n, // avalon_slave.chipselect_n + input wire [15:0] address, // .address + input wire [7:0] writedata, // .writedata + input wire wr_n, // .write_n + input wire rd_n, // .read_n + output wire wait_n, // .waitrequest_n + output wire [7:0] readdata, // .readdata + output wire b_cs_n, // eight_bit_bus.export + output wire b_rd_n, // .export + output wire b_wr_n, // .export + input wire b_wait_n, // .export + output wire [15:0] b_addr, // .export + inout wire [7:0] b_data // .export + ); + + // TODO: Auto-generated HDL template + + assign readdata = 8'b00000000; + + assign b_cs_n = 1'b0; + + assign b_wr_n = 1'b0; + + assign b_rd_n = 1'b0; + + assign b_addr = 16'b0000000000000000; + +endmodule diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd new file mode 100644 index 0000000..5983f63 --- /dev/null +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd @@ -0,0 +1,53 @@ +-- async_8bit_bus_adapter.vhd + +-- This file was auto-generated as a prototype implementation of a module +-- created in component editor. It ties off all outputs to ground and +-- ignores all inputs. It needs to be edited to make it do something +-- useful. +-- +-- This file will not be automatically regenerated. You should check it in +-- to your version control system if you want to keep it. + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity async_8bit_bus_adapter is + generic ( + AUTO_CLOCK_CLOCK_RATE : string := "-1" + ); + port ( + clk : in std_logic := '0'; -- clock.clk + rst_n : in std_logic := '0'; -- reset.reset_n + cs_n : in std_logic := '0'; -- avalon_slave.chipselect_n + address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address + writedata : in std_logic_vector(7 downto 0) := (others => '0'); -- .writedata + wr_n : in std_logic := '0'; -- .write_n + rd_n : in std_logic := '0'; -- .read_n + wait_n : out std_logic; -- .waitrequest_n + readdata : out std_logic_vector(7 downto 0); -- .readdata + b_cs_n : out std_logic; -- eight_bit_bus.export + b_rd_n : out std_logic; -- .export + b_wr_n : out std_logic; -- .export + b_wait_n : in std_logic := '0'; -- .export + b_addr : out std_logic; -- .export + b_data : inout std_logic := '0' -- .export + ); +end entity async_8bit_bus_adapter; + +architecture rtl of async_8bit_bus_adapter is +begin + + -- TODO: Auto-generated HDL template + + readdata <= "00000000"; + + b_cs_n <= '0'; + + b_wr_n <= '0'; + + b_rd_n <= '0'; + + b_addr <= '0'; + +end architecture rtl; -- of async_8bit_bus_adapter diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl new file mode 100644 index 0000000..d4f8021 --- /dev/null +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl @@ -0,0 +1,141 @@ +# TCL File Generated by Component Editor 13.0sp1 +# Sun Oct 13 12:34:21 BST 2013 +# DO NOT MODIFY + + +# +# async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 +# 2013.10.13.12:34:21 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module async_8bit_bus_adapter +# +set_module_property DESCRIPTION "" +set_module_property NAME async_8bit_bus_adapter +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP my_lib +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME async_8bit_bus_adapter +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_8bit_bus_adapter +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file async_8bit_bus_adapter.v VERILOG PATH async_8bit_bus_adapter.v TOP_LEVEL_FILE + +add_fileset SIM_VHDL SIM_VHDL "" "" +set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter +set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file async_8bit_bus_adapter_hw.tcl OTHER PATH async_8bit_bus_adapter_hw.tcl + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset rst_n reset_n Input 1 + + +# +# connection point avalon_slave +# +add_interface avalon_slave avalon end +set_interface_property avalon_slave addressUnits WORDS +set_interface_property avalon_slave associatedClock clock +set_interface_property avalon_slave associatedReset reset +set_interface_property avalon_slave bitsPerSymbol 8 +set_interface_property avalon_slave burstOnBurstBoundariesOnly false +set_interface_property avalon_slave burstcountUnits WORDS +set_interface_property avalon_slave explicitAddressSpan 0 +set_interface_property avalon_slave holdTime 0 +set_interface_property avalon_slave linewrapBursts false +set_interface_property avalon_slave maximumPendingReadTransactions 0 +set_interface_property avalon_slave readLatency 0 +set_interface_property avalon_slave readWaitTime 1 +set_interface_property avalon_slave setupTime 0 +set_interface_property avalon_slave timingUnits Cycles +set_interface_property avalon_slave writeWaitTime 0 +set_interface_property avalon_slave ENABLED true +set_interface_property avalon_slave EXPORT_OF "" +set_interface_property avalon_slave PORT_NAME_MAP "" +set_interface_property avalon_slave SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave cs_n chipselect_n Input 1 +add_interface_port avalon_slave address address Input 16 +add_interface_port avalon_slave writedata writedata Input 8 +add_interface_port avalon_slave wr_n write_n Input 1 +add_interface_port avalon_slave rd_n read_n Input 1 +add_interface_port avalon_slave wait_n waitrequest_n Output 1 +add_interface_port avalon_slave readdata readdata Output 8 +set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point eight_bit_bus +# +add_interface eight_bit_bus conduit end +set_interface_property eight_bit_bus associatedClock clock +set_interface_property eight_bit_bus associatedReset "" +set_interface_property eight_bit_bus ENABLED true +set_interface_property eight_bit_bus EXPORT_OF "" +set_interface_property eight_bit_bus PORT_NAME_MAP "" +set_interface_property eight_bit_bus SVD_ADDRESS_GROUP "" + +add_interface_port eight_bit_bus b_cs_n export Output 1 +add_interface_port eight_bit_bus b_rd_n export Output 1 +add_interface_port eight_bit_bus b_wr_n export Output 1 +add_interface_port eight_bit_bus b_wait_n export Input 1 +add_interface_port eight_bit_bus b_addr export Output 16 +add_interface_port eight_bit_bus b_data export Bidir 8 + diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ new file mode 100644 index 0000000..bd77527 --- /dev/null +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ @@ -0,0 +1,136 @@ +# TCL File Generated by Component Editor 13.0sp1 +# Sun Oct 13 12:34:12 BST 2013 +# DO NOT MODIFY + + +# +# async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 +# 2013.10.13.12:34:12 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module async_8bit_bus_adapter +# +set_module_property DESCRIPTION "" +set_module_property NAME async_8bit_bus_adapter +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP my_lib +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME async_8bit_bus_adapter +set_module_property INSTANTIATE_IN_SYSTEM_MODULE false +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset SIM_VHDL SIM_VHDL "" "" +set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter +set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file async_8bit_bus_adapter_hw.tcl OTHER PATH async_8bit_bus_adapter_hw.tcl + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset rst_n reset_n Input 1 + + +# +# connection point avalon_slave +# +add_interface avalon_slave avalon end +set_interface_property avalon_slave addressUnits WORDS +set_interface_property avalon_slave associatedClock clock +set_interface_property avalon_slave associatedReset reset +set_interface_property avalon_slave bitsPerSymbol 8 +set_interface_property avalon_slave burstOnBurstBoundariesOnly false +set_interface_property avalon_slave burstcountUnits WORDS +set_interface_property avalon_slave explicitAddressSpan 0 +set_interface_property avalon_slave holdTime 0 +set_interface_property avalon_slave linewrapBursts false +set_interface_property avalon_slave maximumPendingReadTransactions 0 +set_interface_property avalon_slave readLatency 0 +set_interface_property avalon_slave readWaitTime 1 +set_interface_property avalon_slave setupTime 0 +set_interface_property avalon_slave timingUnits Cycles +set_interface_property avalon_slave writeWaitTime 0 +set_interface_property avalon_slave ENABLED true +set_interface_property avalon_slave EXPORT_OF "" +set_interface_property avalon_slave PORT_NAME_MAP "" +set_interface_property avalon_slave SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave cs_n chipselect_n Input 1 +add_interface_port avalon_slave address address Input 16 +add_interface_port avalon_slave writedata writedata Input 8 +add_interface_port avalon_slave wr_n write_n Input 1 +add_interface_port avalon_slave rd_n read_n Input 1 +add_interface_port avalon_slave wait_n waitrequest_n Output 1 +add_interface_port avalon_slave readdata readdata Output 8 +set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point eight_bit_bus +# +add_interface eight_bit_bus conduit end +set_interface_property eight_bit_bus associatedClock clock +set_interface_property eight_bit_bus associatedReset "" +set_interface_property eight_bit_bus ENABLED true +set_interface_property eight_bit_bus EXPORT_OF "" +set_interface_property eight_bit_bus PORT_NAME_MAP "" +set_interface_property eight_bit_bus SVD_ADDRESS_GROUP "" + +add_interface_port eight_bit_bus b_cs_n export Output 1 +add_interface_port eight_bit_bus b_rd_n export Output 1 +add_interface_port eight_bit_bus b_wr_n export Output 1 +add_interface_port eight_bit_bus b_wait_n export Input 1 +add_interface_port eight_bit_bus b_addr export Output 16 +add_interface_port eight_bit_bus b_data export Bidir 8 + -- cgit v1.2.3