From 53023c205537e8f4da07f01d8ecf0e9edbcb94a6 Mon Sep 17 00:00:00 2001 From: James Date: Mon, 14 Oct 2013 15:05:12 +0100 Subject: fish --- async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl') diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl index d4f8021..d4b4688 100644 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Sun Oct 13 12:34:21 BST 2013 +# Mon Oct 14 15:03:03 BST 2013 # DO NOT MODIFY # # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 -# 2013.10.13.12:34:21 +# 2013.10.14.15:03:03 # # @@ -39,7 +39,7 @@ set_module_property ALLOW_GREYBOX_GENERATION false add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_8bit_bus_adapter set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false -add_fileset_file async_8bit_bus_adapter.v VERILOG PATH async_8bit_bus_adapter.v TOP_LEVEL_FILE +add_fileset_file async_8bit_bus_adapter.vhd VHDL PATH hdl/async_8bit_bus_adapter.vhd TOP_LEVEL_FILE add_fileset SIM_VHDL SIM_VHDL "" "" set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter @@ -137,5 +137,6 @@ add_interface_port eight_bit_bus b_rd_n export Output 1 add_interface_port eight_bit_bus b_wr_n export Output 1 add_interface_port eight_bit_bus b_wait_n export Input 1 add_interface_port eight_bit_bus b_addr export Output 16 -add_interface_port eight_bit_bus b_data export Bidir 8 +add_interface_port eight_bit_bus b_data_in export Input 8 +add_interface_port eight_bit_bus b_data_out export Output 8 -- cgit v1.2.3