From dee10e9511e5d21ae1c4c02b6b786850b3013b88 Mon Sep 17 00:00:00 2001 From: James Date: Mon, 14 Oct 2013 15:17:08 +0100 Subject: fish --- async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl | 7 +++---- async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ | 7 +++---- async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd | 7 ++----- sdram.vhd | 7 +++---- sdram_mcu.qsys | 10 +++++----- 5 files changed, 16 insertions(+), 22 deletions(-) diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl index d4b4688..0b52d75 100644 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Mon Oct 14 15:03:03 BST 2013 +# Mon Oct 14 15:16:40 BST 2013 # DO NOT MODIFY # # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 -# 2013.10.14.15:03:03 +# 2013.10.14.15:16:40 # # @@ -133,8 +133,7 @@ set_interface_property eight_bit_bus PORT_NAME_MAP "" set_interface_property eight_bit_bus SVD_ADDRESS_GROUP "" add_interface_port eight_bit_bus b_cs_n export Output 1 -add_interface_port eight_bit_bus b_rd_n export Output 1 -add_interface_port eight_bit_bus b_wr_n export Output 1 +add_interface_port eight_bit_bus b_rnw export Output 1 add_interface_port eight_bit_bus b_wait_n export Input 1 add_interface_port eight_bit_bus b_addr export Output 16 add_interface_port eight_bit_bus b_data_in export Input 8 diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ index 5171d01..19ea7ae 100644 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Mon Oct 14 15:01:25 BST 2013 +# Mon Oct 14 15:03:03 BST 2013 # DO NOT MODIFY # # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 -# 2013.10.14.15:01:25 +# 2013.10.14.15:03:03 # # @@ -133,8 +133,7 @@ set_interface_property eight_bit_bus PORT_NAME_MAP "" set_interface_property eight_bit_bus SVD_ADDRESS_GROUP "" add_interface_port eight_bit_bus b_cs_n export Output 1 -add_interface_port eight_bit_bus b_rd_n export Output 1 -add_interface_port eight_bit_bus b_wr_n export Output 1 +add_interface_port eight_bit_bus b_rnw export Output 1 add_interface_port eight_bit_bus b_wait_n export Input 1 add_interface_port eight_bit_bus b_addr export Output 16 add_interface_port eight_bit_bus b_data_in export Input 8 diff --git a/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd index 29e4ff3..14c45e7 100644 --- a/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd +++ b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd @@ -27,8 +27,7 @@ entity async_8bit_bus_adapter is wait_n : out std_logic; -- .waitrequest_n readdata : out std_logic_vector(7 downto 0); -- .readdata b_cs_n : out std_logic; -- eight_bit_bus.export - b_rd_n : out std_logic; -- .export - b_wr_n : out std_logic; -- .export + b_rnw : out std_logic; -- .export b_wait_n : in std_logic := '0'; -- .export b_addr : out std_logic_vector(15 downto 0); -- .export b_data_in : in std_logic_vector(7 downto 0) := (others => '0'); -- .export @@ -45,9 +44,7 @@ begin b_cs_n <= '0'; - b_wr_n <= '0'; - - b_rd_n <= '0'; + b_rnw <= '0'; b_data_out <= "00000000"; diff --git a/sdram.vhd b/sdram.vhd index 557d3b0..7e31b5b 100644 --- a/sdram.vhd +++ b/sdram.vhd @@ -55,8 +55,7 @@ component sdram_mcu is ); end component sdram_mcu; - -entity sdram_ctrl is +component sdram_ctrl is port ( clock_100 : in std_logic; @@ -86,7 +85,7 @@ entity sdram_ctrl is sdram_dq : inout data_t; sdram_dqm : out dqm_t ); -end entity; +end component; signal b_addr : addr_t; @@ -121,7 +120,7 @@ begin ebb_0_rnw => b_rnw, -- .rnw ebb_0_wait_n => b_wait_n, -- .wait_n ebb_0_addr => b_addr, -- .addr - ebb_0_data_in => b_data_in8 -- .data + ebb_0_data_in => b_data_in8, -- .data ebb_0_data_out => b_data_out8 -- .data ); diff --git a/sdram_mcu.qsys b/sdram_mcu.qsys index f2d8f4e..ef018be 100644 --- a/sdram_mcu.qsys +++ b/sdram_mcu.qsys @@ -113,19 +113,19 @@ type = "String"; } } - element pio_0.s1 + element timer_0.s1 { datum baseAddress { - value = "172112"; + value = "172064"; type = "String"; } } - element timer_0.s1 + element pio_0.s1 { datum baseAddress { - value = "172064"; + value = "172112"; type = "String"; } } @@ -152,7 +152,7 @@ - + -- cgit v1.2.3