From 7fbec04d3aaca8909f89b325e125e46fe218e3be Mon Sep 17 00:00:00 2001 From: James Date: Sun, 13 Oct 2013 12:40:04 +0100 Subject: fish --- Makefile | 81 +-- async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v | 44 ++ .../async_8bit_bus_adapter.vhd | 53 ++ .../async_8bit_bus_adapter_hw.tcl | 141 +++++ .../async_8bit_bus_adapter_hw.tcl~ | 136 +++++ sdram.qsf | 8 +- sdram.vhd | 145 ++++- sdram_ctrl.vhd | 49 ++ sdram_mcu.qsys | 617 +++++++++++++++++++++ tools/wrap | 15 + 10 files changed, 1229 insertions(+), 60 deletions(-) create mode 100644 async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v create mode 100644 async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd create mode 100644 async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl create mode 100644 async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ create mode 100644 sdram_ctrl.vhd create mode 100644 sdram_mcu.qsys create mode 100755 tools/wrap diff --git a/Makefile b/Makefile index 0611dcf..59a04ba 100644 --- a/Makefile +++ b/Makefile @@ -1,21 +1,21 @@ -PROJ=pong +PROJ=sdram SRCS=$(wildcard *.vhd *.v *.qsf *.qpf ) SRCS += $(shell find DM9000A -type f -print ) SRCS += $(shell find GPU -type f -print ) -#BSP_DIR=bsp -#QSYS=pong_mcu -#SOPC_FILE=${QSYS}.sopcinfo -#BSP_TYPE=hal -#NIOS2_BSP_ARGS="" -#CPU_NAME= +BSP_DIR=bsp +QSYS=sdram_mcu +SOPC_FILE=${QSYS}.sopcinfo +BSP_TYPE=hal +NIOS2_BSP_ARGS="" +CPU_NAME= -#ELF=src/${PROJ}.elf -#SOF=${PROJ}.sof +ELF=src/${PROJ}.elf +SOF=${PROJ}.sof -#default: load_elf.stamp -default: load_sof.stamp +default: load_elf.stamp +#default: load_sof.stamp sta.stamp:asm.stamp @@ -36,29 +36,30 @@ ans.stamp: source.stamp tools/wrap quartus_map --read_settings_files=on --write_settings_files=off ${PROJ} -c ${PROJ} touch $@ -#${SOPC_FILE}:ans.stamp -# -#source.stamp:${SRC} -# touch source.stamp -# -#${ELF}: src/Makefile -# tools/wrap make -C src +${SOPC_FILE}:ans.stamp -#elf.stamp:${ELF} -# touch $@ - -#src/Makefile: bsp.stamp -# tools/wrap nios2-app-generate-makefile --bsp-dir bsp --src-rdir src --app-dir src --elf-name ${PROJ}.elf -#bsp.stamp:${SOPC_FILE} -# /bin/rm -rf ${BSP_DIR} -# mkdir -p ${BSP_DIR} -# tools/wrap nios2-bsp ${BSP_TYPE} ${BSP_DIR} ${SOPC_FILE} ${NIOS2_BSP_ARGS} ${CPU_NAME} -# tools/wrap make -C ${BSP_DIR} -# touch $@ +source.stamp:${SRC} + touch source.stamp + +${ELF}: src/Makefile + tools/wrap make -C src + +elf.stamp:${ELF} + touch $@ + +src/Makefile: bsp.stamp + tools/wrap nios2-app-generate-makefile --bsp-dir bsp --src-rdir src --app-dir src --elf-name ${PROJ}.elf + +bsp.stamp:${SOPC_FILE} + /bin/rm -rf ${BSP_DIR} + mkdir -p ${BSP_DIR} + tools/wrap nios2-bsp ${BSP_TYPE} ${BSP_DIR} ${SOPC_FILE} ${NIOS2_BSP_ARGS} ${CPU_NAME} + tools/wrap make -C ${BSP_DIR} + touch $@ -#load_elf.stamp:${ELF} load_sof.stamp -# tools/wrap nios2-download ${ELF} -g +load_elf.stamp:${ELF} load_sof.stamp + tools/wrap nios2-download ${ELF} -g load_sof.stamp: ${SOF} tools/wrap quartus_pgm -m JTAG -o "p;${SOF}" @@ -67,18 +68,18 @@ load_sof.stamp: ${SOF} sof.flash: ${SOF} tools/wrap sof2flash --input=$< --output=$@ --epcs --verbose -#elf.flash: ${ELF} sof.flash -# tools/wrap elf2flash --input=${ELF} --output=$@ --epcs --after=sof.flash --verbose +elf.flash: ${ELF} sof.flash + tools/wrap elf2flash --input=${ELF} --output=$@ --epcs --after=sof.flash --verbose -#qsys: -# tools/wrap qsys-edit ${QSYS}.qsys --project-dir=${PWD} --system-info=DEVICE_FAMILY="Cyclone II" --system-info=DEVICE=EP2C8Q208C8 --system-info=DEVICE_SPEEDGRADE=8 --host-controller +qsys: + tools/wrap qsys-edit ${QSYS}.qsys --project-dir=${PWD} --system-info=DEVICE_FAMILY="Cyclone II" --system-info=DEVICE=EP2C8Q208C8 --system-info=DEVICE_SPEEDGRADE=8 --host-controller -#${BSP_DIR}/system.h:bsp.stamp +${BSP_DIR}/system.h:bsp.stamp -#flash: load_sof.stamp sof.flash elf.flash ${BSP_DIR}/system.h -# BASE=` grep EPCS_FLASH_CONTROLLER_0_BASE ${BSP_DIR}/system.h | awk '{print $$3}' ` && \ -# tools/wrap nios2-flash-programmer sof.flash --base=$${BASE} --epcs --accept-bad-sysid --device=1 --instance=0 --program --verbose && \ -# tools/wrap nios2-flash-programmer elf.flash --base=$${BASE} --epcs --accept-bad-sysid --device=1 --instance=0 --program --verbose -g +flash: load_sof.stamp sof.flash elf.flash ${BSP_DIR}/system.h + BASE=` grep EPCS_FLASH_CONTROLLER_0_BASE ${BSP_DIR}/system.h | awk '{print $$3}' ` && \ + tools/wrap nios2-flash-programmer sof.flash --base=$${BASE} --epcs --accept-bad-sysid --device=1 --instance=0 --program --verbose && \ + tools/wrap nios2-flash-programmer elf.flash --base=$${BASE} --epcs --accept-bad-sysid --device=1 --instance=0 --program --verbose -g clean: /bin/rm -rf ${BSP_DIR} db incremental_db src/obj diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v new file mode 100644 index 0000000..bfd69c3 --- /dev/null +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v @@ -0,0 +1,44 @@ +// async_8bit_bus_adapter.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module async_8bit_bus_adapter #( + parameter AUTO_CLOCK_CLOCK_RATE = "-1" + ) ( + input wire clk, // clock.clk + input wire rst_n, // reset.reset_n + input wire cs_n, // avalon_slave.chipselect_n + input wire [15:0] address, // .address + input wire [7:0] writedata, // .writedata + input wire wr_n, // .write_n + input wire rd_n, // .read_n + output wire wait_n, // .waitrequest_n + output wire [7:0] readdata, // .readdata + output wire b_cs_n, // eight_bit_bus.export + output wire b_rd_n, // .export + output wire b_wr_n, // .export + input wire b_wait_n, // .export + output wire [15:0] b_addr, // .export + inout wire [7:0] b_data // .export + ); + + // TODO: Auto-generated HDL template + + assign readdata = 8'b00000000; + + assign b_cs_n = 1'b0; + + assign b_wr_n = 1'b0; + + assign b_rd_n = 1'b0; + + assign b_addr = 16'b0000000000000000; + +endmodule diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd new file mode 100644 index 0000000..5983f63 --- /dev/null +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd @@ -0,0 +1,53 @@ +-- async_8bit_bus_adapter.vhd + +-- This file was auto-generated as a prototype implementation of a module +-- created in component editor. It ties off all outputs to ground and +-- ignores all inputs. It needs to be edited to make it do something +-- useful. +-- +-- This file will not be automatically regenerated. You should check it in +-- to your version control system if you want to keep it. + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity async_8bit_bus_adapter is + generic ( + AUTO_CLOCK_CLOCK_RATE : string := "-1" + ); + port ( + clk : in std_logic := '0'; -- clock.clk + rst_n : in std_logic := '0'; -- reset.reset_n + cs_n : in std_logic := '0'; -- avalon_slave.chipselect_n + address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address + writedata : in std_logic_vector(7 downto 0) := (others => '0'); -- .writedata + wr_n : in std_logic := '0'; -- .write_n + rd_n : in std_logic := '0'; -- .read_n + wait_n : out std_logic; -- .waitrequest_n + readdata : out std_logic_vector(7 downto 0); -- .readdata + b_cs_n : out std_logic; -- eight_bit_bus.export + b_rd_n : out std_logic; -- .export + b_wr_n : out std_logic; -- .export + b_wait_n : in std_logic := '0'; -- .export + b_addr : out std_logic; -- .export + b_data : inout std_logic := '0' -- .export + ); +end entity async_8bit_bus_adapter; + +architecture rtl of async_8bit_bus_adapter is +begin + + -- TODO: Auto-generated HDL template + + readdata <= "00000000"; + + b_cs_n <= '0'; + + b_wr_n <= '0'; + + b_rd_n <= '0'; + + b_addr <= '0'; + +end architecture rtl; -- of async_8bit_bus_adapter diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl new file mode 100644 index 0000000..d4f8021 --- /dev/null +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl @@ -0,0 +1,141 @@ +# TCL File Generated by Component Editor 13.0sp1 +# Sun Oct 13 12:34:21 BST 2013 +# DO NOT MODIFY + + +# +# async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 +# 2013.10.13.12:34:21 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module async_8bit_bus_adapter +# +set_module_property DESCRIPTION "" +set_module_property NAME async_8bit_bus_adapter +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP my_lib +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME async_8bit_bus_adapter +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_8bit_bus_adapter +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file async_8bit_bus_adapter.v VERILOG PATH async_8bit_bus_adapter.v TOP_LEVEL_FILE + +add_fileset SIM_VHDL SIM_VHDL "" "" +set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter +set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file async_8bit_bus_adapter_hw.tcl OTHER PATH async_8bit_bus_adapter_hw.tcl + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset rst_n reset_n Input 1 + + +# +# connection point avalon_slave +# +add_interface avalon_slave avalon end +set_interface_property avalon_slave addressUnits WORDS +set_interface_property avalon_slave associatedClock clock +set_interface_property avalon_slave associatedReset reset +set_interface_property avalon_slave bitsPerSymbol 8 +set_interface_property avalon_slave burstOnBurstBoundariesOnly false +set_interface_property avalon_slave burstcountUnits WORDS +set_interface_property avalon_slave explicitAddressSpan 0 +set_interface_property avalon_slave holdTime 0 +set_interface_property avalon_slave linewrapBursts false +set_interface_property avalon_slave maximumPendingReadTransactions 0 +set_interface_property avalon_slave readLatency 0 +set_interface_property avalon_slave readWaitTime 1 +set_interface_property avalon_slave setupTime 0 +set_interface_property avalon_slave timingUnits Cycles +set_interface_property avalon_slave writeWaitTime 0 +set_interface_property avalon_slave ENABLED true +set_interface_property avalon_slave EXPORT_OF "" +set_interface_property avalon_slave PORT_NAME_MAP "" +set_interface_property avalon_slave SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave cs_n chipselect_n Input 1 +add_interface_port avalon_slave address address Input 16 +add_interface_port avalon_slave writedata writedata Input 8 +add_interface_port avalon_slave wr_n write_n Input 1 +add_interface_port avalon_slave rd_n read_n Input 1 +add_interface_port avalon_slave wait_n waitrequest_n Output 1 +add_interface_port avalon_slave readdata readdata Output 8 +set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point eight_bit_bus +# +add_interface eight_bit_bus conduit end +set_interface_property eight_bit_bus associatedClock clock +set_interface_property eight_bit_bus associatedReset "" +set_interface_property eight_bit_bus ENABLED true +set_interface_property eight_bit_bus EXPORT_OF "" +set_interface_property eight_bit_bus PORT_NAME_MAP "" +set_interface_property eight_bit_bus SVD_ADDRESS_GROUP "" + +add_interface_port eight_bit_bus b_cs_n export Output 1 +add_interface_port eight_bit_bus b_rd_n export Output 1 +add_interface_port eight_bit_bus b_wr_n export Output 1 +add_interface_port eight_bit_bus b_wait_n export Input 1 +add_interface_port eight_bit_bus b_addr export Output 16 +add_interface_port eight_bit_bus b_data export Bidir 8 + diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ new file mode 100644 index 0000000..bd77527 --- /dev/null +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ @@ -0,0 +1,136 @@ +# TCL File Generated by Component Editor 13.0sp1 +# Sun Oct 13 12:34:12 BST 2013 +# DO NOT MODIFY + + +# +# async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 +# 2013.10.13.12:34:12 +# +# + +# +# request TCL package from ACDS 13.1 +# +package require -exact qsys 13.1 + + +# +# module async_8bit_bus_adapter +# +set_module_property DESCRIPTION "" +set_module_property NAME async_8bit_bus_adapter +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP my_lib +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME async_8bit_bus_adapter +set_module_property INSTANTIATE_IN_SYSTEM_MODULE false +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset SIM_VHDL SIM_VHDL "" "" +set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter +set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file async_8bit_bus_adapter_hw.tcl OTHER PATH async_8bit_bus_adapter_hw.tcl + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset rst_n reset_n Input 1 + + +# +# connection point avalon_slave +# +add_interface avalon_slave avalon end +set_interface_property avalon_slave addressUnits WORDS +set_interface_property avalon_slave associatedClock clock +set_interface_property avalon_slave associatedReset reset +set_interface_property avalon_slave bitsPerSymbol 8 +set_interface_property avalon_slave burstOnBurstBoundariesOnly false +set_interface_property avalon_slave burstcountUnits WORDS +set_interface_property avalon_slave explicitAddressSpan 0 +set_interface_property avalon_slave holdTime 0 +set_interface_property avalon_slave linewrapBursts false +set_interface_property avalon_slave maximumPendingReadTransactions 0 +set_interface_property avalon_slave readLatency 0 +set_interface_property avalon_slave readWaitTime 1 +set_interface_property avalon_slave setupTime 0 +set_interface_property avalon_slave timingUnits Cycles +set_interface_property avalon_slave writeWaitTime 0 +set_interface_property avalon_slave ENABLED true +set_interface_property avalon_slave EXPORT_OF "" +set_interface_property avalon_slave PORT_NAME_MAP "" +set_interface_property avalon_slave SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave cs_n chipselect_n Input 1 +add_interface_port avalon_slave address address Input 16 +add_interface_port avalon_slave writedata writedata Input 8 +add_interface_port avalon_slave wr_n write_n Input 1 +add_interface_port avalon_slave rd_n read_n Input 1 +add_interface_port avalon_slave wait_n waitrequest_n Output 1 +add_interface_port avalon_slave readdata readdata Output 8 +set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point eight_bit_bus +# +add_interface eight_bit_bus conduit end +set_interface_property eight_bit_bus associatedClock clock +set_interface_property eight_bit_bus associatedReset "" +set_interface_property eight_bit_bus ENABLED true +set_interface_property eight_bit_bus EXPORT_OF "" +set_interface_property eight_bit_bus PORT_NAME_MAP "" +set_interface_property eight_bit_bus SVD_ADDRESS_GROUP "" + +add_interface_port eight_bit_bus b_cs_n export Output 1 +add_interface_port eight_bit_bus b_rd_n export Output 1 +add_interface_port eight_bit_bus b_wr_n export Output 1 +add_interface_port eight_bit_bus b_wait_n export Input 1 +add_interface_port eight_bit_bus b_addr export Output 16 +add_interface_port eight_bit_bus b_data export Bidir 8 + diff --git a/sdram.qsf b/sdram.qsf index 3ffdd0a..258bb76 100644 --- a/sdram.qsf +++ b/sdram.qsf @@ -56,8 +56,8 @@ set_location_assignment PIN_44 -to seven_seg[3] set_location_assignment PIN_39 -to seven_seg[2] set_location_assignment PIN_35 -to seven_seg[1] set_location_assignment PIN_34 -to seven_seg[0] -set_location_assignment PIN_23 -to clk -set_location_assignment PIN_27 -to rst_n +set_location_assignment PIN_23 -to clock_50 +set_location_assignment PIN_27 -to reset_n set_location_assignment PIN_92 -to sdram_addr[12] set_location_assignment PIN_90 -to sdram_addr[11] set_location_assignment PIN_75 -to sdram_addr[10] @@ -144,6 +144,8 @@ set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name PIN_FILE sdram.pin -set_global_assignment -name VHDL_FILE sdram.v +set_global_assignment -name VHDL_FILE sdram.vhd +set_global_assignment -name VHDL_FILE sdram_ctrl.vhd +set_global_assignment -name QSYS_FILE pong_mcu.qsys set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/sdram.vhd b/sdram.vhd index 6ca4721..4dd27b2 100644 --- a/sdram.vhd +++ b/sdram.vhd @@ -1,17 +1,128 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity sdram is -port ( - clock_50 : in std_logic; - DI : in std_logic_vector(6 downto 0); - fish : out std_logic; - ); -end entity; - -architecture rtl of saa5050 is - -begin - fish <= clock_50; -end architecture; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity sdram is +port ( + clock_50 : in std_logic; + reset_n : in std_logic; + seven_seg : out std_logic_vector(7 downto 0); + + sdram_clk : out std_logic; + + sdram_cs_n : out std_logic; + sdram_cas_n : out std_logic; + sdram_ras_n : out std_logic; + sdram_we_n : out std_logic; + sdram_cke : out std_logic; + + sdram_addr : out std_logic_vector(12 downto 0); + sdram_ba : out std_logic_vector(1 downto 0); + + sdram_dq : inout std_logic_vector(15 downto 0); + sdram_dqm : out std_logic_vector(1 downto 0) +); +end entity; + +architecture rtl of sdram is + + +component sdram_mcu is + port ( + clk_clk : in std_logic := 'X'; -- clk + reset_reset_n : in std_logic := 'X'; -- reset_n + pio_0_d_export : out std_logic_vector(7 downto 0); -- export + ebb_0_cs_n : out std_logic; -- cs_n + ebb_0_rd_n : out std_logic; -- rd_n + ebb_0_wr_n : out std_logic; -- wr_n + ebb_0_wait_n : in std_logic := 'X'; -- wait_n + ebb_0_addr : out std_logic_vector(15 downto 0); -- addr + ebb_0_data : inout std_logic_vector(7 downto 0) := (others => 'X') -- data + ); +end component sdram_mcu; + + +component sdram_ctrl is + port + ( + clock_50 : in std_logic; + reset_n : in std_logic; + + b_cs_n : in std_logic; + b_rd_n : in std_logic; + b_wr_n : in std_logic; + + b_wait_n : out std_logic; + + b_addr : in std_logic_vector(15 downto 0); + b_data : inout std_logic_vector(7 downto 0); + + + sdram_clk : out std_logic; + + sdram_cs_n : out std_logic; + sdram_cas_n : out std_logic; + sdram_ras_n : out std_logic; + sdram_we_n : out std_logic; + sdram_cke : out std_logic; + + sdram_addr : out std_logic_vector(12 downto 0); + sdram_ba : out std_logic_vector(1 downto 0); + + sdram_dq : inout std_logic_vector(15 downto 0); + sdram_dqm : out std_logic_vector(1 downto 0) + ); +end component; + +signal b_addr : std_logic_vector(15 downto 0); +signal b_data : std_logic_vector(7 downto 0); +signal b_cs_n : std_logic; +signal b_rd_n : std_logic; +signal b_wr_n : std_logic; +signal b_wait_n : std_logic; + +begin + + + u0 : component sdram_mcu port map ( + clk_clk => clock_50, -- clk.clk + reset_reset_n => reset_n, -- reset.reset_n + pio_0_d_export => seven_seg, -- pio_0_d.export + ebb_0_cs_n => b_cs_n, -- ebb_0.cs_n + ebb_0_rd_n => b_rd_n, -- .rd_n + ebb_0_wr_n => b_wr_n, -- .wr_n + ebb_0_wait_n => b_wait_n, -- .wait_n + ebb_0_addr => b_addr, -- .addr + ebb_0_data => b_data -- .data + ); + + + sdram_ctrl0: sdram_ctrl port map ( + clock_50, + reset_n, + + b_cs_n, + b_rd_n, + b_wr_n, + + b_wait_n, + + b_addr, + b_data, + + sdram_clk, + + sdram_cs_n, + sdram_cas_n, + sdram_ras_n, + sdram_we_n, + sdram_cke, + + sdram_addr, + sdram_ba, + + sdram_dq, + sdram_dqm + ); + +end architecture; diff --git a/sdram_ctrl.vhd b/sdram_ctrl.vhd new file mode 100644 index 0000000..1c93b13 --- /dev/null +++ b/sdram_ctrl.vhd @@ -0,0 +1,49 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity sdram_ctrl is +port +( + clock_50 : in std_logic; + reset_n : in std_logic; + + b_cs_n : in std_logic; + b_rd_n : in std_logic; + b_wr_n : in std_logic; + + b_wait_n : out std_logic; + + b_addr : in std_logic_vector(15 downto 0); + b_data : inout std_logic_vector(7 downto 0); + + + sdram_clk : out std_logic; + + sdram_cs_n : out std_logic; + sdram_cas_n : out std_logic; + sdram_ras_n : out std_logic; + sdram_we_n : out std_logic; + sdram_cke : out std_logic; + + sdram_addr : out std_logic_vector(12 downto 0); + sdram_ba : out std_logic_vector(1 downto 0); + + sdram_dq : inout std_logic_vector(15 downto 0); + sdram_dqm : out std_logic_vector(1 downto 0) +); +end entity; + +architecture rtl of sdram_ctrl is + + +begin + +sdram_clk <=clock_50; + +end; + + + + + diff --git a/sdram_mcu.qsys b/sdram_mcu.qsys new file mode 100644 index 0000000..0764db1 --- /dev/null +++ b/sdram_mcu.qsys @@ -0,0 +1,617 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + epcs_flash_controller_0.epcs_control_port + + epcs_flash_controller_0.epcs_control_port + nios2_qsys_0.jtag_debug_module + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + ]]> + + + + + ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0 + + + + + + + + + + + + + + + $${FILENAME}_epcs_flash_controller_0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + INTERACTIVE_ASCII_OUTPUT + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_onchip_memory2_0 + + ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/wrap b/tools/wrap new file mode 100755 index 0000000..26a0640 --- /dev/null +++ b/tools/wrap @@ -0,0 +1,15 @@ +#!/bin/bash + +AD=/software/apps/altera/quartus_ii_13.0sp1 +if [ $(uname -m ) == "x86_64" ]; then + LL=linux64 +else + LL=linux +fi +QUARTUS_ROOTDIR="${AD}/quartus" +PATH="${AD}/quartus/bin:${AD}/quartus/sopc_builder/bin:${AD}/nios2eds/sdk2/bin:${AD}/nios2eds/bin:${AD}/nios2eds/bin/gnu/H-i686-pc-linux-gnu/bin:${PATH}" +LD_LIBRARY_PATH="${AD}/quartus/${LL}:${LD_LIBRARY_PATH}" + +export LD_LIBRARY_PATH PATH QUARTUS_ROOTDIR + +"$@" -- cgit v1.2.3