From 3b79402993f7857243ab033644d7ca6b757be76d Mon Sep 17 00:00:00 2001 From: James Date: Mon, 14 Oct 2013 15:37:44 +0100 Subject: runs --- pllx2.vhd | 24 ++++++++++++------------ sdram.qsf | 1 + sdram.vhd | 60 ++++++++++++++++++++++++++++++++---------------------------- 3 files changed, 45 insertions(+), 40 deletions(-) diff --git a/pllx2.vhd b/pllx2.vhd index c1824de..6fa7af2 100644 --- a/pllx2.vhd +++ b/pllx2.vhd @@ -4,7 +4,7 @@ -- MODULE: altpll -- ============================================================ --- File Name: pllpllx2.vhd +-- File Name: pllx2.vhd -- Megafunction Name(s): -- altpll -- @@ -39,7 +39,7 @@ USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; -ENTITY pllpllx2 IS +ENTITY pllx2 IS PORT ( areset : IN STD_LOGIC := '0'; @@ -47,10 +47,10 @@ ENTITY pllpllx2 IS c0 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); -END pllpllx2; +END pllx2; -ARCHITECTURE SYN OF pllpllx2 IS +ARCHITECTURE SYN OF pllx2 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; @@ -147,7 +147,7 @@ BEGIN inclk0_input_frequency => 41666, intended_device_family => "Cyclone II", invalid_lock_multiplier => 5, - lpm_hint => "CBX_MODULE_PREFIX=pllpllx2", + lpm_hint => "CBX_MODULE_PREFIX=pllx2", lpm_type => "altpll", operation_mode => "NORMAL", port_activeclock => "PORT_UNUSED", @@ -270,7 +270,7 @@ END SYN; -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pllpllx2.mif" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pllx2.mif" -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" @@ -355,11 +355,11 @@ END SYN; -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pllpllx2.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pllpllx2.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pllpllx2.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pllpllx2.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pllpllx2.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pllpllx2_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllx2_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/sdram.qsf b/sdram.qsf index 6d3a9f9..44daa61 100644 --- a/sdram.qsf +++ b/sdram.qsf @@ -147,6 +147,7 @@ set_global_assignment -name PIN_FILE sdram.pin set_global_assignment -name VHDL_FILE sdram.vhd set_global_assignment -name VHDL_FILE sdram_util.vhd set_global_assignment -name VHDL_FILE sdram_ctrl.vhd +set_global_assignment -name VHDL_FILE pllx2.vhd set_global_assignment -name QSYS_FILE sdram_mcu.qsys diff --git a/sdram.vhd b/sdram.vhd index 7e31b5b..e9373da 100644 --- a/sdram.vhd +++ b/sdram.vhd @@ -47,11 +47,11 @@ component sdram_mcu is reset_reset_n : in std_logic := 'X'; -- reset_n pio_0_d_export : out std_logic_vector(7 downto 0); -- export ebb_0_cs_n : out std_logic; -- cs_n - ebb_0_rd_n : out std_logic; -- rd_n - ebb_0_wr_n : out std_logic; -- wr_n + ebb_0_rnw : out std_logic; -- rnw ebb_0_wait_n : in std_logic := 'X'; -- wait_n ebb_0_addr : out std_logic_vector(15 downto 0); -- addr - ebb_0_data : inout std_logic_vector(7 downto 0) := (others => 'X') -- data + ebb_0_data_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- data_in + ebb_0_data_out : out std_logic_vector(7 downto 0) -- data_out ); end component sdram_mcu; @@ -87,11 +87,12 @@ component sdram_ctrl is ); end component; +signal b_data_in8 : std_logic_vector(7 downto 0); +signal b_data_out8 : std_logic_vector(7 downto 0); +signal b_addr16: std_logic_vector(15 downto 0); signal b_addr : addr_t; -signal b_data_in8 : std_logic_vector(7 downto 0); signal b_data_in : data_t; -signal b_data_out8 : std_logic_vector(7 downto 0); signal b_data_out : data_t; signal b_cs_n : std_logic; signal b_rnw : std_logic; @@ -119,44 +120,47 @@ begin ebb_0_cs_n => b_cs_n, -- ebb_0.cs_n ebb_0_rnw => b_rnw, -- .rnw ebb_0_wait_n => b_wait_n, -- .wait_n - ebb_0_addr => b_addr, -- .addr + ebb_0_addr => b_addr16, -- .addr ebb_0_data_in => b_data_in8, -- .data ebb_0_data_out => b_data_out8 -- .data ); - b_data_in(7 downto 0) <= b_data_in8; - b_data_in(15 downto 8) <= (others => '0'); + -- bodge buses together + + b_data_in(7 downto 0) <= b_data_out8; + b_data_in(15 downto 8) <= (others =>'0'); - b_data_out8 <= b_data_out(7 downto 0); + b_data_in8 <= b_data_out(7 downto 0); + b_addr(15 downto 0) <= b_addr16; + b_addr(23 downto 16) <= (others => '0'); sdram_ctrl0: sdram_ctrl port map ( - clock_100, - global_reset_n, + clock_100 => clock_100, + reset_n => global_reset_n, - b_cs_n, - b_rnw, + bus_cs_n => b_cs_n, + bus_rnw => b_rnw, - b_wait_n, - sdram_cke, + bus_wait_n => b_wait_n, - b_addr, - b_data_in, - b_data_out, + bus_addr => b_addr, + bus_data_in => b_data_in, + bus_data_out => b_data_out, - sdram_clk, - sdram_cke, + sdram_clk => sdram_clk, + sdram_cke => sdram_cke, - sdram_cs_n, - sdram_cas_n, - sdram_ras_n, - sdram_we_n, + sdram_cs_n => sdram_cs_n, + sdram_cas_n => sdram_cas_n, + sdram_ras_n => sdram_ras_n, + sdram_we_n => sdram_we_n, - sdram_addr, - sdram_ba, + sdram_addr => sdram_addr, + sdram_ba => sdram_ba, - sdram_dq, - sdram_dqm + sdram_dq => sdram_dq, + sdram_dqm => sdram_dqm ); pll_reset <= '0'; -- cgit v1.2.3