From ba36b7b03e8b03600e4342f3fa7ed60dc3d61352 Mon Sep 17 00:00:00 2001 From: the great greene arkleseizure Date: Thu, 10 Oct 2013 10:59:48 +0100 Subject: software-1 --- software/pong3/DM9000A.H | 72 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 software/pong3/DM9000A.H (limited to 'software/pong3/DM9000A.H') diff --git a/software/pong3/DM9000A.H b/software/pong3/DM9000A.H new file mode 100644 index 0000000..47401f1 --- /dev/null +++ b/software/pong3/DM9000A.H @@ -0,0 +1,72 @@ +#ifndef __DM9000A_H__ +#define __DM9000A_H__ + +#define IO_addr 0 +#define IO_data 1 + +#define NCR 0x00 /* Network Control Register REG. 00 */ +#define NSR 0x01 /* Network Status Register REG. 01 */ +#define TCR 0x02 /* Transmit Control Register REG. 02 */ +#define RCR 0x05 /* Receive Control Register REG. 05 */ +#define ETXCSR 0x30 /* TX early Control Register REG. 30 */ +#define MRCMDX 0xF0 /* RX FIFO I/O port command READ for dummy read a byte from RX SRAM */ +#define MRCMD 0xF2 /* RX FIFO I/O port command READ from RX SRAM */ +#define MWCMD 0xF8 /* TX FIFO I/O port command WRITE into TX FIFO */ +#define ISR 0xFE /* NIC Interrupt Status Register REG. FEH */ +#define IMR 0xFF /* NIC Interrupt Mask Register REG. FFH */ +#define OTCR 0x2E /* NIC Operation Test Control Register REG. 2EH */ +#define TCSCR 0x31 /* Transmit Check Sum Control Register REG. 31H */ + +#define NCR_set 0x00 +#define TCR_set 0x00 +#define TX_REQUEST 0x01 /* TCR REG. 02 TXREQ Bit [0] = 1 polling Transmit Request command */ +#define TCR_long 0x40 /* packet disable TX Jabber Timer */ +#define RCR_set 0x30 /* skip CRC_packet and skip LONG_packet */ +#define RX_ENABLE 0x01 /* RCR REG. 05 RXEN Bit [0] = 1 to enable RX machine */ +#define RCR_long 0x40 /* packet disable RX Watchdog Timer */ +#define PASS_MULTICAST 0x08 /* RCR REG. 05 PASS_ALL_MULTICAST Bit [3] = 1: RCR_set value ORed 0x08 */ +#define BPTR_set 0x37 /* BPTR REG. 08 RX Back Pressure Threshold: High Water Overflow Threshold setting 3KB and Jam_Pattern_Time = 200 us */ +#define FCTR_set 0x38 /* FCTR REG. 09 High/ Low Water Overflow Threshold setting 3KB/ 8KB */ +#define RTFCR_set 0x29 /* RTFCR REG. 0AH RX/TX Flow Control Register enable TXPEN + BKPM(TX_Half) + FLCE(RX) */ +#define ETXCSR_set 0x80 /* Early Transmit Bit [7] Enable and Threshold 0~3: 12.5%, 25%, 50%, 75% */ +#define INTR_set 0x81 /* IMR REG. FFH: PAR +PRM, or 0x81: PAR + PRM + PTM */ +#define PAR_set 0x80 /* IMR REG. FFH: PAR only, RX/TX FIFO R/W Pointer Auto Return enable */ +#define OTCR_set 0x80 /* System Clock set = 100Mhz */ +#define TCSCR_set 0x00 /* UDP TCP IP auto send check */ + +#define PHY_reset 0x8000 /* PHY reset: some registers back to default value */ +#define PHY_txab 0x05e1 /* set PHY TX advertised ability: Full-capability + Flow-control (if necessary) */ +#define PHY_mode 0x3100 /* set PHY media mode: Auto negotiation (AUTO sense) */ + +#define STD_DELAY 20 /* standard delay 20 us */ + +#define DMFE_SUCCESS 0 +#define DMFE_FAIL 1 + +#define TRUE 1 +#define FALSE 0 + +#define DM9000_PKT_READY 0x01 /* packets ready to receive */ +#define PACKET_MIN_SIZE 0x40 /* Received packet min size */ +#define MAX_PACKET_SIZE 1522 /* RX largest legal size packet with fcs & QoS */ +#define DM9000_PKT_MAX 3072 /* TX 1 packet max size without 4-byte CRC */ +//------------------------------------------------------------------------- +unsigned char ether_addr[6]={ 0x01, 0x60, 0x6E, 0x11, 0x02, 0x0F }; +//------------------------------------------------------------------------- +void iow(unsigned int reg, unsigned int data); +unsigned int ior(unsigned int reg); +void phy_write(unsigned int reg, unsigned int value); +/* DM9000_init I/O routine */ +unsigned int DM9000_init (void); +/* Transmit One Packet TX I/O routine */ +unsigned int TransmitPacket(unsigned char *data_ptr,unsigned int tx_len); +/* Receive One Packet I/O routine */ +unsigned int ReceivePacket (unsigned char *data_ptr,unsigned int *rx_len); +//------------------------------------------------------------------------- + +#endif + + + + + -- cgit v1.2.3