From 4b7ba2f7366194608aac59b47d0f3c7cd9f21fb1 Mon Sep 17 00:00:00 2001 From: James Date: Thu, 10 Oct 2013 11:40:39 +0100 Subject: remove-path --- DM9000A/dm9000a_hw.tcl | 141 +++++++++++++++++++++++++++++++++++++++++++++++ DM9000A/hdl/DM9000A_IF.v | 85 ++++++++++++++++++++++++++++ 2 files changed, 226 insertions(+) create mode 100644 DM9000A/dm9000a_hw.tcl create mode 100644 DM9000A/hdl/DM9000A_IF.v (limited to 'DM9000A') diff --git a/DM9000A/dm9000a_hw.tcl b/DM9000A/dm9000a_hw.tcl new file mode 100644 index 0000000..ea89ec5 --- /dev/null +++ b/DM9000A/dm9000a_hw.tcl @@ -0,0 +1,141 @@ +# TCL File Generated by Component Editor 12.0 +# Thu Sep 12 21:20:16 CST 2013 +# DO NOT MODIFY + + +# +# dm9000a "dm9000a" v1.0 +# null 2013.09.12.21:20:16 +# +# + +# +# request TCL package from ACDS 12.0 +# +package require -exact qsys 12.0 + + +# +# module dm9000a +# +set_module_property NAME dm9000a +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP my_lib +set_module_property DISPLAY_NAME dm9000a +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property ANALYZE_HDL AUTO +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL DM9000A_IF +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file DM9000A_IF.v VERILOG PATH hdl/DM9000A_IF.v + +add_fileset SIM_VHDL SIM_VHDL "" "" +set_fileset_property SIM_VHDL TOP_LEVEL DM9000A_IF +set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file dm9000a_hw.tcl OTHER PATH dm9000a_hw.tcl + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressAlignment DYNAMIC +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock_sink +set_interface_property avalon_slave_0 associatedReset clock_sink_reset +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 1 +set_interface_property avalon_slave_0 isMemoryDevice false +set_interface_property avalon_slave_0 isNonVolatileStorage false +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 +set_interface_property avalon_slave_0 printableDevice false +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitStates 4 +set_interface_property avalon_slave_0 readWaitTime 4 +set_interface_property avalon_slave_0 setupTime 1 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitStates 4 +set_interface_property avalon_slave_0 writeWaitTime 4 +set_interface_property avalon_slave_0 ENABLED true + +add_interface_port avalon_slave_0 iDATA writedata Input 32 +add_interface_port avalon_slave_0 iCMD address Input 1 +add_interface_port avalon_slave_0 iRD_N read_n Input 1 +add_interface_port avalon_slave_0 iWR_N write_n Input 1 +add_interface_port avalon_slave_0 iCS_N chipselect_n Input 1 +add_interface_port avalon_slave_0 oDATA readdata Output 32 + + +# +# connection point clock_sink +# +add_interface clock_sink clock end +set_interface_property clock_sink clockRate 0 +set_interface_property clock_sink ENABLED true + +add_interface_port clock_sink iCLK clk Input 1 + + +# +# connection point clock_sink_reset +# +add_interface clock_sink_reset reset end +set_interface_property clock_sink_reset associatedClock clock_sink +set_interface_property clock_sink_reset synchronousEdges DEASSERT +set_interface_property clock_sink_reset ENABLED true + +add_interface_port clock_sink_reset iRST_N reset_n Input 1 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock "" +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true + +add_interface_port conduit_end iOSC_50 export Input 1 +add_interface_port conduit_end ENET_DATA export Bidir 16 +add_interface_port conduit_end ENET_CMD export Output 1 +add_interface_port conduit_end ENET_RD_N export Output 1 +add_interface_port conduit_end ENET_WR_N export Output 1 +add_interface_port conduit_end ENET_CS_N export Output 1 +add_interface_port conduit_end ENET_RST_N export Output 1 +add_interface_port conduit_end ENET_INT export Input 1 +add_interface_port conduit_end ENET_CLK export Output 1 + + +# +# connection point interrupt_sender +# +add_interface interrupt_sender interrupt end +set_interface_property interrupt_sender associatedAddressablePoint avalon_slave_0 +set_interface_property interrupt_sender associatedClock clock_sink +set_interface_property interrupt_sender associatedReset clock_sink_reset +set_interface_property interrupt_sender ENABLED true + +add_interface_port interrupt_sender oINT irq Output 1 + diff --git a/DM9000A/hdl/DM9000A_IF.v b/DM9000A/hdl/DM9000A_IF.v new file mode 100644 index 0000000..3fd22e0 --- /dev/null +++ b/DM9000A/hdl/DM9000A_IF.v @@ -0,0 +1,85 @@ +module DM9000A_IF( // HOST Side + iDATA, + oDATA, + iCMD, + iRD_N, + iWR_N, + iCS_N, + iRST_N, + iCLK, + iOSC_50, + oINT, + // DM9000A Side + ENET_DATA, + ENET_CMD, + ENET_RD_N, + ENET_WR_N, + ENET_CS_N, + ENET_RST_N, + ENET_INT, + ENET_CLK ); +// HOST Side +input [31:0] iDATA; +input iCMD; +input iRD_N; +input iWR_N; +input iCS_N; +input iRST_N; +input iCLK; +input iOSC_50; +output [31:0] oDATA; +output oINT; +// DM9000A Side +inout [15:0] ENET_DATA; +output ENET_CMD; +output ENET_RD_N; +output ENET_WR_N; +output ENET_CS_N; +output ENET_RST_N; +output ENET_CLK; +input ENET_INT; + +reg [15:0] TMP_DATA; +reg ENET_CMD; +reg ENET_RD_N; +reg ENET_WR_N; +reg ENET_CS_N; +reg ENET_CLK; +reg [31:0] oDATA; +reg oINT; + +assign ENET_DATA = ENET_WR_N ? 16'hzzzz : TMP_DATA; + +always@(posedge iCLK or negedge iRST_N) +begin + if(!iRST_N) + begin + TMP_DATA <= 0; + ENET_CMD <= 0; + ENET_RD_N <= 1; + ENET_WR_N <= 1; + ENET_CS_N <= 1; + oDATA <= 0; + oINT <= 0; + end + else + begin + oDATA <= ENET_DATA; + oINT <= ENET_INT; + TMP_DATA <= iDATA; + ENET_CMD <= iCMD; + ENET_CS_N <= iCS_N; + ENET_RD_N <= iRD_N; + ENET_WR_N <= iWR_N; + end +end + +always@(posedge iOSC_50) +ENET_CLK <= ~ENET_CLK; + +assign ENET_RST_N = iRST_N; + +endmodule + + + -- cgit v1.2.3