library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity line_doubler is
port (
	CLOCK		:	in	std_logic;
	-- Clock enable qualifies display cycles (interleaved with CPU cycles)
	CLKEN		:	in	std_logic;
	nRESET		:	in	std_logic;
	
	-- Video in (teletext mode)
	R_IN		:	in	std_logic;
	G_IN		:	in	std_logic;
	B_IN		:	in	std_logic;
	HS_IN		:	in	std_logic;
	VS_IN		:	in	std_logic;
	
	-- Video out
	R_OUT			:	out	std_logic;
	G_OUT			:	out	std_logic;
	B_OUT			:	out	std_logic;
	HS_OUT			:	out	std_logic;
	VS_OUT			:	out	std_logic
	);
end entity;

architecture rtl of line_doubler is

component line_buffer is
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		rdclock		: IN STD_LOGIC ;
		rdclocken		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		wrclock		: IN STD_LOGIC  := '1';
		wrclocken		: IN STD_LOGIC  := '1';
		wren		: IN STD_LOGIC  := '0';
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
END component;

signal out_addr : std_logic_vector(9 downto 0);
signal in_addr : std_logic_vector(9 downto 0);

signal in_data : std_logic_vector(3 downto 0);
signal out_data : std_logic_vector(3 downto 0);
signal old_hs: std_logic;

begin

	in_data(3) <= HS_IN;
	in_data(2) <= R_IN;
	in_data(1) <= G_IN;
	in_data(0) <= B_IN;

	line_buffer_inst : line_buffer PORT MAP (
		wrclock	 	 => CLOCK,
		wrclocken	 => CLKEN,
		wren	 	 => '1',
		data	 	 => in_data,
		wraddress	 => in_addr,

		rdclock	 	 => CLOCK,
		rdclocken	 => '1',
		q	 	 => out_data,
		rdaddress	 => out_addr
	);

	HS_OUT <= out_data(3);
	R_OUT <= out_data(2);
	G_OUT <= out_data(1);
	B_OUT <= out_data(0);
	VS_OUT <= VS_IN;

	process(CLOCK,CLKEN,nRESET,HS_IN,in_addr,out_addr)
	begin
		if nRESET = '0' then
			in_addr <= (others => '0');
			out_addr <= (others => '0');
		elsif rising_edge(CLOCK) then
			old_hs <= HS_IN;

			if old_hs ='0' and HS_IN='1' then
				in_addr <= (others => '0');
				out_addr <= (others => '0');
			else
				out_addr <= std_logic_vector(unsigned(out_addr) +1 );
				if CLKEN = '1' then
					in_addr <= std_logic_vector(unsigned(in_addr) +1 );
				end if;
			end if;
		end if;
	end process;
end architecture;