From 91a541897b9e66b107a1017d5cadcc89ce1e7f84 Mon Sep 17 00:00:00 2001
From: root <root@lab.panaceas.james.local>
Date: Fri, 18 Oct 2013 11:18:51 +0100
Subject: add process sensitivity

---
 quartus/saa5050.vhd | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'quartus/saa5050.vhd')

diff --git a/quartus/saa5050.vhd b/quartus/saa5050.vhd
index 57dd999..5fa1b2c 100644
--- a/quartus/saa5050.vhd
+++ b/quartus/saa5050.vhd
@@ -85,6 +85,7 @@ port (
 	);
 end entity;
 
+-- altera message_off 10036
 architecture rtl of saa5050 is
 
 component saa5050_rom IS
@@ -155,7 +156,7 @@ begin
 	flash <= flash_counter(5) and flash_counter(4);
 		
 	-- Sync inputs
-	process(DI_CLOCK,nRESET)
+	process(DI_CLOCK,nRESET,DI_CLKEN)
 	begin
 		if nRESET = '0' then
 			di_r <= (others => '0');
@@ -169,7 +170,7 @@ begin
 	end process;
 	
 	-- Register data into pixel clock domain
-	process(CLOCK,nRESET)
+	process(CLOCK,nRESET,CLKEN)
 	begin
 		if nRESET = '0' then
 			code <= (others => '0');
@@ -188,7 +189,7 @@ begin
 			gfx & code & std_logic_vector(line_addr);
 	
 	-- Character row and pixel counters
-	process(CLOCK,nRESET)
+	process(CLOCK,nRESET,CLKEN)
 	begin	
 		if nRESET = '0' then
 			dew_latch <= '0';
@@ -260,7 +261,7 @@ begin
 	end process;
 	
 	-- Shift register
-	process(CLOCK,nRESET)
+	process(CLOCK,nRESET,CLKEN)
 	begin
 		if nRESET = '0' then
 			shift_reg <= (others => '0');
@@ -292,7 +293,7 @@ begin
 	end process;
 	
 	-- Control character handling
-	process(CLOCK,nRESET)
+	process(CLOCK,nRESET,CLKEN)
 	begin	
 		if nRESET = '0' then
 			fg <= (others => '1');
@@ -363,7 +364,7 @@ begin
 	end process;
 	
 	-- Output
-	process(CLOCK,nRESET)
+	process(CLOCK,nRESET,CLKEN,shift_reg,flash,conceal,is_flash)
 	variable pixel : std_logic;
 	begin	
 		pixel := shift_reg(5) and not ((flash and is_flash) or conceal);
-- 
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