From fdc9f05a49927558ed70b0a4c645780cbedee706 Mon Sep 17 00:00:00 2001
From: root <root@lab.panaceas.james.local>
Date: Fri, 18 Oct 2013 13:38:03 +0100
Subject: working

---
 quartus/bbc_micro_de1.vhd | 62 +++++++++++++++++++++++++++++++++++------------
 1 file changed, 47 insertions(+), 15 deletions(-)

(limited to 'quartus/bbc_micro_de1.vhd')

diff --git a/quartus/bbc_micro_de1.vhd b/quartus/bbc_micro_de1.vhd
index 080b390..4cf33a8 100644
--- a/quartus/bbc_micro_de1.vhd
+++ b/quartus/bbc_micro_de1.vhd
@@ -159,11 +159,12 @@ port (
 	SD_MISO		:	in		std_logic;
 	
 	-- GPIO
-	GPIO_0		:	inout	std_logic_vector(35 downto 0);
-	GPIO_1		:	inout	std_logic_vector(35 downto 0)
+	GPIO_0		:	out	std_logic_vector(35 downto 0);
+	GPIO_1		:	out	std_logic_vector(35 downto 0)
 	);
 end entity;
 
+-- altera message_off 10036
 architecture rtl of bbc_micro_de1 is
 
 ------------------------------
@@ -743,6 +744,9 @@ signal romsel			:	std_logic_vector(3 downto 0);
 
 signal mhz1_enable		:	std_logic;		-- Set for access to any 1 MHz peripheral
 
+signal video_data 	: std_logic_vector (7 downto 0);
+signal cpu_ram_di 	: std_logic_vector (7 downto 0);
+
 begin
 	-------------------------
 	-- COMPONENT INSTANCES
@@ -775,6 +779,8 @@ begin
 		LEDR(2) -- WATCHPOINT
 		);
 
+	debug_aux <= (others => '0');
+
 	-- 6502 CPU
 	cpu : T65 port map (
 		cpu_mode,
@@ -798,6 +804,8 @@ begin
 		cpu_a,
 		cpu_di,
 		cpu_do );
+
+	crtc_lpstb <='0';
 		
 	crtc : mc6845 port map (
 		clock,
@@ -824,7 +832,7 @@ begin
 		vidproc_enable,
 		cpu_a(0),
 		cpu_do,
-		SRAM_DQ(7 downto 0),
+		video_data,
 		vidproc_invert_n,
 		vidproc_disen,
 		crtc_cursor,
@@ -848,7 +856,7 @@ begin
 		reset_n,
 		clock, -- Data input is synchronised from the bus clock domain
 		vid_clken,
-		SRAM_DQ(6 downto 0),
+		video_data(6 downto 0),
 		ttxt_glr,
 		ttxt_dew,
 		ttxt_crs,
@@ -919,6 +927,12 @@ begin
 		mhz4_clken,
 		clock
 		);
+
+	user_via_ca2_in <='0';
+	user_via_pa_in <=(others => '0');
+
+	PS2_CLK <= 'Z'; -- really - I thought you'd need to clock that?
+	PS2_DAT <= 'Z';
 		
 	-- Keyboard
 	keyb : keyboard port map (
@@ -958,6 +972,12 @@ begin
 			LEDR(5), -- IS_DONE
 			LEDR(4) -- IS_ERROR
 		);
+	AUD_ADCLRCK <= '1';
+
+	UART_TXD <= '0';
+	DRAM_ADDR <= (others => '1');
+	LEDR(9 downto 6) <= (others => '0');
+	sys_via_pb_in(3 downto 0) <= (others => '1');
 	
 	-- Asynchronous reset
 	-- PLL is reset by external reset switch
@@ -1109,10 +1129,12 @@ begin
 			end case;
 		end if;
 	end process;
+
+	FL_DQ <= (others =>'Z');
 	
 	-- CPU data bus mux and interrupts
 	cpu_di <=
-		SRAM_DQ(7 downto 0) when ram_enable = '1' else
+		cpu_ram_di	when ram_enable = '1' else
 		FL_DQ		when rom_enable = '1' else
 		FL_DQ		when mos_enable = '1' else
 		crtc_do		when crtc_enable = '1' else
@@ -1140,10 +1162,10 @@ begin
 	-- SRAM bus
 	SRAM_UB_N <= '1';
 	SRAM_LB_N <= '0';
-	SRAM_CE_N <= '0';
+	SRAM_CE_N <= clock;
 	SRAM_OE_N <= '0';
-	SRAM_DQ(15 downto 8) <= (others => '0');
-	
+	video_data <= SRAM_DQ(7 downto 0);
+
 	-- Synchronous outputs to SRAM
 	process(clock,reset_n,ram_enable,cpu_r_nw)
 	variable ram_write : std_logic;
@@ -1152,23 +1174,25 @@ begin
 	
 		if reset_n = '0' then
 			SRAM_WE_N <= '1';
-			SRAM_DQ(7 downto 0) <= (others => 'Z');
+			SRAM_DQ(15 downto 0) <= (others => 'Z');
 		elsif rising_edge(clock) then
-			-- Default to inputs
-			SRAM_DQ(7 downto 0) <= (others => 'Z');
-			
 			-- Register SRAM signals to outputs (clock must be at least 2x CPU clock)
 			if vid_clken = '1' then
-				-- Fetch data from previous CPU cycle
+				-- set up bus for CPU cycle
 				SRAM_WE_N <= not ram_write;
 				SRAM_ADDR <= "00" & cpu_a(15 downto 0);
 				if ram_write = '1' then
+					SRAM_DQ(15 downto 8) <=(others =>'0');
 					SRAM_DQ(7 downto 0) <= cpu_do;
+				else
+					SRAM_DQ(15 downto 0) <= (others => 'Z');
 				end if;
 			else
-				-- Fetch data from previous display cycle
+				cpu_ram_di <= SRAM_DQ(7 downto 0);
+				-- setup crtc cycle 
 				SRAM_WE_N <= '1';
 				SRAM_ADDR <= "000" & display_a;
+				SRAM_DQ(15 downto 0) <= (others => 'Z');
 			end if;
 		end if;
 	end process;
@@ -1236,7 +1260,7 @@ begin
 	
 	-- Connections to System VIA
 	-- ADC
-	sys_via_cb1_in <= '1'; -- /EOC
+	sys_via_cb1_in <= '1'; -- EOC
 	-- CRTC
 	sys_via_ca1_in <= crtc_vsync;
 	sys_via_cb2_in <= crtc_lpstb;
@@ -1254,6 +1278,7 @@ begin
 	-- Connections to User VIA (user port is output on green LEDs)
 	user_via_ca1_in <= '1'; -- Pulled up
 	--LEDG <= user_via_pb_out;
+        LEDG <= (others => '0');
 	
 	-- MMBEEB
 	user_via_cb1_in <= user_via_pb_out(1);
@@ -1304,7 +1329,14 @@ begin
 	-- DEBUG STUFF
 	-----------------
 	
+	DRAM_DQ <= (others => 'Z');
+	DRAM_DQ <= (others => 'Z');
+
 	GPIO_0(0) <= not (crtc_hsync xor crtc_vsync);
 	GPIO_0(1) <= crtc_de;
+	GPIO_0(2) <= ld_vsync;
+	GPIO_0(3) <= ld_hsync;
+	GPIO_0(35 downto 4) <= (others => '0');
+	GPIO_1 <= (others => '0');
 
 end architecture;
-- 
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