From 70d56cad0d02525d2ab5f484d048fca391cdce8c Mon Sep 17 00:00:00 2001 From: James Date: Fri, 18 Oct 2013 12:25:28 +0100 Subject: general tidying --- quartus/bbc_micro_de1.qsf | 4 ++-- quartus/bbc_micro_de1.vhd | 43 ++++++++++++++++++++++++++++++++++++------- quartus/keyboard.vhd | 14 ++++++++------ 3 files changed, 46 insertions(+), 15 deletions(-) diff --git a/quartus/bbc_micro_de1.qsf b/quartus/bbc_micro_de1.qsf index 53ab492..1f4e73f 100644 --- a/quartus/bbc_micro_de1.qsf +++ b/quartus/bbc_micro_de1.qsf @@ -534,5 +534,5 @@ set_global_assignment -name VHDL_FILE m6522_tb.vhd set_global_assignment -name VHDL_FILE keyboard.vhd set_global_assignment -name VHDL_FILE debugger.vhd set_global_assignment -name QIP_FILE saa5050_rom.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top \ No newline at end of file +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/quartus/bbc_micro_de1.vhd b/quartus/bbc_micro_de1.vhd index 080b390..028ec7e 100644 --- a/quartus/bbc_micro_de1.vhd +++ b/quartus/bbc_micro_de1.vhd @@ -159,11 +159,12 @@ port ( SD_MISO : in std_logic; -- GPIO - GPIO_0 : inout std_logic_vector(35 downto 0); - GPIO_1 : inout std_logic_vector(35 downto 0) + GPIO_0 : out std_logic_vector(35 downto 0); + GPIO_1 : out std_logic_vector(35 downto 0) ); end entity; +-- altera message_off 10036 architecture rtl of bbc_micro_de1 is ------------------------------ @@ -752,8 +753,10 @@ begin pll: pll32 port map ( pll_reset, CLOCK_24(0), - clock, + clock_32, pll_locked ); + + clock <= clock_32; -- Hardware debugger block (single-step, breakpoints) debug: debugger port map ( @@ -775,6 +778,8 @@ begin LEDR(2) -- WATCHPOINT ); + debug_aux <= (others => '0'); + -- 6502 CPU cpu : T65 port map ( cpu_mode, @@ -798,6 +803,8 @@ begin cpu_a, cpu_di, cpu_do ); + + crtc_lpstb <='1'; crtc : mc6845 port map ( clock, @@ -919,6 +926,12 @@ begin mhz4_clken, clock ); + + user_via_ca2_in <='0'; + user_via_pa_in <=(others => '0'); + + PS2_CLK <= 'Z'; -- really - I thought you'd need to clock that? + PS2_DAT <= 'Z'; -- Keyboard keyb : keyboard port map ( @@ -958,6 +971,12 @@ begin LEDR(5), -- IS_DONE LEDR(4) -- IS_ERROR ); + AUD_ADCLRCK <= '0'; + + UART_TXD <= '0'; + DRAM_ADDR <= (others => '1'); + LEDR(9 downto 6) <= (others => '0'); + sys_via_pb_in(3 downto 0) <= (others => '1'); -- Asynchronous reset -- PLL is reset by external reset switch @@ -1109,6 +1128,8 @@ begin end case; end if; end process; + + FL_DQ <= (others =>'Z'); -- CPU data bus mux and interrupts cpu_di <= @@ -1142,7 +1163,6 @@ begin SRAM_LB_N <= '0'; SRAM_CE_N <= '0'; SRAM_OE_N <= '0'; - SRAM_DQ(15 downto 8) <= (others => '0'); -- Synchronous outputs to SRAM process(clock,reset_n,ram_enable,cpu_r_nw) @@ -1152,10 +1172,10 @@ begin if reset_n = '0' then SRAM_WE_N <= '1'; - SRAM_DQ(7 downto 0) <= (others => 'Z'); + SRAM_DQ(15 downto 0) <= (others => 'Z'); elsif rising_edge(clock) then -- Default to inputs - SRAM_DQ(7 downto 0) <= (others => 'Z'); + SRAM_DQ(15 downto 0) <= (others => 'Z'); -- Register SRAM signals to outputs (clock must be at least 2x CPU clock) if vid_clken = '1' then @@ -1164,6 +1184,7 @@ begin SRAM_ADDR <= "00" & cpu_a(15 downto 0); if ram_write = '1' then SRAM_DQ(7 downto 0) <= cpu_do; + SRAM_DQ(15 downto 0) <=(others =>'0'); end if; else -- Fetch data from previous display cycle @@ -1236,7 +1257,7 @@ begin -- Connections to System VIA -- ADC - sys_via_cb1_in <= '1'; -- /EOC + sys_via_cb1_in <= '1'; -- EOC -- CRTC sys_via_ca1_in <= crtc_vsync; sys_via_cb2_in <= crtc_lpstb; @@ -1254,6 +1275,7 @@ begin -- Connections to User VIA (user port is output on green LEDs) user_via_ca1_in <= '1'; -- Pulled up --LEDG <= user_via_pb_out; + LEDG <= (others => '0'); -- MMBEEB user_via_cb1_in <= user_via_pb_out(1); @@ -1304,7 +1326,14 @@ begin -- DEBUG STUFF ----------------- + DRAM_DQ <= (others => 'Z'); + DRAM_DQ <= (others => 'Z'); + GPIO_0(0) <= not (crtc_hsync xor crtc_vsync); GPIO_0(1) <= crtc_de; + GPIO_0(2) <= ld_vsync; + GPIO_0(3) <= ld_hsync; + GPIO_0(35 downto 4) <= (others => '0'); + GPIO_1 <= (others => '0'); end architecture; diff --git a/quartus/keyboard.vhd b/quartus/keyboard.vhd index c0b8603..4f736b6 100644 --- a/quartus/keyboard.vhd +++ b/quartus/keyboard.vhd @@ -72,6 +72,7 @@ port ( ); end entity; +-- altera message_off 10036 architecture rtl of keyboard is -- PS/2 interface @@ -149,6 +150,13 @@ begin KEYPRESS <= '0'; end if; end process; + + keys(10) <= (others => '0'); + keys(11) <= (others => '0'); + keys(12) <= (others => '0'); + keys(13) <= (others => '0'); + keys(14) <= (others => '0'); + keys(15) <= (others => '0'); -- Decode PS/2 data process(CLOCK,nRESET) @@ -170,12 +178,6 @@ begin keys(8) <= (others => '0'); keys(9) <= (others => '0'); -- These non-existent rows are used in the BBC master - keys(10) <= (others => '0'); - keys(11) <= (others => '0'); - keys(12) <= (others => '0'); - keys(13) <= (others => '0'); - keys(14) <= (others => '0'); - keys(15) <= (others => '0'); elsif rising_edge(CLOCK) then -- Copy DIP switches through to row 0 keys(2)(0) <= DIP_SWITCH(7); -- cgit v1.2.3